Changeset fcee56c0 in rtems for c/src/lib/libcpu/powerpc/shared


Ignore:
Timestamp:
07/01/99 23:39:13 (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
258fd79
Parents:
2a6a029
Message:

Patch from Eric Valette <valette@…> to clean up the
previous submission.

Location:
c/src/lib/libcpu/powerpc/shared
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/shared/Makefile.in

    r2a6a029 rfcee56c0  
    1515C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
    1616
    17 H_FILES=$(srcdir)/cpu.h $(srcdir)/spr.h $(srcdir)/io.h $(srcdir)/mmu.h $(srcdir)/page.h $(srcdir)/byteorder.h $(srcdir)/pgtable.h $(srcdir)/processor.h
     17H_FILES=$(srcdir)/cpu.h $(srcdir)/spr.h $(srcdir)/io.h $(srcdir)/mmu.h $(srcdir)/page.h $(srcdir)/byteorder.h $(srcdir)/pgtable.h
    1818
    1919# Assembly source names, if any, go here -- minus the .s
  • c/src/lib/libcpu/powerpc/shared/byteorder.h

    r2a6a029 rfcee56c0  
     1/*
     2 * byteorder.h
     3 *
     4 *        This file contains inline implementation of function to
     5 *          deal with endian conversion.
     6 *
     7 * It is a stripped down version of linux ppc file...
     8 *
     9 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     10 *                     Canon Centre Recherche France.
     11 *
     12 *  The license and distribution terms for this file may be
     13 *  found in found in the file LICENSE in this distribution or at
     14 *  http://www.OARcorp.com/rtems/license.html.
     15 *
     16 *  $Id$
     17 */
     18
    119#ifndef _PPC_BYTEORDER_H
    220#define _PPC_BYTEORDER_H
  • c/src/lib/libcpu/powerpc/shared/cpu.h

    r2a6a029 rfcee56c0  
     1/*
     2 * cpu.h
     3 *
     4 *          This file contains some powerpc MSR and registers access definitions.
     5 *
     6 * It is a stripped down version of linux ppc processor.h file...
     7 *
     8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     9 *                     Canon Centre Recherche France.
     10 *
     11 *  The license and distribution terms for this file may be
     12 *  found in found in the file LICENSE in this distribution or at
     13 *  http://www.OARcorp.com/rtems/license.html.
     14 *
     15 *  $Id$
     16 */
     17
    118#ifndef __ASM_PPC_PROCESSOR_H
    219#define __ASM_PPC_PROCESSOR_H
  • c/src/lib/libcpu/powerpc/shared/io.h

    r2a6a029 rfcee56c0  
     1/*
     2 * io.h
     3 *
     4 *          This file contains inline implementation of function to
     5 *          deal with IO.
     6 *
     7 * It is a stripped down version of linux ppc file...
     8 *
     9 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     10 *                     Canon Centre Recherche France.
     11 *
     12 *  The license and distribution terms for this file may be
     13 *  found in found in the file LICENSE in this distribution or at
     14 *  http://www.OARcorp.com/rtems/license.html.
     15 *
     16 *  $Id$
     17 */
    118#ifndef _LIBCPU_IO_H_
    219#define _LIBCPU_IO_H_
  • c/src/lib/libcpu/powerpc/shared/mmu.h

    r2a6a029 rfcee56c0  
    11/*
    2  * PowerPC memory management structures
     2 * mmu.h
     3 *
     4 *      PowerPC memory management structures
     5 *
     6 * It is a stripped down version of linux ppc file...
     7 *
     8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     9 *                     Canon Centre Recherche France.
     10 *
     11 *  The license and distribution terms for this file may be
     12 *  found in found in the file LICENSE in this distribution or at
     13 *  http://www.OARcorp.com/rtems/license.html.
     14 *
     15 *  $Id$
    316 */
    417
  • c/src/lib/libcpu/powerpc/shared/page.h

    r2a6a029 rfcee56c0  
     1/*
     2 * page.h
     3 *
     4 *      PowerPC memory management structures
     5 *
     6 * It is a stripped down version of linux ppc file...
     7 *
     8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     9 *                     Canon Centre Recherche France.
     10 *
     11 *  The license and distribution terms for this file may be
     12 *  found in found in the file LICENSE in this distribution or at
     13 *  http://www.OARcorp.com/rtems/license.html.
     14 *
     15 *  $Id$
     16 */
     17
    118#ifndef _PPC_PAGE_H
    219#define _PPC_PAGE_H
  • c/src/lib/libcpu/powerpc/shared/pgtable.h

    r2a6a029 rfcee56c0  
     1/*
     2 * pgtable.h
     3 *
     4 *      PowerPC memory management structures
     5 *
     6 * It is a stripped down version of linux ppc file...
     7 *
     8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
     9 *                     Canon Centre Recherche France.
     10 *
     11 *  The license and distribution terms for this file may be
     12 *  found in found in the file LICENSE in this distribution or at
     13 *  http://www.OARcorp.com/rtems/license.html.
     14 *
     15 *  $Id$
     16 */
     17
    118#ifndef _PPC_PGTABLE_H
    219#define _PPC_PGTABLE_H
  • c/src/lib/libcpu/powerpc/shared/processor.h

    r2a6a029 rfcee56c0  
    1 #ifndef __ASM_PPC_PROCESSOR_H
    2 #define __ASM_PPC_PROCESSOR_H
    3 
    4 #include <bsp/residual.h>
    5 
    6 /* Bit encodings for Machine State Register (MSR) */
    7 #define MSR_POW         (1<<18)         /* Enable Power Management */
    8 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
    9 #define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
    10 #define MSR_EE          (1<<15)         /* External Interrupt enable */
    11 #define MSR_PR          (1<<14)         /* Supervisor/User privilege */
    12 #define MSR_FP          (1<<13)         /* Floating Point enable */
    13 #define MSR_ME          (1<<12)         /* Machine Check enable */
    14 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
    15 #define MSR_SE          (1<<10)         /* Single Step */
    16 #define MSR_BE          (1<<9)          /* Branch Trace */
    17 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
    18 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
    19 #define MSR_IR          (1<<5)          /* Instruction MMU enable */
    20 #define MSR_DR          (1<<4)          /* Data MMU enable */
    21 #define MSR_RI          (1<<1)          /* Recoverable Exception */
    22 #define MSR_LE          (1<<0)          /* Little-Endian enable */
    23 
    24 #define MSR_            MSR_ME|MSR_RI
    25 #define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
    26 #define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
    27 
    28 /* Bit encodings for Hardware Implementation Register (HID0)
    29    on PowerPC 603, 604, etc. processors (not 601). */
    30 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
    31 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
    32 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
    33 #define HID0_SBCLK      (1<<27)
    34 #define HID0_EICE       (1<<26)
    35 #define HID0_ECLK       (1<<25)
    36 #define HID0_PAR        (1<<24)
    37 #define HID0_DOZE       (1<<23)
    38 #define HID0_NAP        (1<<22)
    39 #define HID0_SLEEP      (1<<21)
    40 #define HID0_DPM        (1<<20)
    41 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
    42 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
    43 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
    44 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
    45 #define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
    46 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
    47 #define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
    48 #define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
    49 #define HID0_BTCD       (1<<1)          /* Branch target cache disable */
    50 
    51 /* fpscr settings */
    52 #define FPSCR_FX        (1<<31)
    53 #define FPSCR_FEX       (1<<30)
    54 
    55 #define _MACH_prep     1
    56 #define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
    57 #define _MACH_chrp     4 /* chrp machine */
    58 #define _MACH_mbx      8 /* Motorola MBX board */
    59 #define _MACH_apus    16 /* amiga with phase5 powerup */
    60 #define _MACH_fads    32 /* Motorola FADS board */
    61 
    62 /* see residual.h for these */
    63 #define _PREP_Motorola 0x01  /* motorola prep */
    64 #define _PREP_Firm     0x02  /* firmworks prep */
    65 #define _PREP_IBM      0x00  /* ibm prep */
    66 #define _PREP_Bull     0x03  /* bull prep */
    67 
    68 /* these are arbitrary */
    69 #define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
    70 #define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
    71 
    72 #define _GLOBAL(n)\
    73         .globl n;\
    74 n:
    75 
    76 #define TBRU    269     /* Time base Upper/Lower (Reading) */
    77 #define TBRL    268
    78 #define TBWU    284     /* Time base Upper/Lower (Writing) */
    79 #define TBWL    285
    80 #define XER     1
    81 #define LR      8
    82 #define CTR     9
    83 #define HID0    1008    /* Hardware Implementation */
    84 #define PVR     287     /* Processor Version */
    85 #define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
    86 #define IBAT0L  529
    87 #define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
    88 #define IBAT1L  531
    89 #define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
    90 #define IBAT2L  533
    91 #define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
    92 #define IBAT3L  535
    93 #define DBAT0U  536     /* Data BAT #0 Upper/Lower */
    94 #define DBAT0L  537
    95 #define DBAT1U  538     /* Data BAT #1 Upper/Lower */
    96 #define DBAT1L  539
    97 #define DBAT2U  540     /* Data BAT #2 Upper/Lower */
    98 #define DBAT2L  541
    99 #define DBAT3U  542     /* Data BAT #3 Upper/Lower */
    100 #define DBAT3L  543
    101 #define DMISS   976     /* TLB Lookup/Refresh registers */
    102 #define DCMP    977
    103 #define HASH1   978
    104 #define HASH2   979
    105 #define IMISS   980
    106 #define ICMP    981
    107 #define RPA     982
    108 #define SDR1    25      /* MMU hash base register */
    109 #define DAR     19      /* Data Address Register */
    110 #define SPR0    272     /* Supervisor Private Registers */
    111 #define SPRG0   272
    112 #define SPR1    273
    113 #define SPRG1   273
    114 #define SPR2    274
    115 #define SPRG2   274
    116 #define SPR3    275
    117 #define SPRG3   275
    118 #define DSISR   18
    119 #define SRR0    26      /* Saved Registers (exception) */
    120 #define SRR1    27
    121 #define IABR    1010    /* Instruction Address Breakpoint */
    122 #define DEC     22      /* Decrementer */
    123 #define EAR     282     /* External Address Register */
    124 #define L2CR    1017    /* PPC 750 L2 control register */
    125 
    126 #define THRM1   1020
    127 #define THRM2   1021
    128 #define THRM3   1022
    129 #define THRM1_TIN 0x1
    130 #define THRM1_TIV 0x2
    131 #define THRM1_THRES (0x7f<<2)
    132 #define THRM1_TID (1<<29)
    133 #define THRM1_TIE (1<<30)
    134 #define THRM1_V   (1<<31)
    135 #define THRM3_E   (1<<31)
    136 
    137 /* Segment Registers */
    138 #define SR0     0
    139 #define SR1     1
    140 #define SR2     2
    141 #define SR3     3
    142 #define SR4     4
    143 #define SR5     5
    144 #define SR6     6
    145 #define SR7     7
    146 #define SR8     8
    147 #define SR9     9
    148 #define SR10    10
    149 #define SR11    11
    150 #define SR12    12
    151 #define SR13    13
    152 #define SR14    14
    153 #define SR15    15
    154 
    155 #endif /* __ASM_PPC_PROCESSOR_H */
    156 
    157 
    158 
    159 
    160 
    161 
    162 
  • c/src/lib/libcpu/powerpc/shared/spr.h

    r2a6a029 rfcee56c0  
    11/*
    2  *  include/asm-ppc/spr.h -- Access to special purpose registers.
     2 *  spr.h -- Access to special purpose registers.
    33 *
    44 *  Copyright (C) 1998 Gabriel Paubert, paubert@iram.es
    55 *
    6  *  This file is subject to the terms and conditions of the GNU General Public
    7  *  License.  See the file COPYING in the main directory of this archive
    8  *  for more details.
     6 *  Modified to compile in RTEMS development environment
     7 *  by Eric Valette
     8 *
     9 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     10 *
     11 *  The license and distribution terms for this file may be
     12 *  found in found in the file LICENSE in this distribution or at
     13 *  http://www.OARcorp.com/rtems/license.html.
     14 *
     15 * $Id$
     16 *
    917 */
    1018
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