Changeset fc82e71 in rtems
- Timestamp:
- 02/08/02 21:26:00 (22 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 14c2084
- Parents:
- fb63984
- Location:
- c/src/lib/libbsp/mips/shared/gdbstub
- Files:
-
- 5 deleted
- 3 edited
- 2 moved
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/mips/shared/gdbstub/ChangeLog
rfb63984 rfc82e71 1 2002-02-08 Joel Sherrill <joel@OARcorp.com> 2 3 * Makefile, stubinit.S, r46kstub.ld, ioaddr.h: Removed as unused 4 with RTEMS. 5 * r46kstub.c: Renamed to mips-stub.c. 6 * mips-stub.c: New file -- was r46kstub.c. 7 * memlimits.h: New file was limits.h. 8 * limits.h: Removed. 9 * r4600.h: Eliminated need for this file. 10 * README: Updated. 11 * gdb_if.h: Added CVS Id. 12 * mips-stub.c: Attempt to deal with MIPS1 versus MIPS3. 13 1 14 2002-02-08 Joel Sherrill <joel@OARcorp.com> 2 15 -
c/src/lib/libbsp/mips/shared/gdbstub/README
rfb63984 rfc82e71 1 /* r46kstub 9/29/96 c. m. heard */ 2 /* 7/26/96 -- original posting */ 3 /* 8/06/96 -- cache initialization/flushing logic fixed */ 4 /* 9/29/96 -- coprocessor load delay slots respected, documentation improved */ 1 # 2 # $Id$ 3 # 4 5 6 The contents of this directory are based upon the "r46kstub.tar.gz" package 7 released to the net by 8 9 C. M. Heard 10 VVNET, Inc. phone: +1 408 247 9376 11 4040 Moorpark Ave. Suite 206 fax: +1 408 244 3651 12 San Jose, CA 95117 USA e-mail: heard@vvnet.com 13 14 This package was released in the September 1996 time frame for use 15 with gdb 4.16 and an IDT R4600 Orion. The stub was modified to support 16 R3000 class CPUs and to work within the mips-rtems exeception processing 17 framework. 18 19 THe file memlimits.h could end up being target board dependent. If 20 this is the case, copy it to your BSP directory and modify as necessary. 21 22 --joel 23 8 February 2002 24 25 Original README 26 =============== 5 27 6 28 The r46kstub directory and its compressed archive (r46kstub.tar.gz) contain … … 109 131 110 132 Please send bug reports, comments, or suggestions for improvement to: 111 112 C. M. Heard113 VVNET, Inc. phone: +1 408 247 9376114 4040 Moorpark Ave. Suite 206 fax: +1 408 244 3651115 San Jose, CA 95117 USA e-mail: heard@vvnet.com -
c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h
rfb63984 rfc82e71 11 11 * REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES 12 12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * $Id$ 13 15 */ 14 16 … … 17 19 18 20 /* 19 * R4600registers, numbered in the order in which gdb expects to see them.21 * MIPS registers, numbered in the order in which gdb expects to see them. 20 22 */ 21 23 #define ZERO 0 -
c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
rfb63984 rfc82e71 10 10 REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES 11 11 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 12 13 $Id$ 12 14 13 15 ******************************************************************************** … … 122 124 #include <signal.h> 123 125 #include "mips_opcode.h" 124 #include " r4600.h"125 #include "limits.h"126 #include "memlimits.h" 127 #include <rtems.h> 126 128 #include "gdb_if.h" 127 129 130 /***************/ 131 /* Exception Codes */ 132 #define EXC_INT 0 /* External interrupt */ 133 #define EXC_MOD 1 /* TLB modification exception */ 134 #define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */ 135 #define EXC_TLBS 3 /* TLB miss (Store) */ 136 #define EXC_ADEL 4 /* Address error (Load or Ifetch) */ 137 #define EXC_ADES 5 /* Address error (Store) */ 138 #define EXC_IBE 6 /* Bus error (Ifetch) */ 139 #define EXC_DBE 7 /* Bus error (data load or store) */ 140 #define EXC_SYS 8 /* System call */ 141 #define EXC_BP 9 /* Break point */ 142 #define EXC_RI 10 /* Reserved instruction */ 143 #define EXC_CPU 11 /* Coprocessor unusable */ 144 #define EXC_OVF 12 /* Arithmetic overflow */ 145 #define EXC_TRAP 13 /* Trap exception */ 146 #define EXC_FPE 15 /* Floating Point Exception */ 147 148 /* FPU Control/Status register fields */ 149 #define CSR_FS 0x01000000 /* Set to flush denormals to zero */ 150 #define CSR_C 0x00800000 /* Condition bit (set by FP compare) */ 151 152 #define CSR_CMASK (0x3f<<12) 153 #define CSR_CE 0x00020000 154 #define CSR_CV 0x00010000 155 #define CSR_CZ 0x00008000 156 #define CSR_CO 0x00004000 157 #define CSR_CU 0x00002000 158 #define CSR_CI 0x00001000 159 160 #define CSR_EMASK (0x1f<<7) 161 #define CSR_EV 0x00000800 162 #define CSR_EZ 0x00000400 163 #define CSR_EO 0x00000200 164 #define CSR_EU 0x00000100 165 #define CSR_EI 0x00000080 166 167 #define CSR_FMASK (0x1f<<2) 168 #define CSR_FV 0x00000040 169 #define CSR_FZ 0x00000020 170 #define CSR_FO 0x00000010 171 #define CSR_FU 0x00000008 172 #define CSR_FI 0x00000004 173 174 #define CSR_RMODE_MASK (0x3<<0) 175 #define CSR_RM 0x00000003 176 #define CSR_RP 0x00000002 177 #define CSR_RZ 0x00000001 178 #define CSR_RN 0x00000000 179 180 /***************/ 128 181 129 182 /* … … 131 184 * preprocessor before handle_exception is invoked. 132 185 */ 133 extern long long registers[NUM_REGS]; 186 #if (__mips == 3) 187 typedef long long mips_register_t; 188 #elif (__mips == 1) 189 typedef unsigned int mips_register_t; 190 #else 191 #error "unknown MIPS ISA" 192 #endif 193 static mips_register_t *registers; 134 194 135 195 … … 728 788 */ 729 789 void 730 handle_exception ( void)790 handle_exception (CPU_Interrupt_frame *frame) 731 791 { 732 792 int host_has_detached = 0; … … 735 795 long long regval; 736 796 char *ptr; 797 798 registers = (mips_register_t *)frame; 737 799 738 800 /* reply to host that an exception has occurred */ … … 763 825 outBuffer[2] = lowhex (sigval); 764 826 outBuffer[3] = '\0'; 827 break; 828 829 case 'd': 830 /* toggle debug flag */ 765 831 break; 766 832
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