Changeset fc76056e in rtems


Ignore:
Timestamp:
Dec 20, 2013, 1:01:12 PM (5 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
80b9c8ac
Parents:
9d88008
git-author:
Daniel Hellstrom <daniel@…> (12/20/13 13:01:12)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:20)
Message:

GR-RASTA-TMTC: updated for new version

From this driver's point of view the major new thing is that the
GRPCI peripheral PCI bridge has been updated to GRPCI2, the second
version. This means that both Big and Little Endian systems are now
supported and autodetected on runtime.

The PCI frequency is used as AMBA frequency of the GR-RASTA-TMTC.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c

    r9d88008 rfc76056e  
    4545#define AHB1_BASE_ADDR 0x80000000
    4646#define AHB1_IOAREA_BASE_ADDR 0x80200000
     47#define AHB1_IOAREA_OFS (AHB1_IOAREA_BASE_ADDR - AHB1_BASE_ADDR)
     48
     49/* Second revision constants (GRPCI2) */
     50#define GRPCI2_BAR0_TO_AHB_MAP 0x04  /* Fixme */
     51#define GRPCI2_BAR1_TO_AHB_MAP 0x08  /* Fixme */
     52#define GRPCI2_PCI_CONFIG      0x20  /* Fixme */
    4753
    4854/* #define DEBUG 1 */
     
    6773};
    6874
     75struct grpci2_regs {
     76        volatile unsigned int ctrl;
     77        volatile unsigned int statcap;
     78        volatile unsigned int pcimstprefetch;
     79        volatile unsigned int ahbtopciiomap;
     80        volatile unsigned int dmactrl;
     81        volatile unsigned int dmadesc;
     82        volatile unsigned int dmachanact;
     83        volatile unsigned int reserved;
     84        volatile unsigned int pcibartoahb[6];
     85        volatile unsigned int reserved2[2];
     86        volatile unsigned int ahbtopcimemmap[16];
     87        volatile unsigned int trcctrl;
     88        volatile unsigned int trccntmode;
     89        volatile unsigned int trcadpat;
     90        volatile unsigned int trcadmask;
     91        volatile unsigned int trcctrlsigpat;
     92        volatile unsigned int trcctrlsigmask;
     93        volatile unsigned int trcadstate;
     94        volatile unsigned int trcctrlsigstate;
     95};
     96
    6997struct gr_rasta_tmtc_ver {
    7098        const unsigned int      amba_freq_hz;   /* The frequency */
     
    90118        struct irqmp_regs               *irq;
    91119        struct grpci_regs               *grpci;
     120        struct grpci2_regs              *grpci2;
    92121        struct grgpio_regs              *gpio;
    93122        struct drvmgr_map_entry         bus_maps_down[3];
     
    216245}
    217246
     247/* PCI Hardware (Revision 0) initialization */
    218248int gr_rasta_tmtc_hw_init(struct gr_rasta_tmtc_priv *priv)
    219249{
     
    381411
    382412        /* Successfully registered the RASTA board */
     413        return 0;
     414}
     415
     416/* PCI Hardware (Revision 1) initialization */
     417int gr_rasta_tmtc1_hw_init(struct gr_rasta_tmtc_priv *priv)
     418{
     419        int i;
     420        uint32_t data;
     421        unsigned int ctrl;
     422        uint8_t tmp2;
     423        struct ambapp_dev *tmp;
     424        int status;
     425        struct ambapp_ahb_info *ahb;
     426        uint8_t cap_ptr;
     427        pci_dev_t pcidev = priv->pcidev;
     428        struct pci_dev_info *devinfo = priv->devinfo;
     429        unsigned int pci_freq_hz;
     430
     431        /* Check capabilities list bit */
     432        pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
     433
     434        if (!((tmp2 >> 4) & 1)) {
     435                /* Capabilities list not available which it should be in the
     436                 * GRPCI2
     437                 */
     438                return -3;
     439        }
     440
     441        /* Read capabilities pointer */
     442        pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
     443
     444        /* Set AHB address mappings for target PCI bars
     445         * BAR0: 16MB  : Mapped to I/O at 0x80000000
     446         * BAR1: 256MB : Mapped to MEM at 0x40000000
     447         */
     448        pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, AHB1_BASE_ADDR);
     449        pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR1_TO_AHB_MAP, 0x40000000);
     450
     451        /* Set PCI bus to be same endianess as PCI system */
     452        pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data);
     453        if (pci_endian == PCI_BIG_ENDIAN)
     454                data = data & 0xFFFFFFFE;
     455        else
     456                data = data | 0x00000001;
     457        pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data);
     458
     459#if 0
     460        /* set parity error response */
     461        pci_cfg_r32(pcidev, PCI_COMMAND, &data);
     462        pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
     463#endif
     464
     465        /* Scan AMBA Plug&Play */
     466
     467        /* AMBA MAP bar0 (in PCI) ==> 0x40000000 (remote amba address) */
     468        priv->amba_maps[0].size = devinfo->resources[0].size;
     469        priv->amba_maps[0].local_adr = devinfo->resources[0].address;
     470        priv->amba_maps[0].remote_adr = AHB1_BASE_ADDR;
     471
     472        /* AMBA MAP bar0 (in PCI) ==> 0x80000000 (remote amba address) */
     473        priv->amba_maps[1].size = devinfo->resources[1].size;
     474        priv->amba_maps[1].local_adr = devinfo->resources[1].address;
     475        priv->amba_maps[1].remote_adr = 0x40000000;
     476
     477        /* Addresses not matching with map be untouched */
     478        priv->amba_maps[2].size = 0xfffffff0;
     479        priv->amba_maps[2].local_adr = 0;
     480        priv->amba_maps[2].remote_adr = 0;
     481
     482        /* Mark end of table */
     483        priv->amba_maps[3].size=0;
     484
     485        /* Start AMBA PnP scan at first AHB bus */
     486        ambapp_scan(
     487                &priv->abus,
     488                devinfo->resources[0].address + AHB1_IOAREA_OFS,
     489                NULL,
     490                &priv->amba_maps[0]);
     491
     492        /* Initialize Frequency of AMBA bus. The AMBA bus runs at same
     493         * frequency as PCI bus
     494         */
     495        drvmgr_freq_get(priv->dev, 0, &pci_freq_hz);
     496        ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
     497
     498        /* Find IRQ controller, Clear all current IRQs */
     499        tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus,
     500                                (OPTIONS_ALL|OPTIONS_APB_SLVS),
     501                                VENDOR_GAISLER, GAISLER_IRQMP,
     502                                ambapp_find_by_idx, NULL);
     503        if ( !tmp ) {
     504                return -4;
     505        }
     506        priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
     507        /* Set up GR-RASTA-SPW-ROUTER irq controller */
     508        priv->irq->mask[0] = 0;
     509        priv->irq->iclear = 0xffff;
     510        priv->irq->ilevel = 0;
     511
     512        priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
     513        priv->bus_maps_down[0].size = priv->amba_maps[0].size;
     514        priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
     515        priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
     516        priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
     517        priv->bus_maps_down[1].size = priv->amba_maps[1].size;
     518        priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
     519        priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
     520        priv->bus_maps_down[2].size = 0;
     521
     522        /* Find GRPCI2 controller AHB Slave interface */
     523        tmp = (void *)ambapp_for_each(&priv->abus,
     524                                        (OPTIONS_ALL|OPTIONS_AHB_SLVS),
     525                                        VENDOR_GAISLER, GAISLER_GRPCI2,
     526                                        ambapp_find_by_idx, NULL);
     527        if ( !tmp ) {
     528                return -5;
     529        }
     530        ahb = (struct ambapp_ahb_info *)tmp->devinfo;
     531        priv->bus_maps_up[0].name = "AMBA GRPCI2 Window";
     532        priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-SPW-ROUTER board */
     533        priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
     534        priv->bus_maps_up[0].to_adr = (void *)
     535                                (priv->ahbmst2pci_map & ~(ahb->mask[0]-1));
     536        priv->bus_maps_up[1].size = 0;
     537
     538        /* Find GRPCI2 controller APB Slave interface */
     539        tmp = (void *)ambapp_for_each(&priv->abus,
     540                                        (OPTIONS_ALL|OPTIONS_APB_SLVS),
     541                                        VENDOR_GAISLER, GAISLER_GRPCI2,
     542                                        ambapp_find_by_idx, NULL);
     543        if ( !tmp ) {
     544                return -6;
     545        }
     546        priv->grpci2 = (struct grpci2_regs *)
     547                ((struct ambapp_apb_info *)tmp->devinfo)->start;
     548
     549        /* Set AHB to PCI mapping for all AMBA AHB masters */
     550        for(i = 0; i < 16; i++) {
     551                priv->grpci2->ahbtopcimemmap[i] = priv->ahbmst2pci_map &
     552                                                        ~(ahb->mask[0]-1);
     553        }
     554
     555        /* Make sure dirq(0) sampling is enabled */
     556        ctrl = priv->grpci2->ctrl;
     557        ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4);
     558        priv->grpci2->ctrl = ctrl;
     559
     560        /* Successfully registered the RASTA-SPW-ROUTER board */
    383561        return 0;
    384562}
     
    456634                return DRVMGR_FAIL;
    457635
    458         status = gr_rasta_tmtc_hw_init(priv);
     636        /* Select version of GR-RASTA-IO board */
     637        switch (devinfo->rev) {
     638                case 0:
     639                        puts("GR-RASTA-TMTC: REVISION 0");
     640                        status = gr_rasta_tmtc_hw_init(priv);
     641                        break;
     642                case 1:
     643                        puts("GR-RASTA-TMTC: REVISION 1");
     644                        status = gr_rasta_tmtc1_hw_init(priv);
     645                        break;
     646                default:
     647                        return DRVMGR_ENOSYS; /* HW not supported */
     648        }
     649
    459650        if ( status != 0 ) {
    460651                genirq_destroy(priv->genirq);
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