Changeset fc63544 in rtems
- Timestamp:
- Nov 22, 2004, 10:40:25 PM (16 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 712fe15
- Parents:
- bb15d1d2
- Location:
- cpukit/score/cpu/powerpc
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/powerpc/ChangeLog
rbb15d1d2 rfc63544 1 2004-11-22 Joel Sherrill <joel@OARcorp.com> 2 3 * rtems/old-exceptions/cpu.h: Make compile in assembly. 4 1 5 2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> 2 6 -
cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h
rbb15d1d2 rfc63544 327 327 */ 328 328 329 #ifndef ASM 329 330 typedef struct { 330 331 uint32_t gpr1; /* Stack pointer for all */ … … 442 443 #endif 443 444 } rtems_cpu_table; 445 #endif 444 446 445 447 /* … … 452 454 */ 453 455 456 #ifndef ASM 454 457 #define rtems_cpu_configuration_get_clicks_per_usec() \ 455 458 (_CPU_Table.clicks_per_usec) … … 494 497 #endif 495 498 499 #endif 496 500 497 501 /* … … 504 508 */ 505 509 510 #ifndef ASM 506 511 typedef struct { 507 512 uint32_t stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ … … 510 515 uint32_t b_Handler; /* b PROC (_ISR_Handler) */ 511 516 } CPU_Trap_table_entry; 517 #endif 512 518 513 519 /* … … 518 524 */ 519 525 526 #ifndef ASM 520 527 /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ 528 #endif 521 529 522 530 /* … … 533 541 */ 534 542 543 #ifndef ASM 535 544 SCORE_EXTERN void *_CPU_Interrupt_stack_low; 536 545 SCORE_EXTERN void *_CPU_Interrupt_stack_high; 546 #endif 537 547 538 548 /* … … 546 556 */ 547 557 558 #ifndef ASM 548 559 /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ 560 #endif 549 561 550 562 /* … … 553 565 554 566 567 #ifndef ASM 555 568 SCORE_EXTERN struct { 556 569 uint32_t volatile* Nest_level; … … 571 584 uint32_t msr_initial; 572 585 } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; 586 #endif 573 587 574 588 /* … … 669 683 */ 670 684 685 #ifndef ASM 671 686 void _CPU_Initialize_vectors(void); 687 #endif 672 688 673 689 /* … … 676 692 */ 677 693 694 #ifndef ASM 678 695 #define _CPU_MSR_Value( _msr_value ) \ 679 696 do { \ … … 716 733 ); \ 717 734 } 735 #endif 718 736 719 737 /* … … 723 741 */ 724 742 743 #ifndef ASM 725 744 #define _CPU_ISR_Enable( _isr_cookie ) \ 726 745 { \ … … 729 748 "0" ((_isr_cookie))); \ 730 749 } 750 #endif 731 751 732 752 /* … … 741 761 */ 742 762 763 #ifndef ASM 743 764 #define _CPU_ISR_Flash( _isr_cookie ) \ 744 765 { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ … … 749 770 ); \ 750 771 } 772 #endif 751 773 752 774 /* … … 761 783 */ 762 784 785 #ifndef ASM 763 786 uint32_t _CPU_ISR_Calculate_level( 764 787 uint32_t new_level … … 776 799 proc_ptr *old_handler 777 800 ); 801 #endif 778 802 779 803 /* end of ISR handler macros */ … … 783 807 * This is very dependent on the clock speed of the target. 784 808 */ 809 810 #ifndef ASM 785 811 786 812 #define CPU_Get_timebase_low( _value ) \ … … 806 832 } while (0) 807 833 834 #endif 808 835 809 836 … … 828 855 */ 829 856 857 #ifndef ASM 830 858 void _CPU_Context_Initialize( 831 859 Context_Control *the_context, … … 836 864 boolean is_fp 837 865 ); 866 #endif 838 867 839 868 /* … … 987 1016 /* variables */ 988 1017 1018 #ifndef ASM 989 1019 extern const uint32_t _CPU_msrs[4]; 1020 #endif 990 1021 991 1022 /* functions */ 1023 1024 #ifndef ASM 992 1025 993 1026 /* … … 1143 1176 } 1144 1177 1178 /* ASM */ 1179 #endif 1180 1145 1181 #ifdef __cplusplus 1146 1182 }
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