Changeset fc63544 in rtems

Timestamp:

Nov 22, 2004, 10:40:25 PM (15 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, master

Children:

712fe15

Parents:

bb15d1d2

Message:

2004-11-22 Joel Sherrill <joel@…>

• rtems/old-exceptions/cpu.h: Make compile in assembly.

Location:

cpukit/score/cpu/powerpc

Files:

• ChangeLog (modified) (1 diff)
• rtems/old-exceptions/cpu.h (modified) (26 diffs)

cpukit/score/cpu/powerpc/ChangeLog

@@ +1 @@
+2004-11-22      Joel Sherrill <joel@OARcorp.com>
+
+        * rtems/old-exceptions/cpu.h: Make compile in assembly.
+
 2004-11-21      Ralf Corsepius <ralf.corsepius@rtems.org>
 

cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h

@@ -327 +327 @@
  */
 
+#ifndef ASM
 typedef struct {
     uint32_t   gpr1;    /* Stack pointer for all */
@@ -442 +443 @@
 #endif
 }   rtems_cpu_table;
+#endif
 
 /*
@@ -452 +454 @@
  */
 
+#ifndef ASM
 #define rtems_cpu_configuration_get_clicks_per_usec() \
    (_CPU_Table.clicks_per_usec)
@@ -494 +497 @@
 #endif
 
+#endif
 
 /*
@@ -504 +508 @@
  */
  
+#ifndef ASM
 typedef struct {
   uint32_t     stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
@@ -510 +515 @@
   uint32_t     b_Handler;                     /* b     PROC (_ISR_Handler)  */
 } CPU_Trap_table_entry;
+#endif
 
 /*
@@ -518 +524 @@
  */
 
+#ifndef ASM
 /* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
+#endif
 
 /*
@@ -533 +541 @@
  */
 
+#ifndef ASM
 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+#endif
 
 /*
@@ -546 +556 @@
  */
 
+#ifndef ASM
 /* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
+#endif
 
 /*
@@ -553 +565 @@
 
 
+#ifndef ASM
 SCORE_EXTERN struct {
   uint32_t   volatile* Nest_level;
@@ -571 +584 @@
   uint32_t   msr_initial;
 } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
+#endif
 
 /*
@@ -669 +683 @@
  */
 
+#ifndef ASM
 void _CPU_Initialize_vectors(void);
+#endif
 
 /*
@@ -676 +692 @@
  */
 
+#ifndef ASM
 #define _CPU_MSR_Value( _msr_value ) \
   do { \
@@ -716 +733 @@
         ); \
   }
+#endif
 
 /*
@@ -723 +741 @@
  */
 
+#ifndef ASM
 #define _CPU_ISR_Enable( _isr_cookie )  \
   { \
@@ -729 +748 @@
                    "0" ((_isr_cookie))); \
   }
+#endif
 
 /*
@@ -741 +761 @@
  */
 
+#ifndef ASM
 #define _CPU_ISR_Flash( _isr_cookie ) \
   { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
@@ -749 +770 @@
     ); \
   }
+#endif
 
 /*
@@ -761 +783 @@
  */
 
+#ifndef ASM
 uint32_t   _CPU_ISR_Calculate_level(
   uint32_t   new_level
@@ -776 +799 @@
   proc_ptr   *old_handler
 );
+#endif
 
 /* end of ISR handler macros */
@@ -783 +807 @@
  *  This is very dependent on the clock speed of the target.
  */
+
+#ifndef ASM
 
 #define CPU_Get_timebase_low( _value ) \
@@ -806 +832 @@
   } while (0)
 
+#endif
 
 
@@ -828 +855 @@
  */
 
+#ifndef ASM
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -836 +864 @@
   boolean           is_fp
 );
+#endif
 
 /*
@@ -987 +1016 @@
 /* variables */
 
+#ifndef ASM
 extern const uint32_t   _CPU_msrs[4];
+#endif
 
 /* functions */
+
+#ifndef ASM
 
 /*
@@ -1143 +1176 @@
 }
 
+/* ASM */
+#endif
+
 #ifdef __cplusplus
 }