Changeset fb557a9 in rtems


Ignore:
Timestamp:
Oct 16, 2009, 4:42:03 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.9
Children:
1c2ea245
Parents:
af46ad9
Message:

2009-10-16 Jennifer Averett <jennifer@…>

  • Makefile.am, configure.ac, preinstall.am, console/alloc360.c, console/config.c, console/console.c, console/m68360.h, console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h, include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S, startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h: Updated and tested against RTEMS 4.9. Updated README file to latest source status. Modified to use the shared irq source code. Turned off debugging, cleaned up warnings, removed unused code. Tested with two PMCQ1 serial cards. Tested MC68360 serial ports and VME using external tests.
  • README, irq/irq.h, vme/vmeconfig.c: New files.
Location:
c/src/lib/libbsp/powerpc/ep1a
Files:
3 added
18 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ep1a/ChangeLog

    raf46ad9 rfb557a9  
     12009-10-16      Jennifer Averett <jennifer@OARcorp.com>
     2
     3        * Makefile.am, configure.ac, preinstall.am, console/alloc360.c,
     4        console/config.c, console/console.c, console/m68360.h,
     5        console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
     6        include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S,
     7        startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h:
     8        Updated and tested against RTEMS 4.9. Updated README file to latest
     9        source status. Modified to use the shared irq source code. Turned off
     10        debugging, cleaned up warnings, removed unused code. Tested with two
     11        PMCQ1 serial cards. Tested MC68360 serial ports and VME using
     12        external tests.
     13        * README, irq/irq.h, vme/vmeconfig.c: New files.
    1142008-12-08      Ralf Corsépius <ralf.corsepius@rtems.org>
    215
  • c/src/lib/libbsp/powerpc/ep1a/Makefile.am

    raf46ad9 rfb557a9  
    2323
    2424startup_SOURCES = startup/bspstart.c ../../shared/bootcard.c \
    25     ../../shared/bsppost.c ../../shared/bsppredriverhook.c \
    26     ../../shared/bsplibc.c ../../powerpc/shared/startup/sbrk.c \
    27     ../../shared/bspclean.c ../../shared/gnatinstallhandler.c \
    28     ../../powerpc/shared/startup/pgtbl_setup.c \
    29     ../../powerpc/shared/startup/pgtbl_activate.c \
    30     ../../powerpc/shared/showbats.c
     25    ../../shared/bspclean.c ../../shared/bsplibc.c \
     26    ../../shared/sbrk.c \
     27    ../../shared/gnatinstallhandler.c \
     28    ../../powerpc/shared/showbats.c \
     29    ../../shared/bsppost.c ../../shared/bsppredriverhook.c
     30
    3131
    3232pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
    33 
    34 include_bsp_HEADERS = ../../powerpc/shared/console/uart.h \
    35     ../../powerpc/shared/motorola/motorola.h \
    36     ../../powerpc/shared/residual/residual.h \
    37     ../../powerpc/shared/residual/pnp.h \
    38     ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
    3933console_SOURCES = console/console.c console/ns16550cfg.c \
    4034    console/mc68360_scc.c console/rsPMCQ1.c console/alloc360.c \
    4135    console/init68360.c
    4236
    43 include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
    44 openpic_SOURCES = ../../powerpc/shared/openpic/openpic.h \
    45     ../../powerpc/shared/openpic/openpic.c
     37include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
     38    ../../powerpc/shared/motorola/motorola.h \
     39     ../../powerpc/shared/residual/residual.h \
     40    ../../powerpc/shared/residual/pnp.h \
     41    ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
    4642
    47 include_bsp_HEADERS += ../../powerpc/shared/pci/pci.h
    4843pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
    49     ../../powerpc/shared/pci/pcifinddevice.c
     44        ../../powerpc/shared/pci/pcifinddevice.c
    5045
    51 include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
     46include_bsp_HEADERS += irq/irq.h \
    5247        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    5348        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    5449        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    55 irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c
     50
     51irq_SOURCES =  irq/irq.h  irq/irq_init.c irq/openpic_xxx_irq.c \
     52    ../../powerpc/shared/irq/i8259.c
     53   
     54include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
     55
     56openpic_SOURCES = ../../powerpc/shared/openpic/openpic.c
    5657
    5758include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
     
    6566vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \
    6667    ../../shared/vmeUniverse/bspVmeDmaList.c \
    67     ../shared/vme/vmeconfig.c \
     68    vme/vmeconfig.c \
    6869    ../shared/vme/vme_universe.c \
    6970    ../../shared/vmeUniverse/vme_am_defs.h
     
    7980project_lib_DATA += rtems_crti.$(OBJEXT)
    8081
     82EXTRA_DIST += README
     83
    8184noinst_LIBRARIES = libbsp.a
    82 libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \
    83     $(openpic_SOURCES) $(pci_SOURCES) $(irq_SOURCES) $(vme_SOURCES)
     85libbsp_a_SOURCES =  $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
     86    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) \
     87    $(openpic_SOURCES) $(vme_SOURCES)
    8488
    8589libbsp_a_LIBADD = \
  • c/src/lib/libbsp/powerpc/ep1a/configure.ac

    raf46ad9 rfb557a9  
    1616RTEMS_PROG_CCAS
    1717
     18RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
     19RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
     20[whether using console interrupts])
     21
     22RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
     23RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
     24[FIXME: Missing explanation])
     25
     26RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
     27RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
     28[If defined, then the PowerPC specific code in RTEMS will use some
     29of the special purpose registers to slightly optimize interrupt
     30response time.  The use of these registers can conflict with
     31other tools like debuggers.])
     32
    1833RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
    1934RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
     
    2540 The BSP actually contains the call that enables this.])
    2641
    27 RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
    28 RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
    29 [If defined, the instruction cache will be enabled after address translation
    30  is turned on.])
    31 
    32 RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
    33 RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
    34 [whether using console interrupts])
     42RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
     43RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
     44[This defines the base address of the exception table.
     45 NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
    3546
    3647RTEMS_CHECK_NETWORKING
  • c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c

    raf46ad9 rfb557a9  
    3535#if DEBUG_PRINT
    3636printk("m360->mcr:0x%08x  Q1_360_SIM_MCR:0x%08x\n",
    37        (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
     37       (uint32_t)&(m360->mcr), ((uint32_t)m360+Q1_360_SIM_MCR));
    3838#endif
    39   ptr->bdregions[0].base = (char *)&m360->dpram1[0];
     39  ptr->bdregions[0].base = (uint8_t *)&m360->dpram1[0];
    4040  ptr->bdregions[0].size = sizeof m360->dpram1;
    4141  ptr->bdregions[0].used = 0;
     42#if DEBUG_PRINT
     43printk("%d) base 0x%x size %d used %d\n", 0,
     44       (uint32_t)ptr->bdregions[0].base, ptr->bdregions[0].size, ptr->bdregions[0].used );
     45#endif
    4246
    43   ptr->bdregions[1].base = (char *)&m360->dpram3[0];
     47  ptr->bdregions[1].base = (uint8_t *)&m360->dpram3[0];
    4448  ptr->bdregions[1].size = sizeof m360->dpram3;
    4549  ptr->bdregions[1].used = 0;
     50#if DEBUG_PRINT
     51printk("%d) base 0x%x size %d used %d\n", 1,
     52       (uint32_t)ptr->bdregions[1].base, ptr->bdregions[1].size, ptr->bdregions[1].used );
     53#endif
    4654
    47   ptr->bdregions[2].base = (char *)&m360->dpram0[0];
     55  ptr->bdregions[2].base = (uint8_t *)&m360->dpram0[0];
    4856  ptr->bdregions[2].size = sizeof m360->dpram0;
    4957  ptr->bdregions[2].used = 0;
     58#if DEBUG_PRINT
     59printk("%d) base 0x%x size %d used %d\n", 2,
     60       (uint32_t)ptr->bdregions[2].base, ptr->bdregions[2].size, ptr->bdregions[2].used );
     61#endif
    5062
    51   ptr->bdregions[3].base = (char *)&m360->dpram2[0];
     63  ptr->bdregions[3].base = (uint8_t *)&m360->dpram2[0];
    5264  ptr->bdregions[3].size = sizeof m360->dpram2;
    5365  ptr->bdregions[3].used = 0;
     66#if DEBUG_PRINT
     67printk("%d) base 0x%x size %d used %d\n", 3,
     68       (uint32_t)ptr->bdregions[3].base, ptr->bdregions[3].size, ptr->bdregions[3].used );
     69#endif
     70
    5471}
    5572
     
    6178M360AllocateBufferDescriptors (M68360_t ptr, int count)
    6279{
    63   unsigned int i;
     80  uint32_t    i;
    6481  ISR_Level    level;
    6582  void         *bdp  = NULL;
    66   unsigned int want  = count * sizeof(m360BufferDescriptor_t);
    67   int          have;
     83  uint32_t      want  = count * sizeof(m360BufferDescriptor_t);
     84  uint32_t      have;
    6885
    6986  /*
     
    8299     */
    83100    if (ptr->bdregions[i].used == 0) {
    84       volatile unsigned char *cp = ptr->bdregions[i].base;
     101      volatile uint8_t *cp = ptr->bdregions[i].base;
     102      uint8_t data;
     103
    85104      *cp = 0xAA;
    86       if (*cp != 0xAA) {
     105      data = *cp;
     106      if (data != 0xAA) {
    87107        ptr->bdregions[i].used = ptr->bdregions[i].size;
     108#if DEBUG_PRINT
     109printk("%d) base 0x%x used %d expected 0xAA read 0x%x\n",i,
     110       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
     111#endif
    88112        continue;
    89113      }
    90114      *cp = 0x55;
    91       if (*cp != 0x55) {
     115      data = *cp;
     116      if (data != 0x55) {
    92117        ptr->bdregions[i].used = ptr->bdregions[i].size;
     118#if DEBUG_PRINT
     119printk("%d) base 0x%x used %d expected 0x55 read 0x%x\n",i,
     120       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
     121#endif
    93122        continue;
    94123      }
  • c/src/lib/libbsp/powerpc/ep1a/console/config.c

    raf46ad9 rfb557a9  
    22 *  This file contains the TTY driver table for the EP1A
    33 *
    4  *  COPYRIGHT (c) 1989-1999.
     4 *  COPYRIGHT (c) 1989-2009.
    55 *  On-Line Applications Research Corporation (OAR).
    66 *
     
    2222 */
    2323
     24#if 1
    2425#define NS16550_FUNCTIONS &ns16550_fns_polled
     26#else
     27#define NS16550_FUNCTIONS &ns16550_fns
     28#endif
     29
    2530#define MC68360_SCC_FUNCTIONS &mc68360_scc_fns
    2631
     
    123128                0                               /* ulIntVector */
    124129        },
     130
    125131        /*
    126132         * Up to 12 serial ports are provided by MC68360 SCC ports.
     
    432438}
    433439
     440
     441void Force_mc8360_interrupt( int d ) {
     442  mc68360_sccInterruptHandler( M68360_chips->next );
     443}
     444
  • c/src/lib/libbsp/powerpc/ep1a/console/console.c

    raf46ad9 rfb557a9  
    1 /*XXX
     1/*
    22 *  This file contains the TTY driver for the ep1a
    33 *
     
    213213      Console_Port_Minor);
    214214
     215  /*
     216   * NOTE:  We must probe ALL possible devices, which initializes
     217   *        the address information in the config.c tables.
     218   */
     219
    215220  for(minor++;minor<Console_Port_Count;minor++)
    216221  {
     
    242247  return RTEMS_SUCCESSFUL;
    243248}
    244 #if 0
    245 /* PAGE
    246  *
    247  *  DEBUG_puts
    248  *
    249  *  This should be safe in the event of an error.  It attempts to ensure
    250  *  that no TX empty interrupts occur while it is doing polled IO.  Then
    251  *  it restores the state of that external interrupt.
    252  *
    253  *  Input parameters:
    254  *    string  - pointer to debug output string
    255  *
    256  *  Output parameters:  NONE
    257  *
    258  *  Return values:      NONE
    259  */
    260 
    261 void DEBUG_puts(
    262         char *string
    263 )
    264 {
    265         char *s;
    266         unsigned32      Irql;
    267 
    268         rtems_interrupt_disable(Irql);
    269 
    270         for ( s = string ; *s ; s++ )
    271         {
    272                 Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
    273                         deviceWritePolled(Console_Port_Minor, *s);
    274         }
    275 
    276         rtems_interrupt_enable(Irql);
    277 }
    278 
    279 /* PAGE
    280  *
    281  *  DEBUG_puth
    282  *
    283  *  This should be safe in the event of an error.  It attempts to ensure
    284  *  that no TX empty interrupts occur while it is doing polled IO.  Then
    285  *  it restores the state of that external interrupt.
    286  *
    287  *  Input parameters:
    288  *    ulHexNum - value to display
    289  *
    290  *  Output parameters:  NONE
    291  *
    292  *  Return values:      NONE
    293  */
    294 void
    295 DEBUG_puth(
    296     unsigned32 ulHexNum
    297     )
    298 {
    299         unsigned long i,d;
    300         unsigned32 Irql;
    301 
    302         rtems_interrupt_disable(Irql);
    303        
    304         Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
    305                 deviceWritePolled(Console_Port_Minor, '0');
    306         Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
    307                 deviceWritePolled(Console_Port_Minor, 'x');
    308 
    309         for(i=32;i;)
    310         {
    311                 i-=4;
    312                 d=(ulHexNum>>i)&0xf;
    313                 Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
    314                         deviceWritePolled(Console_Port_Minor,
    315                                           (d<=9) ? d+'0' : d+'a'-0xa);
    316         }
    317 
    318         rtems_interrupt_enable(Irql);
    319 }
    320 #endif
    321249
    322250/* const char arg to be compatible with BSP_output_char decl. */
  • c/src/lib/libbsp/powerpc/ep1a/console/m68360.h

    raf46ad9 rfb557a9  
    1717 *                                           
    1818 *
    19  *  COPYRIGHT (c) 1989-1999.
     19 *  COPYRIGHT (c) 1989-2009.
    2020 *  On-Line Applications Research Corporation (OAR).
    2121 *
     
    936936
    937937struct bdregions_t {
    938   char            *base;
    939   unsigned int    size;
    940   unsigned int    used;
     938  uint8_t     *base;
     939  uint32_t    size;
     940  uint32_t    used;
    941941};
    942942
     
    978978int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );
    979979
     980void mc68360_sccInterruptHandler( void *ptr);
     981
    980982#if 0
    981983extern volatile m360_t *m360;
  • c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c

    raf46ad9 rfb557a9  
    22 *  Motorola MC68360 SCC ports.
    33 *
    4  *  COPYRIGHT (c) 1989-2008.
     4 *  COPYRIGHT (c) 1989-2009.
    55 *  On-Line Applications Research Corporation (OAR).
    66 *
     
    2626#include <string.h>
    2727
    28 #if 0
     28#if 0 
    2929#define DEBUG_360
    3030#endif
     
    7878)
    7979{
     80  *address = value;
    8081#ifdef DEBUG_360
    8182  printk( "WR8 %s 0x%08x 0x%02x\n", name, address, value );
    8283#endif
    83   *address = value;
    8484}
    8585
     
    109109)
    110110{
     111  *address = value;
    111112#ifdef DEBUG_360
    112113  printk( "WR16 %s 0x%08x 0x%04x\n", name, address, value );
    113114#endif
    114   *address = value;
    115115}
    116116
     
    140140)
    141141{
     142  *address = value;
     143  Processor_Synchronize();
    142144#ifdef DEBUG_360
    143145  printk( "WR32 %s 0x%08x 0x%08x\n", name, address, value );
    144146#endif
    145   *address = value;
    146147}
    147148
     
    156157
    157158#define TX_BUFFER_ADDRESS( _ptr ) \
    158   ((char *)ptr->txBuf - (char *)ptr->chip->board_data->baseaddr)
     159  ((uint8_t *)ptr->txBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
    159160#define RX_BUFFER_ADDRESS( _ptr ) \
    160   ((char *)ptr->rxBuf - (char *)ptr->chip->board_data->baseaddr)
     161  ((uint8_t *)ptr->rxBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
    161162
    162163
     
    240241 *                                                                        *
    241242 **************************************************************************/
    242 void mc68360_sccInterruptHandler( M68360_t chip )
    243 {
     243void mc68360_sccInterruptHandler( void *ptr)
     244{
     245  M68360_t           chip   = ptr;
    244246  volatile m360_t    *m360;
    245247  int                port;
     
    251253
    252254
    253 #ifdef DEBUG_360
    254   printk("mc68360_sccInterruptHandler\n");
     255#ifdef DEBUG_360 
     256  printk("mc68360_sccInterruptHandler with 0x%x \n", ptr);
    255257#endif
    256258  for (port=0; port<4; port++) {
     
    276278        {
    277279           length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);
    278 if (length > 1)
    279   EP1A_READ_LENGTH_GREATER_THAN_1 = length;
     280           if (length > 1)
     281             EP1A_READ_LENGTH_GREATER_THAN_1 = length;
    280282
    281283           for (i=0;i<length;i++) {
     
    303305        {
    304306           scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
    305 #if 1
    306307           rtems_termios_dequeue_characters(
    307308             Console_Port_Data[chip->port[port].minor].termios_data,
    308              chip->port[port].sccTxBd->length);
    309 #else
    310            mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);
    311 #endif
     309             chip->port[port].sccTxBd->length
     310           );
    312311        }
    313312      }
     
    316315       * Clear SCC interrupt-in-service bit.
    317316       */
    318       if ( clear_isr )
     317      if ( clear_isr ) {
    319318        scc_write32( "cisr", &m360->cisr, (0x80000000 >> chip->port[port].channel) );
     319      }
    320320  }
    321321}
     
    340340
    341341#ifdef DEBUG_360
    342   printk("mc68360_scc_open %d\n", minor);
    343 #endif
    344 
     342  printk("mc68360_scc_open %s (%d)\n", Console_Port_Tbl[minor].sDeviceName, minor);
     343#endif
    345344
    346345  ptr   = Console_Port_Tbl[minor].pDeviceParams;
     
    369368uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
    370369{
    371   uint32_t               i;
    372   uint32_t               pbdat_data;
     370  int                    i;
     371  uint32_t               pbdat_data = 0x03;
    373372  int                    minor;
    374373  uint32_t               type422data[4] = {
     
    379378  for (i=0; i<4; i++) {
    380379    minor = chip->port[i].minor;
    381     if mc68360_scc_Is_422( minor ) 
     380    if mc68360_scc_Is_422( minor ){
    382381      pbdat_data |= type422data[i];
     382    }
    383383  }
    384384
    385385  return pbdat_data;
    386386}
     387
    387388
    388389/*
     
    401402  uint32_t               tmp_u32;
    402403
    403 #ifdef DEBUG_360
     404#ifdef DEBUG_360 
    404405  printk("mc68360_scc_initialize_interrupts: minor %d\n", minor );
    405406  printk("Console_Port_Tbl[minor].pDeviceParams 0x%08x\n",
     
    410411  m360  = ptr->chip->m360;
    411412 
    412 #ifdef DEBUG_360
     413#ifdef DEBUG_360 
    413414  printk("m360 0x%08x baseaddr 0x%08x\n",
    414415     m360, ptr->chip->board_data->baseaddr);
     
    465466   * XXX
    466467   */
     468
    467469  scc_write16( "papar", &m360->papar, 0xffff );
    468470  scc_write16( "padir", &m360->padir, 0x5500 ); /* From Memo    */
     
    665667  M68360_serial_ports_t  ptr;
    666668
     669#ifdef DEBUG_360
     670  printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
     671       (unsigned int)*buf, len );
     672#endif
     673
    667674#if 1
    668675  mc68360_length_array[ mc68360_length_count ] = len;
     
    683690
    684691  /*
    685    *
    686    */
    687 #ifdef DEBUG_360
    688   printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
    689        (unsigned int)*buf, len );
    690 #endif
    691   /*
    692692   *  We must copy the data from the global memory space to MC68360 space
    693693   */
    694 
    695694  rtems_interrupt_disable(Irql);
     695#ifdef DEBUG_360
     696  printk("mc68360_scc_write_support_int: disable irq 0x%x\n", Irql );
     697#endif
    696698
    697699  scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 );
     
    703705               (M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) );
    704706
     707#ifdef DEBUG_360
     708  printk("mc68360_scc_write_support_int: enable irq 0x%x\n", Irql );
     709#endif
    705710  rtems_interrupt_enable(Irql);
    706711
     
    898903   *       section?
    899904   */
    900   if ((chip = malloc(sizeof(struct _m68360_per_chip))) == NULL)
     905
     906  if ((chip = calloc( 1, sizeof(struct _m68360_per_chip))) == NULL)
    901907  {
    902908    printk("Error Unable to allocate memory for _m68360_per_chip\n");
    903909    return RTEMS_IO_ERROR;
     910  } else {
     911    printk("Allocate memory for _m68360_per_chip at 0x%x\n", chip );
    904912  }
    905 
    906913  chip->next                    = M68360_chips;
    907914  chip->m360                    = (void *)BoardData->baseaddr;
     
    946953     * Allocate buffer descriptors.
    947954     */
    948 
    949955    chip->port[i-1].sccRxBd = M360AllocateBufferDescriptors(chip, 1);
    950956    chip->port[i-1].sccTxBd = M360AllocateBufferDescriptors(chip, 1);
     
    958964    chip
    959965  );
    960 
    961966  return RTEMS_SUCCESSFUL;
    962967}
  • c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c

    raf46ad9 rfb557a9  
    2828
    2929USAGE
    30 call rsPMCQ1Init() to perform ba  sic initialisation of the PMCQ1's.
     30call rsPMCQ1Init() to perform basic initialisation of the PMCQ1's.
    3131*/
    3232
     
    4242
    4343/* defines */
    44 #if 1
    45 #define DEBUG_360
     44#if 0
     45#define DEBUG_360     TRUE
    4646#endif
    4747
     
    8383void MsDelay(void)
    8484{
    85   printk(".");
     85  printk("..");
    8686}
    8787
    8888void write8( int addr, int data ){
    89   out_8((void *)addr, (unsigned char)data);
     89  out_8((volatile void *)addr, (unsigned char)data);
     90  Processor_Synchronize();
    9091}
    9192
    9293void write16( int addr, int data ) {
    93   out_be16((void *)addr, (short)data );
     94  out_be16((volatile void *)addr, (short)data );
     95  Processor_Synchronize();
    9496}
    9597
    9698void write32( int addr, int data ) {
    97   out_be32((unsigned int *)addr, data );
     99  out_be32((volatile unsigned int *)addr, data );
     100  Processor_Synchronize();
    98101}
    99102
    100103int read32( int addr){
    101   return in_be32((unsigned int *)addr);
    102 }
    103 
    104 
    105 void rsPMCQ1_scc_nullFunc(void) {}
     104  int value = in_be32((volatile unsigned int *)addr);
     105  Processor_Synchronize();
     106  return value;
     107}
     108
     109void rsPMCQ1_scc_On(const struct __rtems_irq_connect_data__ *ptr)
     110{
     111
     112}
     113
     114void rsPMCQ1_scc_Off(const struct __rtems_irq_connect_data__ *ptr)
     115{
     116
     117}
     118
     119int rsPMCQ1_scc_except_always_enabled(const struct __rtems_irq_connect_data__ *ptr)
     120{
     121  return TRUE;
     122}
     123
     124
     125void rsPMCQ1ShowIntrStatus(void )
     126{
     127  unsigned long   status;
     128  unsigned long   mask;
     129  PPMCQ1BoardData boardData;
     130
     131  for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
     132  {
     133
     134    status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
     135    mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
     136    printk("rsPMCQ1ShowIntrStatus: interrupt status 0x%x) 0x%x with mask: 0x%x\n", boardData->quiccInt, status, mask);
     137  }
     138}
     139
    106140 
    107141/*******************************************************************************
     
    117151{
    118152  unsigned long   status;
    119   unsigned long   status1;
     153  static unsigned long   status1;
    120154  unsigned long   mask;
    121155  uint32_t        data;
    122156  PPMCQ1BoardData boardData = ptr;
     157  volatile unsigned long *hrdwr;
     158  unsigned long           value;
    123159
    124160  status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
    125161  mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
    126162
    127   if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC))
     163
     164  if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && ((status & PMCQ1_INT_STATUS_QUICC) != 0 ))
    128165  {
    129166    /* If there is a handler call it otherwise mask the interrupt */
     
    131168      boardData->quiccInt(boardData->quiccArg);
    132169    } else {
    133       *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
     170      printk("No handler - Masking interrupt\n");
     171      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
     172      value = (*hrdwr) | PMCQ1_INT_MASK_QUICC;
     173      *hrdwr = value;
    134174    }
    135175  }
     
    137177  if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA))
    138178  {
     179
    139180    /* If there is a handler call it otherwise mask the interrupt */
    140181    if (boardData->maInt) {
    141182      boardData->maInt(boardData->maArg);
    142 
    143183      data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
    144       data &= (~PMCQ1_INT_STATUS_MA);
     184      data = data & (~PMCQ1_INT_STATUS_MA);
    145185      PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
    146 
    147     } else {
    148      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
     186    } else {
     187      printk("No handler - Masking interrupt\n");
     188      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
     189      value = (*hrdwr) | PMCQ1_INT_MASK_MA;
     190      *hrdwr = value;
    149191    }
    150192  }
     
    153195
    154196  /* Clear Interrupt on QSPAN */
    155   *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
     197  hrdwr = (volatile unsigned long *)(boardData->bridgeaddr + 0x600);
     198  *hrdwr = 0x00001000;
    156199
    157200  /* read back the status register to ensure that the pci write has completed */
    158   status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);
     201  status1 = *hrdwr;
     202
    159203  RTEMS_COMPILER_MEMORY_BARRIER();
    160 
    161204}
    162205
     
    176219    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    177220    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
    178     FUNCION_PTR routine,/* interrupt routine */
    179     int         arg     /* argument to pass to interrupt routine */
     221    PMCQ1_FUNCTION_PTR  routine,/* interrupt routine */
     222    void *              arg     /* argument to pass to interrupt routine */
    180223)
    181224{
     
    232275    {
    233276      boardData->maInt = NULL;
    234       *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
     277      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
    235278      status = RTEMS_SUCCESSFUL;
    236279      break;
     
    252295
    253296unsigned int rsPMCQ1QuiccIntConnect(
    254     unsigned long       busNo,  /* Pci Bus number of PMCQ1 */
    255     unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    256     unsigned long       funcNo, /* Pci Function number of PMCQ1 */
    257     FUNCION_PTR routine,/* interrupt routine */
    258     int         arg     /* argument to pass to interrupt routine */
     297  unsigned long         busNo,   /* Pci Bus number of PMCQ1 */
     298  unsigned long         slotNo,  /* Pci Slot number of PMCQ1 */
     299  unsigned long         funcNo,  /* Pci Function number of PMCQ1 */
     300  PMCQ1_FUNCTION_PTR    routine, /* interrupt routine */
     301  void *                arg      /* argument to pass to interrupt routine */
    259302)
    260303{
     
    301344    {
    302345      boardData->quiccInt = NULL;
    303       *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
     346      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
    304347      status = RTEMS_SUCCESSFUL;
    305348      break;
     
    324367  int busNo;
    325368  int slotNo;
    326   unsigned int baseaddr = 0;
    327   unsigned int bridgeaddr = 0;
     369  uint32_t baseaddr = 0;
     370  uint32_t bridgeaddr = 0;
    328371  unsigned long pbti0_ctl;
    329372  int i;
    330373  unsigned char int_vector;
    331374  int fun;
    332   int temp;
     375  uint32_t temp;
    333376  PPMCQ1BoardData       boardData;
    334   rtems_irq_connect_data IrqData = {0,
    335                                     rsPMCQ1Int,
    336                                     rsPMCQ1_scc_nullFunc,
    337                                     rsPMCQ1_scc_nullFunc,
    338                                     rsPMCQ1_scc_nullFunc,
    339                                     NULL};
     377  rtems_irq_connect_data *IrqData = NULL;
    340378
    341379  if (rsPMCQ1Initialized)
    342380  {
     381    printk("rsPMCQ1Init: Already Initialized\n");
    343382    return RTEMS_SUCCESSFUL;
    344   }
     383  }
     384
    345385  for (i=0;;i++){
    346386    if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 )
     
    350390    pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr);
    351391#ifdef DEBUG_360
    352   printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
     392  printk("rsPMCQ1Init: PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
    353393#endif
    354394
    355395    /* Set function code to normal mode and enable window */
    356     pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff;
     396    pbti0_ctl = (*(unsigned long *)(bridgeaddr + 0x100)) & 0xff0fffff;
    357397    eieio();
    358     *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
     398    *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
    359399    eieio();
    360400
    361401    /* Assert QBUS reset */
    362     *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
     402    *(volatile unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
    363403    eieio();
    364404
     
    369409
    370410    /* Take QBUS out of reset */
    371     *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
     411    *(volatile unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
    372412    eieio();
    373413
     
    378418    {
    379419#ifdef DEBUG_360
    380   printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
     420  printk("rsPMCQ1Init: Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
    381421#endif
    382422
    383423      /* Initialise MBAR (must use function code of 7) */
    384       *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
     424      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
    385425      eieio();
    386426
    387427      /* place internal 8K SRAM and registers at address 0x0 */
    388       *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
     428      *(volatile unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
    389429      eieio();
    390430
    391431      /* Set function code to normal mode */
    392       *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
     432      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
    393433      eieio();
    394434
     
    426466    pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp);
    427467    if (temp) {
    428       *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
     468      *(volatile unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
    429469    }
    430470
     
    432472     * Create descriptor structure for this card
    433473     */
    434     if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL)
    435     {
    436       printk("Error Unable to allocate memory for _PMCQ1BoardData\n");
     474    if ((boardData = calloc(1, sizeof(struct _PMCQ1BoardData))) == NULL)
     475    {
     476      printk("rsPMCQ1Init: Error Unable to allocate memory for _PMCQ1BoardData\n");
    437477      return(RTEMS_IO_ERROR);
    438478    }
     
    447487    boardData->maInt = NULL;
    448488    pmcq1BoardData = boardData;
     489
    449490    mc68360_scc_create_chip( boardData, int_vector );
    450491
     
    454495    pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector);
    455496#ifdef DEBUG_360
    456     printk("PMCQ1 int_vector %d\n", int_vector);
     497    printk("rsPMCQ1Init: PMCQ1 int_vector %d\n", int_vector);
    457498#endif
    458     IrqData.name  = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
    459     IrqData.handle = boardData;
    460     if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {
     499
     500    if ((IrqData = calloc( 1, sizeof(rtems_irq_connect_data) )) == NULL )
     501    {
     502      printk("rsPMCQ1Init: Error Unable to allocate memory for rtems_irq_connect_data\n");
     503      return(RTEMS_IO_ERROR);
     504    }
     505    IrqData->name   = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
     506    IrqData->hdl    = rsPMCQ1Int;
     507    IrqData->handle = boardData;
     508    IrqData->on     = rsPMCQ1_scc_On;
     509    IrqData->off    = rsPMCQ1_scc_Off;
     510    IrqData->isOn   = rsPMCQ1_scc_except_always_enabled;
     511
     512    if (!BSP_install_rtems_shared_irq_handler (IrqData)) {
    461513        printk("Error installing interrupt handler!\n");
    462514        rtems_fatal_error_occurred(1);
     
    466518     * Enable PMCQ1 Interrupts from QSPAN-II
    467519     */
    468        
    469     *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
     520    *(volatile unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
    470521    eieio();
    471     *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
    472 
     522    Processor_Synchronize();
     523    *(volatile unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
    473524    eieio();
    474525  }
     
    513564     */
    514565    if ((busNo == 0) && (slotNo == 1)) {
    515       *(unsigned long *)rsPMCQ1eeprom = 0;
     566      *(volatile unsigned long *)rsPMCQ1eeprom = 0;
    516567    } else {
    517       *(unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
     568      *(volatile unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
    518569    }
    519570
     
    559610uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg )
    560611{
    561   uint32_t data;
    562 
    563   data = ( *((unsigned long *) (base + reg)) );
     612  uint32_t           data;
     613  volatile uint32_t *ptr;
     614
     615  Processor_Synchronize();
     616  ptr =  (volatile uint32_t *)(base + reg);
     617  data =  *ptr ;
    564618#ifdef DEBUG_360
    565   printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data );
     619  printk("EPLD Read 0x%x: 0x%08x\n", ptr, data );
    566620#endif
    567621  return data;
     
    570624void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data )
    571625{
    572   *((unsigned long *) (base + reg)) = data;
     626  volatile uint32_t *ptr;
     627
     628  ptr = (volatile uint32_t *) (base + reg);
     629  *ptr = data;
     630  Processor_Synchronize();
    573631#ifdef DEBUG_360
    574   printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data );
     632  printk("EPLD Write 0x%x: 0x%08x\n", ptr, data );
    575633#endif
    576634}
  • c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h

    raf46ad9 rfb557a9  
    3131 */
    3232
    33 #ifndef __INCPMCQ1H
    34 #define __INCPMCQ1H
     33#ifndef __RSPMCQ1_H
     34#define __RSPMCQ1_H
    3535
    3636/*
     
    9696#define PMCQ1_RAM               0x00200000
    9797
    98 /*
    99 #define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )
    100 #define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data
    101 */
    10298uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );
    10399void     PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );
     
    109105#define QSPAN2_INT_STATUS       0x00000600
    110106
    111 typedef void (*FUNCION_PTR) (int);
     107typedef void (*PMCQ1_FUNCTION_PTR) (void *);
    112108
    113109#define PCI_ID(v, d) ((d << 16) | v)
     
    126122typedef struct _PMCQ1BoardData
    127123{
    128     struct _PMCQ1BoardData              *pNext;     
    129     unsigned long                       busNo;
    130     unsigned long                       slotNo;
    131     unsigned long                       funcNo;
    132     unsigned long                       baseaddr;
    133     unsigned long                       bridgeaddr;
    134     FUNCION_PTR                         quiccInt;
    135     int                                 quiccArg;
    136     FUNCION_PTR                         maInt;
    137     int                                 maArg;
     124    struct _PMCQ1BoardData              *pNext;     
     125    unsigned long                       busNo;
     126    unsigned long                       slotNo;
     127    unsigned long                       funcNo;
     128    unsigned long                       baseaddr;
     129    unsigned long                       bridgeaddr;
     130    PMCQ1_FUNCTION_PTR                  quiccInt;
     131    void *                              quiccArg;
     132    PMCQ1_FUNCTION_PTR                  maInt;
     133    void *                              maArg;
    138134} PMCQ1BoardData, *PPMCQ1BoardData;
    139135
     
    147143  unsigned long         slotNo,
    148144  unsigned long         funcNo,
    149   FUNCION_PTR           routine,
    150   int                   arg
     145  PMCQ1_FUNCTION_PTR    routine,
     146  void *                arg
    151147);
    152148unsigned int rsPMCQ1Init();
     
    155151    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    156152    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
    157     FUNCION_PTR         routine,/* interrupt routine */
    158     int                 arg     /* argument to pass to interrupt routine */
     153    PMCQ1_FUNCTION_PTR  routine,/* interrupt routine */
     154    void *              arg     /* argument to pass to interrupt routine */
    159155);
    160156
    161 #endif                          /* __INCPMCQ1H */
     157void rsPMCQ1ShowIntrStatus(void );
     158
     159#endif                          /* __RSPMCQ1_H */
  • c/src/lib/libbsp/powerpc/ep1a/include/bsp.h

    raf46ad9 rfb557a9  
    11/*
    22 *
    3  *  COPYRIGHT (c) 1989-1999.
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
     
    1313#ifndef _BSP_H
    1414#define _BSP_H
     15
     16
     17#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
    1518
    1619#include <bspopts.h>
  • c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c

    raf46ad9 rfb557a9  
    66 *  CopyRight (C) 1999 valette@crf.canon.fr
    77 *
    8  * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
    9  * to make it valid for MVME2300 Motorola boards.
    10  *
    11  * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
    12  * Use the new interface to openpic_init
    13  *
    14  *  COPYRIGHT (c) 1989-1999.
     8 *  Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
     9 *  to make it valid for MVME2300 Motorola boards.
     10 *
     11 *  Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
     12 *  Use the new interface to openpic_init
     13 *
     14 *  COPYRIGHT (c) 1989-2009.
    1515 *  On-Line Applications Research Corporation (OAR).
    1616 *
     
    3333#include <rtems/bspIo.h>
    3434
    35 /*
    36 #define SHOW_ISA_PCI_BRIDGE_SETTINGS
    37 */
    38 #define TRACE_IRQ_INIT
    39 
    40 /*
    41  * default on/off function
    42  */
    43 static void nop_func(void){}
    44 /*
    45  * default isOn function
    46  */
    47 static int not_connected(void) {return 0;}
    48 /*
    49  * default possible isOn function
    50  */
    51 static int connected(void) {return 1;}
    52 
     35#if 0
     36#define TRACE_IRQ_INIT 1   /* XXX */
     37#endif
     38
     39typedef struct {
     40  unsigned char bus;    /* few chance the PCI/ISA bridge is not on first bus but ... */
     41  unsigned char device;
     42  unsigned char function;
     43} pci_isa_bridge_device;
     44
     45pci_isa_bridge_device* via_82c586 = 0;
     46#if 0
     47static pci_isa_bridge_device bridge;
     48#endif
     49
     50
     51
     52extern unsigned int external_exception_vector_prolog_code_size[];
     53extern void external_exception_vector_prolog_code();
     54extern unsigned int decrementer_exception_vector_prolog_code_size[];
     55extern void decrementer_exception_vector_prolog_code();
     56
     57
     58static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); }
     59static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr)   {}
     60static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr)   {}
     61static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
    5362static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
    5463static rtems_irq_global_settings        initial_config;
    5564static rtems_irq_connect_data           defaultIrq = {
    56   /* vectorIdex,         hdl            , handle        , on            , off           , isOn */
    57   0,                     nop_func       , NULL          , nop_func      , nop_func      , not_connected
    58 };
     65/*name,  hdl                            handle  on                              off                             isOn */
     66  0,     IRQ_Default_rtems_irq_hdl,     NULL,   IRQ_Default_rtems_irq_enable,   IRQ_Default_rtems_irq_disable,  IRQ_Default_rtems_irq_is_enabled
     67};
     68
     69
     70/*
     71 *  If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected.
     72 */
     73#if ( (BSP_ISA_IRQ_NUMBER == 16)      && \
     74      (BSP_PCI_IRQ_NUMBER == 26)      && \
     75      (BSP_PROCESSOR_IRQ_NUMBER == 1) && \
     76      (BSP_MISC_IRQ_NUMBER == 8) )
     77
     78
    5979static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
    6080  /*
    61    * actual rpiorities for interrupt :
    62    *    0   means that only current interrupt is masked
    63    *    255 means all other interrupts are masked
    64    */
    65   /*
    6681   * ISA interrupts.
    67    * The second entry has a priority of 255 because
    68    * it is the slave pic entry and is should always remain
    69    * unmasked.
    70    */
    71   0,0,
    72   255,
     82   */
     83  0, 0,
     84  (OPENPIC_NUM_PRI-1),
    7385  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
     86
    7487  /*
    7588   * PCI Interrupts
    7689   */
    77   8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
     90  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
     91  8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
     92
    7893  /*
    7994   * Processor exceptions handled as interrupts
    8095   */
    81   0
    82 };
    83 
    84 static unsigned char mcp750_openpic_initpolarities[] = {
     96  8,
     97 
     98  8, 8, 8, 8, 8, 8, 8, 8
     99};
     100
     101static unsigned char mpc8245_openpic_initpolarities[] = {
    85102    1,  /*  0 8259 cascade */
    86     0,  /*  1 all the rest of them */
    87     0,  /*  2 all the rest of them */
    88     0,  /*  3 all the rest of them */
    89     0,  /*  4 all the rest of them */
    90     0,  /*  5 all the rest of them */
    91     0,  /*  6 all the rest of them */
    92     0,  /*  7 all the rest of them */
    93     0,  /*  8 all the rest of them */
    94     0,  /*  9 all the rest of them */
    95     0,  /* 10 all the rest of them */
    96     0,  /* 11 all the rest of them */
    97     0,  /* 12 all the rest of them */
    98     0,  /* 13 all the rest of them */
    99     0,  /* 14 all the rest of them */
    100     0,  /* 15 all the rest of them */
    101     0,  /* 16 all the rest of them */
    102     0,  /* 17 all the rest of them */
     103    0,  /*  1 */
     104    0,  /*  2 */
     105    0,  /*  3 */
     106    0,  /*  4 */
     107    0,  /*  5 */
     108    0,  /*  6 */
     109    0,  /*  7 */
     110    0,  /*  8 */
     111    0,  /*  9 */
     112    0,  /* 10 */
     113    0,  /* 11 */
     114    0,  /* 12 */
     115    0,  /* 13 */
     116    0,  /* 14 */
     117    0,  /* 15 */
     118    0,  /* 16 */
     119    0,  /* 17 */
    103120    1,  /* 18 all the rest of them */
    104121    1,  /* 19 all the rest of them */
     
    109126    1,  /* 24 all the rest of them */
    110127    1,  /* 25 all the rest of them */
    111 };
    112 
    113 static unsigned char mcp750_openpic_initsenses[] = {
    114     1,  /* 0 MCP750_INT_PCB(8259) */
    115     0,  /* 1 MCP750_INT_FALCON_ECC_ERR */
    116     1,  /* 2 MCP750_INT_PCI_ETHERNET */
    117     1,  /* 3 MCP750_INT_PCI_PMC */
    118     1,  /* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */
    119     1,  /* 5 MCP750_INT_PCI_PRST_SIGNAL */
    120     1,  /* 6 MCP750_INT_PCI_FALL_SIGNAL */
    121     1,  /* 7 MCP750_INT_PCI_DEG_SIGNAL */
    122     1,  /* 8 MCP750_INT_PCI_BUS1_INTA */
    123     1,  /* 9 MCP750_INT_PCI_BUS1_INTB */
    124     1,  /*10 MCP750_INT_PCI_BUS1_INTC */
    125     1,  /*11 MCP750_INT_PCI_BUS1_INTD */
    126     1,  /*12 MCP750_INT_PCI_BUS2_INTA */
    127     1,  /*13 MCP750_INT_PCI_BUS2_INTB */
    128     1,  /*14 MCP750_INT_PCI_BUS2_INTC */
    129     1,  /*15 MCP750_INT_PCI_BUS2_INTD */
     128    1,  /* 26 all the rest of them */
     129    1,  /* 27 all the rest of them */
     130    1,  /* 28 all the rest of them */
     131    1,  /* 29 all the rest of them */
     132    1,  /* 30 all the rest of them */
     133    1,  /* 31 all the rest of them */
     134    1,  /* 32 all the rest of them */
     135    1,  /* 33 all the rest of them */
     136    1,  /* 34 all the rest of them */
     137    1,  /* 35 all the rest of them */
     138    1,  /* 36 all the rest of them */
     139    1,  /* 37 all the rest of them */
     140    1,  /* 38 all the rest of them */
     141    1,  /* 39 all the rest of them */
     142    1,  /* 40 all the rest of them */
     143    1,  /* 41 all the rest of them */
     144    1,  /* 42 all the rest of them */
     145    1,  /* 43 all the rest of them */
     146    1,  /* 44 all the rest of them */
     147    1,  /* 45 all the rest of them */
     148    1,  /* 46 all the rest of them */
     149    1,  /* 47 all the rest of them */
     150    1,  /* 48 all the rest of them */
     151    1,  /* 49 all the rest of them */
     152    1,  /* 50 all the rest of them */
     153    1,  /* 51 all the rest of them */
     154
     155};
     156
     157static unsigned char mpc8245_openpic_initsenses[] = {
     158    1,  /* 0  */
     159    0,  /* 1  */
     160    1,  /* 2  */
     161    1,  /* 3  */
     162    1,  /* 4  */
     163    1,  /* 5  */
     164    1,  /* 6  */
     165    1,  /* 7  */
     166    1,  /* 8  */
     167    1,  /* 9  */
     168    1,  /*10  */
     169    1,  /*11  */
     170    1,  /*12  */
     171    1,  /*13  */
     172    1,  /*14  */
     173    1,  /*15  */
    130174    1,
    131175    1,
     
    137181    1,
    138182    1,
     183    1,
     184    1,
     185    1,
     186    1,
     187    1,
     188    1,
     189    1,
     190    1,
     191    1,
     192    1,
     193    1,
     194    1,
     195    1,
     196    1,
     197    1,
     198    1,
     199    1,
     200    1,
     201    1,
     202    1,
     203    1,
     204    1,
     205    1,
     206    1,
     207    1,
     208    1,
    139209    1
    140210};
     211#endif
    141212
    142213  /*
     
    148219void BSP_rtems_irq_mng_init(unsigned cpuId)
    149220{
    150   int i;
     221  int                           i;
    151222
    152223  /*
     
    154225   */
    155226#ifdef TRACE_IRQ_INIT 
    156   printk("Going to initialize openpic compliant device\n");
    157 #endif       
     227  uint32_t                      msr;
     228
     229  _CPU_MSR_GET( msr );
     230  printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr);
     231  printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER );
     232  printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET );
     233  printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET);
     234  printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER );
     235  printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET );
     236  printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET );
     237  printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER );
     238  printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET );
     239  printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET);
     240  printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER);
     241  printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET);
     242  printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET );
     243  printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER );
     244  printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET );
     245  printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET );
     246#endif
     247       
    158248  /* FIXME (t.s.): we should probably setup the EOI delay by
    159249   * passing a non-zero 'epic_freq' argument (frequency of the
    160250   * EPIC serial interface) but I don't know the value on this
    161251   * board (8245 SDRAM freq, IIRC)...
    162    */
    163   openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */);
    164 
    165 #ifdef TRACE_IRQ_INIT 
    166   printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
    167 #endif
     252   *
     253   * When tested this appears to work correctly.
     254   */
     255  openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0);
    168256
    169257  /*
     
    176264      rtemsIrq[i]      = defaultIrq;
    177265      rtemsIrq[i].name = i;
     266#ifdef BSP_SHARED_HANDLER_SUPPORT
     267      rtemsIrq[i].next_handler = NULL;
     268#endif
    178269    }
     270
    179271    /*
    180272     * Init initial Interrupt management config
     
    186278    initial_config.irqPrioTbl   = irqPrioTable;
    187279
    188 printk("Call BSP_rtems_irq_mngt_set\n");
     280
     281#ifdef TRACE_IRQ_INIT 
     282    _CPU_MSR_GET( msr );
     283    printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr);
     284#endif
    189285    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
    190286      /*
     
    192288       */
    193289      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
     290    }  else {
     291      printk(" Initialized RTEMS Interrupt Manager\n");
    194292    }
    195  
     293
    196294#ifdef TRACE_IRQ_INIT 
    197295    printk("RTEMS IRQ management is now operationnal\n");
  • c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c

    raf46ad9 rfb557a9  
    2424#include <stdlib.h>
    2525
    26 #include <rtems/bspIo.h> /* for printk */
     26#include <rtems/bspIo.h>
    2727#define RAVEN_INTR_ACK_REG 0xfeff0030
    2828
     
    4242 * default handler connected on each irq after bsp initialization
    4343 */
    44 static rtems_irq_connect_data   default_rtems_entry;
    45 
    46 static rtems_irq_connect_data*          rtems_hdl_tbl;
    47 
    48 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
     44static rtems_irq_connect_data      default_rtems_entry;
     45static rtems_irq_connect_data*     rtems_hdl_tbl;
     46
    4947/*
    5048 * Check if IRQ is an ISA IRQ
     
    5250static inline int is_isa_irq(const rtems_irq_number irqLine)
    5351{
    54   return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
     52  if  ( BSP_ISA_IRQ_NUMBER == 0 )
     53    return FALSE;
     54
     55  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &&
    5556          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
    5657         );
    5758}
    58 #endif
    5959
    6060/*
     
    6363static inline int is_pci_irq(const rtems_irq_number irqLine)
    6464{
    65   return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
     65  if ( BSP_PCI_IRQ_NUMBER == 0 )
     66    return FALSE;
     67
     68  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &&
    6669          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
    6770         );
     
    99102#endif
    100103
    101 void
    102 BSP_enable_irq_at_pic(const rtems_irq_number name)
    103 {
    104 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
     104void BSP_enable_irq_at_pic(const rtems_irq_number name)
     105{
     106  if (is_isa_irq(name)) {
     107    printk("BSP_enable_irq_at_pic: called with isa irq\n");
     108  }
     109  if (is_pci_irq(name)) {
     110    /*
     111     * enable interrupt at OPENPIC level.
     112     */
     113    openpic_enable_irq ( ((int)name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 ); 
     114  }
     115}
     116
     117int BSP_disable_irq_at_pic(const rtems_irq_number name)
     118{
    105119    if (is_isa_irq(name)) {
    106120      /*
    107        * Enable interrupt at PIC level
    108        */
    109 printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
    110       BSP_irq_enable_at_i8259s ((int) name);
    111     }
    112 #endif
    113    
     121       * disable interrupt at PIC level
     122       */
     123      printk("BSP_disable_irq_at_pic: called with isa irq\n");
     124    }
    114125    if (is_pci_irq(name)) {
    115126      /*
    116        * Enable interrupt at OPENPIC level
    117        */
    118 printk(" openpic_enable_irq %d\n", (int)name );
    119        openpic_enable_irq ((int) name);
    120     }
    121 }
    122 
    123 int
    124 BSP_disable_irq_at_pic(const rtems_irq_number name)
    125 {
    126 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
    127     if (is_isa_irq(name)) {
    128       /*
    129        * disable interrupt at PIC level
    130        */
    131       return BSP_irq_disable_at_i8259s ((int) name);
    132     }
    133 #endif
    134     if (is_pci_irq(name)) {
    135       /*
    136127       * disable interrupt at OPENPIC level
    137128       */
    138       return openpic_disable_irq ((int) name );
    139     }
    140         return -1;
     129      return openpic_disable_irq (((int) name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 );
     130    }
     131    return -1;
    141132}
    142133
     
    147138{
    148139    int i;
     140
    149141   /*
    150142    * Store various code accelerators
    151143    */
    152144    default_rtems_entry = config->defaultEntry;
    153     rtems_hdl_tbl               = config->irqHdlTbl;
    154 
     145    rtems_hdl_tbl       = config->irqHdlTbl;
     146   
    155147    /*
    156148     * set up internal tables used by rtems interrupt prologue
    157149     */
    158 #if 0
    159150#ifdef BSP_PCI_ISA_BRIDGE_IRQ
    160151    /*
     
    163154    compute_i8259_masks_from_prio (config);
    164155
    165     for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
     156    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; (i < (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER)); i++) {
    166157      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    167158         BSP_irq_enable_at_i8259s (i);
     
    179170        }
    180171#endif
    181 #endif
    182172
    183173    /*
     
    191181                                  config->irqPrioTbl[i]);
    192182      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    193          openpic_enable_irq ((int) i );
     183         openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
    194184      }
    195185      else {
    196          openpic_disable_irq ((int) i );
     186         openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
    197187      }
    198188    }
     
    200190#ifdef BSP_PCI_ISA_BRIDGE_IRQ
    201191        if ( BSP_ISA_IRQ_NUMBER > 0 ) {
    202         /*
    203              * Must enable PCI/ISA bridge IRQ
    204              */
    205         openpic_enable_irq (0);
     192          /*
     193           * Must enable PCI/ISA bridge IRQ
     194           */
     195          openpic_enable_irq (0);
    206196        }
    207197#endif
    208 
     198   
    209199    return 1;
    210200}
    211201
    212202int _BSP_vme_bridge_irq = -1;
    213 
    214203unsigned BSP_spuriousIntr = 0;
    215204
     
    225214  register unsigned newMask;                  /* new isa pic masks */
    226215#endif
    227 
    228216  if (excNum == ASM_DEC_VECTOR) {
    229 /* printk("ASM_DEC_VECTOR\n"); */
    230         bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
    231 
     217    bsp_irq_dispatch_list_base(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
    232218    return 0;
    233219
     
    235221  irq = openpic_irq(0);
    236222  if (irq == OPENPIC_VEC_SPURIOUS) {
    237 /* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */
    238      ++BSP_spuriousIntr;
     223    printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS );
     224    ++BSP_spuriousIntr;
    239225    return 0;
    240226  }
    241227
    242228  /* some BSPs might want to use a different numbering... */
    243   irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
    244 /* printk("OpenPic Irq: %d\n", irq); */
     229  irq = irq - OPENPIC_VEC_SOURCE ;
    245230
    246231#ifdef BSP_PCI_ISA_BRIDGE_IRQ
    247232  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
    248233  if (isaIntr)  {
    249 /* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */
    250234    /*
    251235     * Acknowledge and read 8259 vector
     
    265249#endif
    266250
    267 
    268251  /* dispatch handlers */
    269 /* printk("dispatch\n"); */
    270 irq -=16;
    271   bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
    272 /* printk("Back from dispatch\n"); */
    273 
    274 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
    275   if (isaIntr)  {\
     252  bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
     253
     254#ifdef BSP_PCI_ISA_BRIDGE_IRQ
     255  if (isaIntr)  {
    276256    i8259s_cache = oldMask;
    277257    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
     
    280260  else
    281261#endif
     262
    282263  {
    283264#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
    284         /* leave it to the VME bridge driver to do EOI, so
     265    /* leave it to the VME bridge driver to do EOI, so
    285266     * it can re-enable the openpic while handling
    286267     * VME interrupts (-> VME priorities in software)
    287         */
    288         if (_BSP_vme_bridge_irq != irq)
    289 #endif
    290                 openpic_eoi(0);
     268    */
     269    if (_BSP_vme_bridge_irq != irq)
     270#endif
     271      openpic_eoi(0);
    291272  }
    292273  return 0;
    293 }
     274
     275}
  • c/src/lib/libbsp/powerpc/ep1a/preinstall.am

    raf46ad9 rfb557a9  
    5858PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
    5959
    60 $(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    61         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h
    62 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h
     60$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
    6363
    6464$(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h
    8383
    84 $(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    85         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
    86 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
    87 
    88 $(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
    91 
    92 $(PROJECT_INCLUDE)/bsp/irq.h: ../../powerpc/shared/irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     84$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    9385        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
    9486PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     
    10597        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    10698PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
     99
     100$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     101        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
     102PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
    107103
    108104$(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
  • c/src/lib/libbsp/powerpc/ep1a/start/start.S

    raf46ad9 rfb557a9  
    115115        ori     sp,sp,__stack@l
    116116
     117        lis     r13,_SDA_BASE_@ha
     118        la      r13,_SDA_BASE_@l(r13)           /* Read-write small data */
     119
     120
    117121        /* set up initial stack frame */
    118122        addi    sp,sp,-4                /* make sure we don't overwrite debug mem */
  • c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c

    raf46ad9 rfb557a9  
    55 *  before this routine is invoked.
    66 *
    7  *  COPYRIGHT (c) 1989-2007.
     7 *  COPYRIGHT (c) 1989-2009.
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
     
    1515 */
    1616
    17 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
     17#define SHOW_MORE_INIT_SETTINGS
    1818
    1919#include <string.h>
     
    3434#include <bsp/vectors.h>
    3535#include <rtems/powerpc/powerpc.h>
     36#include <bsp/ppc_exc_bspsupp.h>
    3637
    3738extern unsigned long __rtems_end[];
     
    9596
    9697/*
     98 * Where the heap starts; is used by bsp_pretasking_hook;
     99 */
     100unsigned int BSP_heap_start;
     101uint32_t BSP_intrStackStart;
     102uint32_t BSP_intrStackSize;
     103
     104/*
    97105 * PCI Bus Frequency
    98106 */
     
    106114/*
    107115 * Time base divisior (how many tick for 1 second).
    108  */
    109 unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
     116 * Calibrated by outputing a 20 ms pulse.
     117 */
     118unsigned int BSP_time_base_divisor = 1320; 
    110119
    111120/*
    112121 * system init stack
    113122 */
    114 #define INIT_STACK_SIZE 0x1000
     123#define INIT_STACK_SIZE 0x2000
     124#define INTR_STACK_SIZE rtems_configuration_get_interrupt_stack_size()
    115125
    116126void BSP_panic(char *s)
     
    171181void bsp_libc_init( void *, uint32_t, int );
    172182
     183
     184void ShowMemoryLayout(){
     185  extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];
     186  extern unsigned long __SBSS2_START__[], __SBSS2_END__[];
     187  extern unsigned long __bss_start[];
     188  extern unsigned long __bss_end[];
     189  extern unsigned long __stack[];
     190  extern unsigned long __stackLow[];
     191  extern uint32_t end;
     192  /* extern uint32_t BSP_intrStackStart; */
     193  /* extern uint32_t BSP_intrStackSize; */
     194  /* Configuration.work_space_start     */
     195  /* rtems_configuration_get_work_space_size() */
     196  printk(" bss start: 0x%x\n", __bss_start);
     197  printk(" bss end: 0x%x\n",  __bss_end);
     198  printk(" rtems end: 0x%x\n",  __rtems_end);
     199  printk(" stack    : 0x%x\n",  __stack);
     200  printk(" stack Low: 0x%x\n",  __stackLow);
     201  printk(" end      : 0x%x\n",  &end);
     202  printk(" Intr Stack: 0x%x\n", BSP_intrStackStart);
     203  printk(" Intr Stack Size: 0x%x\n", BSP_intrStackSize);
     204  printk(" Heap start: %x\n", BSP_heap_start);
     205
     206  printk(" workspace start: 0x%x\n", Configuration.work_space_start);
     207  printk(" workspace size: 0x%x\n", rtems_configuration_get_work_space_size() );
     208
     209}
     210
     211
     212
     213
     214
    173215/*
    174216 *  Function:   bsp_pretasking_hook
     
    187229void bsp_pretasking_hook(void)
    188230{
    189   uint32_t        heap_start;   
     231  uint32_t        heap_start = BSP_heap_start;   
    190232  uint32_t        heap_size;
    191233  uint32_t        heap_sbrk_spared;
    192 
    193234  extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
    194  
    195   heap_start = ((uint32_t) __rtems_end) +
    196     INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size();
    197   if (heap_start & (CPU_ALIGNMENT-1))
    198     heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
    199 
    200   heap_size = (BSP_mem_size - heap_start) - rtems_configuration_get_work_space_size();
    201 
    202   heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
    203 
    204 #ifdef SHOW_MORE_INIT_SETTINGS
    205   printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n",
    206     heap_start, heap_size, heap_sbrk_spared);
     235  extern uint32_t end;
     236
     237  heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1);
     238  heap_size = (uint32_t) &RAM_END;
     239  heap_size = heap_size - heap_start - Configuration.work_space_size;
     240  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
     241
     242#if 0  /*XXXXXXX */
     243    heap_size = Configuration.work_space_start - (void *)&end;
     244    heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
     245#endif
     246
     247#ifdef SHOW_MORE_INIT_SETTINGS
     248  printk(" HEAP start 0x%x  size %x \n",
     249    heap_start, heap_size, 0 );
    207250#endif   
    208251
    209   bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
     252  bsp_libc_init((void *)heap_start, heap_size, 0);
    210253  rsPMCQ1Init();
     254  ShowMemoryLayout();
    211255}
    212256
     
    233277
    234278unsigned int get_eumbbar() {
    235   register int a, e;
    236 
    237   asm volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
    238   asm volatile("sync");
    239                                                                
    240   asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
    241   asm volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a)); 
    242   asm volatile("sync");
    243 
    244   asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
    245   asm volatile("sync");
    246                                                          
    247   asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
    248   asm volatile("isync");
    249   return e;
     279  out_le32( (uint32_t*)0xfec00000, 0x80000078 );
     280  return in_le32( (uint32_t*)0xfee00000 );
    250281}
    251282
     
    318349      break;
    319350  }
     351  printk("Processor Frequency %d  Bus Frequency: %d\n", BSP_processor_frequency, BSP_bus_frequency );
    320352}
    321353
     
    329361{
    330362  unsigned char *stack;
    331   uint32_t intrStackStart;
    332   uint32_t intrStackSize;
    333363  unsigned char *work_space_start;
    334364  ppc_cpu_id_t myCpu;
     
    347377  printk("EUMBBAR 0x%08x\n", EUMBBAR );
    348378
     379  /*
     380   * Init MMU block address translation to enable hardware
     381   * access
     382   */
     383  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
     384  setdbat(2, 0x80000000, 0x80000000, 0x10000000, IO_PAGE);
     385  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
     386ShowBATS();
     387
    349388  /*
    350389   * Note this sets BSP_processor_frequency based upon register settings.
     
    352391   */
    353392  Read_ep1a_config_registers( myCpu );
    354 
    355393  bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);
    356394
    357 ShowBATS();
    358395#if 0   /* XXX - Add back in cache enable when we get this up and running!! */
    359396  /*
     
    365402
    366403  /*
    367    * the initial stack  has aready been set to this value in start.S
    368    * so there is no need to set it in r1 again... It is just for info
    369    * so that It can be printed without accessing R1.
    370    */
    371   stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE;
    372 
    373  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
    374   *((uint32_t *)stack) = 0;
    375 
    376   /*
    377404   * Initialize the interrupt related settings.
    378405   */
    379   intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
    380   intrStackSize = rtems_configuration_get_interrupt_stack_size();
     406  BSP_intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
     407  BSP_intrStackSize = rtems_configuration_get_interrupt_stack_size();
     408  BSP_heap_start = BSP_intrStackStart + BSP_intrStackSize;
     409  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
     410    BSP_intrStackStart, BSP_intrStackSize, BSP_heap_start
     411  );
     412
     413  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
     414  *((uint32_t *)BSP_intrStackStart) = 0;
    381415
    382416  /*
    383417   * Initialize default raw exception hanlders.
    384418   */
     419
     420#ifdef SHOW_MORE_INIT_SETTINGS
     421  printk("bsp_start: Initialize Exceptions\n");
     422#endif 
     423  ppc_exc_cache_wb_check = 0;
    385424  ppc_exc_initialize(
    386425    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    387     intrStackStart,
    388     intrStackSize
     426    BSP_intrStackStart,
     427    BSP_intrStackSize
    389428  );
    390429
    391   /*
    392    * Init MMU block address translation to enable hardware
    393    * access
    394    */
    395   setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
    396   setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
    397 
    398 
    399 #ifdef SHOW_MORE_INIT_SETTINGS
    400   printk("Going to start PCI buses scanning and initialization\n");
     430#ifdef SHOW_MORE_INIT_SETTINGS
     431  printk("bsp_start: Going to start PCI buses scanning and initialization\n");
    401432#endif 
    402433  pci_initialize();
     
    406437#endif
    407438#ifdef TEST_RAW_EXCEPTION_CODE 
    408   printk("Testing exception handling Part 1\n");
     439  printk("bsp_start: Testing exception handling Part 1\n");
    409440
    410441  /*
     
    416447   * Check we can still catch exceptions and returned coorectly.
    417448   */
    418   printk("Testing exception handling Part 2\n");
     449  printk("bsp_start: Testing exception handling Part 2\n");
    419450  __asm__ __volatile ("sc");
    420451#endif 
    421452
    422453#ifdef SHOW_MORE_INIT_SETTINGS
    423   printk("rtems_configuration_get_work_space_size() = %x\n",
     454  printk("bsp_start: rtems_configuration_get_work_space_size() = %x\n",
    424455     rtems_configuration_get_work_space_size());
    425456#endif 
    426457  work_space_start =
    427     (unsigned char *)BSP_mem_size - rtems_configuration_get_work_space_size();
    428 
     458    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
    429459  if ( work_space_start <= ((unsigned char *)__rtems_end) +
    430460        INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size()) {
     
    432462    bsp_cleanup();
    433463  }
    434 
    435464  Configuration.work_space_start = work_space_start;
     465#ifdef SHOW_MORE_INIT_SETTINGS
     466  printk("bsp_start: workspace_start = 0x%x\n",
     467     work_space_start);
     468#endif 
     469
     470  #if ( PPC_USE_DATA_CACHE )
     471    #if DEBUG
     472      printk("bsp_start: cache_enable\n");
     473    #endif
     474    instruction_cache_enable ();
     475    data_cache_enable ();
     476    #if DEBUG
     477      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
     478    #endif
     479  #endif
     480
    436481
    437482  /*
    438483   * Initalize RTEMS IRQ system
    439484   */
     485#ifdef  SHOW_MORE_INIT_SETTINGS
     486    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
     487#endif
    440488  BSP_rtems_irq_mng_init(0);
    441489 
     
    446494  if (pt) {
    447495#ifdef  SHOW_MORE_INIT_SETTINGS
    448     printk("Page table setup finished; will activate it NOW...\n");
     496    printk("bspstart: Page table setup finished; will activate it NOW...\n");
    449497#endif
    450498    BSP_pgtbl_activate(pt);
     
    456504   */
    457505#ifdef SHOW_MORE_INIT_SETTINGS
    458   printk("Going to initialize VME bridge\n");
     506  printk("bspstart: Going to initialize VME bridge\n");
    459507#endif
    460508  /* VME initialization is in a separate file so apps which don't use
  • c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds

    raf46ad9 rfb557a9  
    153153   PROVIDE (__bss_end = .);
    154154  }
    155   . =  ALIGN(8) + 0x8000;
     155  . =  ALIGN(0x100);
     156  PROVIDE (__stackLow = .);
     157  . += 0x8000;
    156158  PROVIDE (__stack = .);
    157159  _end = . ;
  • c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h

    raf46ad9 rfb557a9  
    7878 */
    7979#undef  _VME_DRAM_OFFSET
    80 #define _VME_DRAM_OFFSET                0xc0000000 
     80/* #define _VME_DRAM_OFFSET                0xc0000000   */
     81
    8182#define _VME_DRAM_32_OFFSET1            0x20000000
    8283#define _VME_DRAM_32_OFFSET2            0x20b00000
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