Index: c/src/exec/score/cpu/h8300/cpu_asm.S
===================================================================
--- c/src/exec/score/cpu/h8300/cpu_asm.S	(revision 237c2598510a6f4844577717741b1bee0299e4ab)
+++ c/src/exec/score/cpu/h8300/cpu_asm.S	(revision fb31e1a2e7c0598ff9fd62a98134114b9c5ff6fb)
@@ -19,18 +19,18 @@
 ;.equ	HEIRCONTEXT_ARG, er1
 	
-
-/*
+/*      
  *  Make sure we tell the assembler what type of CPU model we are
  *  being compiled for.
- */
+ */ 
 
 #if defined(__H8300H__)
-	.h8300h
+        .h8300h
 #endif
-#if defined(__H8300S__)
-	.h8300s
+#if defined(__H8300S__) 
+        .h8300s
 #endif
+        .text
+
 	.text
-
 /*
 	GCC Compiled with optimisations and Wimplicit decs to ensure
@@ -44,9 +44,10 @@
 
 	.align 2
+
 	.global	__CPU_Context_switch
+
 __CPU_Context_switch:
-#if defined(__H8300H__) || defined(__H8300S__)
 	/* Save Context */
-	stc	ccr,@(0:16,er0)
+	stc.w	ccr,@(0:16,er0)
 	mov.l	er7,@(2:16,er0)
 	mov.l	er6,@(6:16,er0)
@@ -65,17 +66,16 @@
 	mov.l	@(6:16,er1),er6
 	mov.l	@(2:16,er1),er7
-	ldc	@(0:16,er1),ccr
-#endif
+	ldc.w	@(0:16,er1),ccr
+
 	rts
 
 	.align 2
+
 	.global	__CPU_Context_restore
+
 __CPU_Context_restore:
-#if defined(__H8300H__) || defined(__H8300S__)
-	mov.l	er0,er1
-	jmp	@restore:24
-#else
-	rts
-#endif
+	
+	Mov.l	er0,er1
+	jmp		@restore:24
 
 
@@ -97,5 +97,4 @@
 	
 __ISR_Handler:
-#if defined(__H8300H__) || defined(__H8300S__)
 	mov.l	er1,@-er7
 	mov.l	er2,@-er7
@@ -106,5 +105,5 @@
 	
 /*  Set IRQ Stack */
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 	mov.l	er7,er6		; save stack pointer
 	mov.l	@__ISR_Nest_level,er1
@@ -133,5 +132,5 @@
 	jsr		@er1	; er0 = arg1 =vector
 	
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 	mov.l	@__ISR_Nest_level,er1
 	dec.l	#1,er1
@@ -151,5 +150,5 @@
 	
 bframe:
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 /*	Pop Stack	*/
 	mov		@er7+,er6
@@ -160,10 +159,5 @@
 	/* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
 	
-	stc		ccr,@er2
-	and.l	#0xff,er2	
-	rotr.l	er2
-	rotr.l	er2
-	rotr.l	er2
-	rotr.l	er2
+	mov.l	#0xc0000000,er2		/* Disable IRQ */
 	or.l	#_ISR_Dispatch,er2
 	mov.l	er2,@-er7
@@ -176,29 +170,4 @@
 	mov		@er7+,er6
 	mov		er6,er7
-	andc	#0x7f,ccr
-	mov		@er7+,er6
-	mov		@er7+,er5
-	mov		@er7+,er4
-	mov		@er7+,er3
-	mov		@er7+,er2
-	mov		@er7+,er1
-	mov		@er7+,er0
-	andc	#0x7f,ccr
-	rte
-#endif
-	
-/*
-	Called from ISR_Handler as a way of ending IRQ
-	but allowing dispatch to another task.
-	Must use RTE as CCR is still on stack but IRQ has been serviced.	
-	CCR and PC occupy same word so rte can be used.
-*/
-
-	.align 2
-	.global _ISR_Dispatch
-
-_ISR_Dispatch:
-#if defined(__H8300H__) || defined(__H8300S__)
-	jsr		@__Thread_Dispatch
 	mov		@er7+,er6
 	mov		@er7+,er5
@@ -209,5 +178,27 @@
 	mov		@er7+,er0
 	rte
-#endif
+	
+/*
+	Called from ISR_Handler as a way of ending IRQ
+	but allowing dispatch to another task.
+	Must use RTE as CCR is still on stack but IRQ has been serviced.	
+	CCR and PC occupy same word so rte can be used.
+	now using task stack
+*/
+
+	.align 2
+	.global _ISR_Dispatch
+
+_ISR_Dispatch:
+	
+	Jsr		@__Thread_Dispatch
+	mov		@er7+,er6
+	mov		@er7+,er5
+	mov		@er7+,er4
+	mov		@er7+,er3
+	mov		@er7+,er2
+	mov		@er7+,er1
+	mov		@er7+,er0
+	rte
 	
 
Index: c/src/exec/score/cpu/h8300/rtems/score/cpu.h
===================================================================
--- c/src/exec/score/cpu/h8300/rtems/score/cpu.h	(revision 237c2598510a6f4844577717741b1bee0299e4ab)
+++ c/src/exec/score/cpu/h8300/rtems/score/cpu.h	(revision fb31e1a2e7c0598ff9fd62a98134114b9c5ff6fb)
@@ -604,11 +604,59 @@
 /* ISR handler macros */
 
+/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
+   Note requires ISR_Level be unsigned16 or assembler croaks.
+*/
+
+#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
+
+
 /*
  *  Disable all interrupts for an RTEMS critical section.  The previous
  *  level is returned in _level.
- *
- *  H8300 Specific Information:
- *
- *  XXX  FIXME this does not nest properly for the H8300.
+ */
+
+#define _CPU_ISR_Disable( _isr_cookie ) \
+  do { \
+    asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+
+/*
+ *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  _level is not modified.
+ */
+
+
+#define _CPU_ISR_Enable( _isr_cookie )  \
+  do { \
+    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+
+/*
+ *  This temporarily restores the interrupt to _level before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter _level is not
+ * modified.
+ */
+
+
+#define _CPU_ISR_Flash( _isr_cookie ) \
+  do { \
+    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+/* end of ISR handler macros */
+
+#else
+
+/*
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in _level.
+ *
+ *  H8300 Specific Information:
+ *
+ *  XXX  
  */
 
@@ -669,4 +717,6 @@
   } while (0) 
 #endif
+
+#endif /* end of old gcc */
 
 
Index: cpukit/score/cpu/h8300/cpu_asm.S
===================================================================
--- cpukit/score/cpu/h8300/cpu_asm.S	(revision 237c2598510a6f4844577717741b1bee0299e4ab)
+++ cpukit/score/cpu/h8300/cpu_asm.S	(revision fb31e1a2e7c0598ff9fd62a98134114b9c5ff6fb)
@@ -19,18 +19,18 @@
 ;.equ	HEIRCONTEXT_ARG, er1
 	
-
-/*
+/*      
  *  Make sure we tell the assembler what type of CPU model we are
  *  being compiled for.
- */
+ */ 
 
 #if defined(__H8300H__)
-	.h8300h
+        .h8300h
 #endif
-#if defined(__H8300S__)
-	.h8300s
+#if defined(__H8300S__) 
+        .h8300s
 #endif
+        .text
+
 	.text
-
 /*
 	GCC Compiled with optimisations and Wimplicit decs to ensure
@@ -44,9 +44,10 @@
 
 	.align 2
+
 	.global	__CPU_Context_switch
+
 __CPU_Context_switch:
-#if defined(__H8300H__) || defined(__H8300S__)
 	/* Save Context */
-	stc	ccr,@(0:16,er0)
+	stc.w	ccr,@(0:16,er0)
 	mov.l	er7,@(2:16,er0)
 	mov.l	er6,@(6:16,er0)
@@ -65,17 +66,16 @@
 	mov.l	@(6:16,er1),er6
 	mov.l	@(2:16,er1),er7
-	ldc	@(0:16,er1),ccr
-#endif
+	ldc.w	@(0:16,er1),ccr
+
 	rts
 
 	.align 2
+
 	.global	__CPU_Context_restore
+
 __CPU_Context_restore:
-#if defined(__H8300H__) || defined(__H8300S__)
-	mov.l	er0,er1
-	jmp	@restore:24
-#else
-	rts
-#endif
+	
+	Mov.l	er0,er1
+	jmp		@restore:24
 
 
@@ -97,5 +97,4 @@
 	
 __ISR_Handler:
-#if defined(__H8300H__) || defined(__H8300S__)
 	mov.l	er1,@-er7
 	mov.l	er2,@-er7
@@ -106,5 +105,5 @@
 	
 /*  Set IRQ Stack */
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 	mov.l	er7,er6		; save stack pointer
 	mov.l	@__ISR_Nest_level,er1
@@ -133,5 +132,5 @@
 	jsr		@er1	; er0 = arg1 =vector
 	
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 	mov.l	@__ISR_Nest_level,er1
 	dec.l	#1,er1
@@ -151,5 +150,5 @@
 	
 bframe:
-	orc		#0x80,ccr
+	orc		#0xc0,ccr
 /*	Pop Stack	*/
 	mov		@er7+,er6
@@ -160,10 +159,5 @@
 	/* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
 	
-	stc		ccr,@er2
-	and.l	#0xff,er2	
-	rotr.l	er2
-	rotr.l	er2
-	rotr.l	er2
-	rotr.l	er2
+	mov.l	#0xc0000000,er2		/* Disable IRQ */
 	or.l	#_ISR_Dispatch,er2
 	mov.l	er2,@-er7
@@ -176,29 +170,4 @@
 	mov		@er7+,er6
 	mov		er6,er7
-	andc	#0x7f,ccr
-	mov		@er7+,er6
-	mov		@er7+,er5
-	mov		@er7+,er4
-	mov		@er7+,er3
-	mov		@er7+,er2
-	mov		@er7+,er1
-	mov		@er7+,er0
-	andc	#0x7f,ccr
-	rte
-#endif
-	
-/*
-	Called from ISR_Handler as a way of ending IRQ
-	but allowing dispatch to another task.
-	Must use RTE as CCR is still on stack but IRQ has been serviced.	
-	CCR and PC occupy same word so rte can be used.
-*/
-
-	.align 2
-	.global _ISR_Dispatch
-
-_ISR_Dispatch:
-#if defined(__H8300H__) || defined(__H8300S__)
-	jsr		@__Thread_Dispatch
 	mov		@er7+,er6
 	mov		@er7+,er5
@@ -209,5 +178,27 @@
 	mov		@er7+,er0
 	rte
-#endif
+	
+/*
+	Called from ISR_Handler as a way of ending IRQ
+	but allowing dispatch to another task.
+	Must use RTE as CCR is still on stack but IRQ has been serviced.	
+	CCR and PC occupy same word so rte can be used.
+	now using task stack
+*/
+
+	.align 2
+	.global _ISR_Dispatch
+
+_ISR_Dispatch:
+	
+	Jsr		@__Thread_Dispatch
+	mov		@er7+,er6
+	mov		@er7+,er5
+	mov		@er7+,er4
+	mov		@er7+,er3
+	mov		@er7+,er2
+	mov		@er7+,er1
+	mov		@er7+,er0
+	rte
 	
 
Index: cpukit/score/cpu/h8300/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/h8300/rtems/score/cpu.h	(revision 237c2598510a6f4844577717741b1bee0299e4ab)
+++ cpukit/score/cpu/h8300/rtems/score/cpu.h	(revision fb31e1a2e7c0598ff9fd62a98134114b9c5ff6fb)
@@ -604,11 +604,59 @@
 /* ISR handler macros */
 
+/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
+   Note requires ISR_Level be unsigned16 or assembler croaks.
+*/
+
+#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
+
+
 /*
  *  Disable all interrupts for an RTEMS critical section.  The previous
  *  level is returned in _level.
- *
- *  H8300 Specific Information:
- *
- *  XXX  FIXME this does not nest properly for the H8300.
+ */
+
+#define _CPU_ISR_Disable( _isr_cookie ) \
+  do { \
+    asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+
+/*
+ *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  _level is not modified.
+ */
+
+
+#define _CPU_ISR_Enable( _isr_cookie )  \
+  do { \
+    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+
+/*
+ *  This temporarily restores the interrupt to _level before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter _level is not
+ * modified.
+ */
+
+
+#define _CPU_ISR_Flash( _isr_cookie ) \
+  do { \
+    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
+  } while (0)
+
+/* end of ISR handler macros */
+
+#else
+
+/*
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in _level.
+ *
+ *  H8300 Specific Information:
+ *
+ *  XXX  
  */
 
@@ -669,4 +717,6 @@
   } while (0) 
 #endif
+
+#endif /* end of old gcc */
 
 
