Changeset faaffbd9 in rtems


Ignore:
Timestamp:
02/25/22 16:45:06 (7 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
a286d28
Parents:
4b09a4c7
git-author:
Sebastian Huber <sebastian.huber@…> (02/25/22 16:45:06)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/25/22 19:38:20)
Message:

riscv: Use zicsr architecture extension

This is required for ISA 2.0 support, see chapter

"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0

in

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA

Files:
7 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/griscv/clock/clockdrv.c

    r4b09a4c7 rfaaffbd9  
    188188  unsigned long timec;
    189189
    190   __asm__ volatile ( "csrr %0, time" : "=&r" ( timec ) );
     190  __asm__ volatile (
     191    ".option push\n"
     192    ".option arch, +zicsr\n"
     193    "csrr %0, time\n"
     194    ".option pop" :
     195    "=&r" ( timec )
     196  );
    191197
    192198  return timec;
  • bsps/riscv/shared/start/start.S

    r4b09a4c7 rfaaffbd9  
    4040        .section        .bsp_start_text, "wax", @progbits
    4141        .align  2
     42        .option arch, +zicsr
    4243
    4344TYPE_FUNC(_start)
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r4b09a4c7 rfaaffbd9  
    153153
    154154  __asm__ volatile (
    155     "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) :
     155    ".option push\n"
     156    ".option arch, +zicsr\n"
     157    "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
     158    ".option pop" :
    156159      "=&r" ( mstatus )
    157160  );
     
    162165static inline void riscv_interrupt_enable( uint32_t level )
    163166{
    164   __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) );
     167  __asm__ volatile (
     168    ".option push\n"
     169    ".option arch, +zicsr\n"
     170    "csrrs zero, mstatus, %0\n"
     171    ".option pop" :
     172    :
     173    "r" ( level )
     174  );
    165175}
    166176
     
    186196  if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
    187197    __asm__ volatile (
    188       "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
     198      ".option push\n"
     199      ".option arch, +zicsr\n"
     200      "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
     201      ".option pop"
    189202    );
    190203  } else {
    191204    __asm__ volatile (
    192       "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
     205      ".option push\n"
     206      ".option arch, +zicsr\n"
     207      "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
     208      ".option pop"
    193209    );
    194210  }
     
    466482  unsigned long mhartid;
    467483
    468   __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) );
     484  __asm__ volatile (
     485    ".option push\n"
     486    ".option arch, +zicsr\n"
     487    "csrr %0, mhartid\n"
     488    ".option pop" :
     489    "=&r" ( mhartid )
     490  );
    469491
    470492  return (uint32_t) mhartid;
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r4b09a4c7 rfaaffbd9  
    400400  struct Per_CPU_Control *cpu_self;
    401401
    402   __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
     402  __asm__ volatile (
     403    ".option push\n"
     404    ".option arch, +zicsr\n"
     405    "csrr %0, mscratch\n"
     406    ".option pop" :
     407    "=r" ( cpu_self )
     408  );
    403409
    404410  return cpu_self;
  • cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h

    r4b09a4c7 rfaaffbd9  
    248248
    249249#define read_csr(reg) ({ unsigned long __tmp; \
    250   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
     250  asm volatile (".option push\n.option arch, +zicsr\n" \
     251  "csrr %0, " #reg "\n.option pop ": "=r"(__tmp)); \
    251252  __tmp; })
    252253
    253254#define write_csr(reg, val) ({ \
    254   asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
     255  asm volatile (".option push\n.option arch, +zicsr\n" \
     256  "csrw " #reg ", %0\n.option pop" :: "rK"(val)); })
    255257
    256258#define swap_csr(reg, val) ({ unsigned long __tmp; \
    257   asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
     259  asm volatile (".option push\n.option arch, +zicsr\n" \
     260  "csrrw %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(val)); \
    258261  __tmp; })
    259262
    260263#define set_csr(reg, bit) ({ unsigned long __tmp; \
    261   asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
     264  asm volatile (".option push\n.option arch, +zicsr\nc" \
     265  "srrs %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
    262266  __tmp; })
    263267
    264268#define clear_csr(reg, bit) ({ unsigned long __tmp; \
    265   asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
     269  asm volatile (".option push\n.option arch, +zicsr\n" \
     270  "csrrc %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
    266271  __tmp; })
    267272
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    r4b09a4c7 rfaaffbd9  
    3636        .section        .text, "ax", @progbits
    3737        .align  2
     38        .option arch, +zicsr
    3839
    3940PUBLIC(_CPU_Context_switch)
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r4b09a4c7 rfaaffbd9  
    4646        .section        .text, "ax", @progbits
    4747        .align  2
     48        .option arch, +zicsr
    4849
    4950TYPE_FUNC(_RISCV_Exception_handler)
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