Changeset faaffbd9 in rtems

Timestamp:

02/25/22 16:45:06 (21 months ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

master

Children:

a286d28

Parents:

4b09a4c7

git-author:

Sebastian Huber <sebastian.huber@…> (02/25/22 16:45:06)

git-committer:

Sebastian Huber <sebastian.huber@…> (02/25/22 19:38:20)

Message:

riscv: Use zicsr architecture extension

This is required for ISA 2.0 support, see chapter

"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0

in

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA

Files:

• bsps/riscv/griscv/clock/clockdrv.c (modified) (1 diff)
• bsps/riscv/shared/start/start.S (modified) (1 diff)
• cpukit/score/cpu/riscv/include/rtems/score/cpu.h (modified) (4 diffs)
• cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h (modified) (1 diff)
• cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h (modified) (1 diff)
• cpukit/score/cpu/riscv/riscv-context-switch.S (modified) (1 diff)
• cpukit/score/cpu/riscv/riscv-exception-handler.S (modified) (1 diff)

bsps/riscv/griscv/clock/clockdrv.c

@@ -188 +188 @@
   unsigned long timec;
 
-  __asm__ volatile ( "csrr %0, time" : "=&r" ( timec ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrr %0, time\n"
+    ".option pop" :
+    "=&r" ( timec )
+  );
 
   return timec;

bsps/riscv/shared/start/start.S

@@ -40 +40 @@
         .section        .bsp_start_text, "wax", @progbits
         .align  2
+        .option arch, +zicsr
 
 TYPE_FUNC(_start)

cpukit/score/cpu/riscv/include/rtems/score/cpu.h

@@ -153 +153 @@
 
   __asm__ volatile (
-    "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) :
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+    ".option pop" :
       "=&r" ( mstatus )
   );
@@ -162 +165 @@
 static inline void riscv_interrupt_enable( uint32_t level )
 {
-  __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrrs zero, mstatus, %0\n"
+    ".option pop" :
+    :
+    "r" ( level )
+  );
 }
 
@@ -186 +196 @@
   if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
     __asm__ volatile (
-      "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
+      ".option push\n"
+      ".option arch, +zicsr\n"
+      "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+      ".option pop"
     );
   } else {
     __asm__ volatile (
-      "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
+      ".option push\n"
+      ".option arch, +zicsr\n"
+      "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+      ".option pop"
     );
   }
@@ -466 +482 @@
   unsigned long mhartid;
 
-  __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrr %0, mhartid\n"
+    ".option pop" :
+    "=&r" ( mhartid )
+  );
 
   return (uint32_t) mhartid;

cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

@@ -400 +400 @@
   struct Per_CPU_Control *cpu_self;
 
-  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrr %0, mscratch\n"
+    ".option pop" :
+    "=r" ( cpu_self )
+  );
 
   return cpu_self;

cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h

@@ -248 +248 @@
 
 #define read_csr(reg) ({ unsigned long __tmp; \
-  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  asm volatile (".option push\n.option arch, +zicsr\n" \
+  "csrr %0, " #reg "\n.option pop ": "=r"(__tmp)); \
   __tmp; })
 
 #define write_csr(reg, val) ({ \
-  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+  asm volatile (".option push\n.option arch, +zicsr\n" \
+  "csrw " #reg ", %0\n.option pop" :: "rK"(val)); })
 
 #define swap_csr(reg, val) ({ unsigned long __tmp; \
-  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+  asm volatile (".option push\n.option arch, +zicsr\n" \
+  "csrrw %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(val)); \
   __tmp; })
 
 #define set_csr(reg, bit) ({ unsigned long __tmp; \
-  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  asm volatile (".option push\n.option arch, +zicsr\nc" \
+  "srrs %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
   __tmp; })
 
 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
-  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  asm volatile (".option push\n.option arch, +zicsr\n" \
+  "csrrc %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
   __tmp; })
 

cpukit/score/cpu/riscv/riscv-context-switch.S

@@ -36 +36 @@
         .section        .text, "ax", @progbits
         .align  2
+        .option arch, +zicsr
 
 PUBLIC(_CPU_Context_switch)

cpukit/score/cpu/riscv/riscv-exception-handler.S

@@ -46 +46 @@
         .section        .text, "ax", @progbits
         .align  2
+        .option arch, +zicsr
 
 TYPE_FUNC(_RISCV_Exception_handler)