Changeset fa9fa1e4 in rtems


Ignore:
Timestamp:
Jan 28, 2005, 7:48:25 PM (15 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
547b04f
Parents:
ed71774a
Message:

ColdFire? ISA A+ instructions.

Location:
cpukit/score/cpu/m68k
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/m68k/ChangeLog

    red71774a rfa9fa1e4  
     12005-01-28      Eric Norum <norume@aps.anl.gov>
     2
     3        * rtems/score/cpu.h, rtems/score/m68k.h: ColdFire ISA A+ instructions
     4
    152004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
    26
  • cpukit/score/cpu/m68k/rtems/score/cpu.h

    red71774a rfa9fa1e4  
    481481#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    482482  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
     483
     484#elif ( M68K_HAS_ISA_APLUS == 1 )
     485  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
     486#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
     487    asm volatile ( \
     488       "   swap     %0\n"        \
     489       "   ff1.l    %0\n"        \
     490       : "=d" ((_output))        \
     491       : "0" ((_value))          \
     492       : "cc" ) ;
     493
    483494#else
    484 
    485495/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
    486496   _CPU_Priority_bits_index is not needed), handles the 0 case, and
  • cpukit/score/cpu/m68k/rtems/score/m68k.h

    red71774a rfa9fa1e4  
    4646 *     -mcpu32        (no FP)
    4747 *     -m5200         (no FP)
     48 *     -m528x         (no FP, ISA A+)
    4849 *
    4950 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
     
    197198#define M68K_HAS_FPSP_PACKAGE    0
    198199
     200#elif defined(__mcf528x__)
     201/* Motorola ColdFire ISA A+ - RISC/68020 hybrid */
     202#define CPU_MODEL_NAME         "m528x"
     203#define M68K_HAS_VBR             1
     204#define M68K_HAS_BFFFO           0
     205#define M68K_HAS_SEPARATE_STACKS 0
     206#define M68K_HAS_PREINDEXING     0
     207#define M68K_HAS_EXTB_L          1
     208#define M68K_HAS_MISALIGNED      1
     209#define M68K_HAS_FPU             0
     210#define M68K_HAS_FPSP_PACKAGE    0
     211#define M68K_COLDFIRE_ARCH       1
     212#define M68K_HAS_ISA_APLUS       1
     213
    199214#elif defined(__mcf5200__)
    200215/* Motorola ColdFire V2 core - RISC/68020 hybrid */
     
    209224#define M68K_HAS_FPSP_PACKAGE    0
    210225#define M68K_COLDFIRE_ARCH       1
     226#define M68K_HAS_ISA_APLUS       0
    211227
    212228#elif defined(__mc68000__)
     
    317333
    318334#elif ( M68K_COLDFIRE_ARCH == 1 )
    319 #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
    320 
    321 #define m68k_set_vbr( _vbr ) \
    322     asm volatile ("move.l  %%a7,%%d1 \n\t" \
    323                   "move.l  %0,%%a7\n\t"    \
    324                   "movec   %%a7,%%vbr\n\t" \
    325                   "move.l  %%d1,%%a7\n\t" \
    326                   : : "d" (_vbr) : "d1" );
     335extern void *_ColdFire_VBR;
     336#define m68k_get_vbr( _vbr ) _vbr = _ColdFire_VBR
     337
     338#define m68k_set_vbr( vbr ) \
     339  do { \
     340    asm volatile ( "movec   %0,%%vbr " : : "r" (vbr)); \
     341    _ColdFire_VBR = (void *)vbr; \
     342  } while(0)
    327343 
    328344#else
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