Timestamp:
05/29/14 19:09:00 (10 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, 5, master
Children:
fad33860
Parents:
33ba808
git-author:
Daniel Hellstrom <daniel@…> (05/29/14 19:09:00)
git-committer:
Daniel Hellstrom <daniel@…> (10/09/14 07:07:22)
Message:

SPARC BSPs: added CPU aware interrupt ctrl operations

The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.

(No files)

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