Changeset fa27fe5c in rtems


Ignore:
Timestamp:
04/25/17 13:26:18 (6 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
5, master
Children:
011efee8
Parents:
8ac070a
git-author:
Daniel Hellstrom <daniel@…> (04/25/17 13:26:18)
git-committer:
Daniel Hellstrom <daniel@…> (05/14/17 10:31:56)
Message:

leon, greth: new option and change soft-reset logic for EDCL

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/net/greth.c

    r8ac070a rfa27fe5c  
    156156   int phyaddr;  /* PHY Address configured by user (or -1 to autodetect) */
    157157   unsigned int edcl_dis;
     158   int greth_rst;
    158159
    159160   int acceptBroadcast;
     
    354355    struct timespec tstart, tnow;
    355356    greth_regs *regs;
    356     unsigned int advmodes;
     357    unsigned int advmodes, speed;
    357358
    358359    regs = sc->regs;
     
    362363    sc->rxPackets = 0;
    363364
    364     regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
    365     for (i = 0; i<100 && (regs->ctrl & GRETH_CTRL_RST); i++)
    366         ;
    367     regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset OFF. SW do PHY Init */
     365    if (sc->greth_rst) {
     366        /* Reset ON */
     367        regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     368        for (i = 0; i<100 && (regs->ctrl & GRETH_CTRL_RST); i++)
     369            ;
     370        speed = 0; /* probe mode below */
     371    } else {
     372        /* inherit EDCL mode for now */
     373        speed = sc->regs->ctrl & (GRETH_CTRL_GB|GRETH_CTRL_SP|GRETH_CTRL_FULLD);
     374    }
     375    /* Reset OFF and RX/TX DMA OFF. SW do PHY Init */
     376    regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed;
    368377
    369378    /* Check if mac is gbit capable*/
     
    527536    while ((read_mii(sc, phyaddr, 0)) & 0x8000) {}
    528537
    529     regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
    530     for (i = 0; i < 100 && (regs->ctrl & GRETH_CTRL_RST); i++)
    531         ;
    532     regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis; /* Reset OFF. SW do PHY Init */
     538    if (sc->greth_rst) {
     539        /* Reset ON */
     540        regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     541        for (i = 0; i < 100 && (regs->ctrl & GRETH_CTRL_RST); i++)
     542            ;
     543    }
     544    /* Reset OFF. Set mode matching PHY settings. */
     545    speed = (sc->gb << 8) | (sc->sp << 7) | (sc->fd << 4);
     546    regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed;
    533547
    534548    /* Initialize rx/tx descriptor table pointers. Due to alignment we
     
    617631    drvmgr_interrupt_register(sc->dev, 0, "greth", greth_interrupt, sc);
    618632
    619     regs->ctrl |= GRETH_CTRL_RXEN | (sc->fd << 4) | GRETH_CTRL_RXIRQ | (sc->sp << 7) | (sc->gb << 8);
     633    regs->ctrl |= GRETH_CTRL_RXEN | GRETH_CTRL_RXIRQ;
    620634
    621635    print_init_info(sc);
     
    11791193    struct ifnet *ifp = &sc->arpcom.ac_if;
    11801194    SPIN_IRQFLAGS(flags);
     1195    unsigned int speed;
    11811196
    11821197    SPIN_LOCK_IRQ(&sc->devlock, flags);
    11831198    ifp->if_flags &= ~IFF_RUNNING;
    11841199
     1200    speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD);
     1201
    11851202    /* RX/TX OFF */
    1186     sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
     1203    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed;
    11871204    /* Reset ON */
    1188     sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     1205    if (sc->greth_rst)
     1206        sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED | speed;
    11891207    /* Reset OFF and restore link settings previously detected if any */
    1190     sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis |
    1191                      (sc->gb << 8) | (sc->sp << 7) | (sc->fd << 4);
     1208    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed;
    11921209    SPIN_UNLOCK_IRQ(&sc->devlock, flags);
    11931210
     
    14611478    sc->regs = (greth_regs *)pnpinfo->apb_slv->start;
    14621479    sc->minor = sc->dev->minor_drv;
     1480    sc->greth_rst = 1;
    14631481
    14641482    /* Remember EDCL enabled/disable state before reset */
     
    14691487    if ( value ) {
    14701488        /* Force EDCL mode. Has an effect later when GRETH+PHY is initialized */
    1471         if (value->i > 0)
     1489        if (value->i > 0) {
    14721490            sc->edcl_dis = GRETH_CTRL_ED;
    1473         else
     1491        } else {
     1492            /* Default to avoid soft-reset the GRETH when EDCL is forced */
    14741493            sc->edcl_dis = 0;
     1494            sc->greth_rst = 0;
     1495        }
     1496    }
     1497
     1498    /* let user control soft-reset of GRETH (for debug) */
     1499    value = drvmgr_dev_key_get(sc->dev, "soft-reset", DRVMGR_KT_INT);
     1500    if ( value) {
     1501        sc->greth_rst = value->i ? 1 : 0;
    14751502    }
    14761503
     
    14781505     * This should be done as quick as possible during startup, this is to
    14791506     * stop DMA transfers after a reboot.
     1507     *
     1508     * When EDCL is forced enabled reset is skipped, disabling RX/TX DMA is
     1509     * is enough during debug.
    14801510     */
    14811511    speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD);
    1482     sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
    1483     sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     1512    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED | speed;
     1513    if (sc->greth_rst)
     1514        sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED | speed;
    14841515    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed;
    14851516
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