Changeset fa237002 in rtems


Ignore:
Timestamp:
Jul 30, 2002, 11:16:40 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
8c408ed4
Parents:
5ba286f
Message:

2002-07-30 Jay Monkman <jtm@…>

  • cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works well enough to run all sptests, tmtests, and ttcp. In addition to general cleanup, there has been considerable optimization to interrupt disable/enable, endian swapping, and context switching.
Location:
cpukit/score/cpu/arm
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/ChangeLog

    r5ba286f rfa237002  
     12002-07-30      Jay Monkman <jtm@smoothsmoothie.com>
     2
     3        * cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h,
     4        rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works
     5        well enough to run all sptests, tmtests, and ttcp. 
     6        In addition to general cleanup, there has been considerable
     7        optimization to interrupt disable/enable, endian swapping,
     8        and context switching.
     9
    1102002-07-26      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    211
  • cpukit/score/cpu/arm/cpu.c

    r5ba286f rfa237002  
    3333 */
    3434
     35unsigned32 g_data_abort_cnt = 0;
     36unsigned32 g_data_abort_insn_list[1024];
     37
    3538void _CPU_Initialize(
    3639  rtems_cpu_table  *cpu_table,
     
    5255    asm volatile ("mrs  %0, cpsr \n"           \
    5356                  "and  %0,  %0, #0xc0 \n"     \
    54                   : "=r" (reg));
     57                  : "=r" (reg)                 \
     58                  : "0" (reg) );
    5559   
    5660    return reg;
     
    102106)
    103107{
    104     the_context->register_sp = ((unsigned32)(stack_base)) + (size) ;
    105     the_context->register_pc = (entry_point);
    106     the_context->register_cpsr = (new_level | 0x13);
    107 }
    108 
    109 /*PAGE
    110  *
    111  *  _CPU_Install_interrupt_stack
     108    the_context->register_sp = (unsigned32)stack_base + size ;
     109    the_context->register_lr = (unsigned32)entry_point;
     110    the_context->register_cpsr = new_level | 0x13;
     111}
     112
     113
     114/*
     115 *  _CPU_Install_interrupt_stack - this function is empty since the
     116 *  BSP must set up the interrupt stacks.
    112117 */
    113118
    114119void _CPU_Install_interrupt_stack( void )
    115120{
    116 /* FIXME: do something here */
    117 #if 0
    118     extern unsigned long _fiq_stack;
    119     extern unsigned long _fiq_stack_size;
    120     extern unsigned long _irq_stack;
    121     extern unsigned long _irq_stack_size;
    122     extern unsigned long _abt_stack;
    123     extern unsigned long _abt_stack_size;
    124     unsigned long *ptr;
    125     int i;
    126 
    127     ptr = &_fiq_stack;
    128     for (i = 0; i < ((int)&_fiq_stack_size/4); i++) {
    129         ptr[i] = 0x13131313;
    130     }
    131 
    132     ptr = &_irq_stack;
    133     for (i = 0; i < ((int)&_irq_stack_size/4); i++) {
    134         ptr[i] = 0xf0f0f0f0;
    135     }
    136 
    137     ptr = &_abt_stack;
    138     for (i = 0; i < ((int)&_abt_stack_size/4); i++) {
    139         ptr[i] = 0x55555555;
    140     }
    141 #endif
    142 }
    143 
    144 /*PAGE
    145  *
    146  *  _CPU_Thread_Idle_body
    147  *
    148  *  NOTES:
    149  *
    150  *  1. This is the same as the regular CPU independent algorithm.
    151  *
    152  *  2. If you implement this using a "halt", "idle", or "shutdown"
    153  *     instruction, then don't forget to put it in an infinite loop.
    154  *
    155  *  3. Be warned. Some processors with onboard DMA have been known
    156  *     to stop the DMA if the CPU were put in IDLE mode.  This might
    157  *     also be a problem with other on-chip peripherals.  So use this
    158  *     hook with caution.
    159  */
    160 
    161 void _CPU_Thread_Idle_body( void )
    162 {
    163 
    164     while(1); /* FIXME: finish this */
    165     /* insert your "halt" instruction here */ ;
    166121}
    167122
     
    170125    printk("\n\r");
    171126    printk("----------------------------------------------------------\n\r");
     127#if 0
    172128    printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
    173129           ctx->register_pc, ctx->register_lr - 4,
    174130           _Thread_Executing->Object.id);
     131#endif
    175132    printk("----------------------------------------------------------\n\r");
    176133    printk("Processor execution context at time of the fault was  :\n\r");
    177134    printk("----------------------------------------------------------\n\r");
     135#if 0
    178136    printk(" r0  = %8x  r1  = %8x  r2  = %8x  r3  = %8x\n\r",
    179137           ctx->register_r0, ctx->register_r1,
     
    188146           ctx->register_sp, ctx->register_lr - 4);
    189147    printk("----------------------------------------------------------\n\r");
    190    
     148#endif   
    191149    if (_ISR_Nest_level > 0) {
    192150        /*
     
    208166extern void _Exception_Handler_Undef_Swi();
    209167extern void _Exception_Handler_Abort();
     168extern void _exc_data_abort();
    210169/* FIXME: put comments here */
    211170void rtems_exception_init_mngt()
     
    227186     
    228187      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
    229                               _Exception_Handler_Abort,
     188                              _exc_data_abort,
    230189                              NULL);
    231190     
     
    241200}
    242201 
    243 
     202#define INSN_MASK         0xc5
     203
     204#define INSN_STM1         0x80
     205#define INSN_STM2         0x84
     206#define INSN_STR          0x40
     207#define INSN_STRB         0x44
     208
     209#define INSN_LDM1         0x81
     210#define INSN_LDM23        0x85
     211#define INSN_LDR          0x41
     212#define INSN_LDRB         0x45
     213
     214#define GET_RD(x)         ((x & 0x0000f000) >> 12)
     215#define GET_RN(x)         ((x & 0x000f0000) >> 16)
     216
     217#define GET_U(x)              ((x & 0x00800000) >> 23)
     218#define GET_I(x)              ((x & 0x02000000) >> 25)
     219
     220#define GET_REG(r, ctx)      (((unsigned32 *)ctx)[r])
     221#define SET_REG(r, ctx, v)   (((unsigned32 *)ctx)[r] = v)
     222#define GET_OFFSET(insn)     (insn & 0xfff)
     223
     224
     225/* This function is supposed to figure out what caused the
     226 * data abort, do that, then return.
     227 *
     228 * All unhandled instructions cause the system to hang.
     229 */
     230
     231void do_data_abort(unsigned32 insn, unsigned32 spsr,
     232                   CPU_Exception_frame *ctx)
     233{
     234    unsigned8  decode;
     235    unsigned8  insn_type;
     236
     237    unsigned32 rn;
     238    unsigned32 rd;
     239
     240    unsigned8  *src_addr;
     241    unsigned8  *dest_addr;
     242    unsigned32  tmp;
     243
     244    g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
     245    g_data_abort_cnt++;
     246   
     247    decode = ((insn >> 20) & 0xff);
     248
     249    insn_type = decode & INSN_MASK;
     250    switch(insn_type) {
     251    case INSN_STM1:
     252        printk("\n\nINSN_STM1\n");
     253        break;
     254    case INSN_STM2:
     255        printk("\n\nINSN_STM2\n");
     256        break;
     257    case INSN_STR:
     258        printk("\n\nINSN_STR\n");
     259        break;
     260    case INSN_STRB:
     261        printk("\n\nINSN_STRB\n");
     262        break;
     263    case INSN_LDM1:
     264        printk("\n\nINSN_LDM1\n");
     265        break;
     266    case INSN_LDM23:
     267        printk("\n\nINSN_LDM23\n");
     268        break;
     269    case INSN_LDR:
     270        printk("\n\nINSN_LDR\n");
     271
     272        rn = GET_RN(insn);
     273        rd = GET_RD(insn);
     274
     275        /* immediate offset/index */
     276        if (GET_I(insn) == 0) {
     277            switch(decode & 0x12) {  /* P and W bits */
     278            case 0x00:  /* P=0, W=0 -> base is updated, post-indexed */
     279                printk("\tPost-indexed\n");
     280                break;
     281            case 0x02:  /* P=0, W=1 -> user mode access */
     282                printk("\tUser mode\n");
     283                break;
     284            case 0x10:  /* P=1, W=0 -> base not updated */
     285                src_addr = GET_REG(rn, ctx);
     286                if (GET_U(insn) == 0) {
     287                    src_addr -= GET_OFFSET(insn);
     288                } else {
     289                    src_addr += GET_OFFSET(insn);
     290                }
     291                tmp = (src_addr[0] |
     292                       (src_addr[1] << 8) |
     293                       (src_addr[2] << 16) |
     294                       (src_addr[3] << 24));
     295                SET_REG(rd, ctx, tmp);
     296                return;
     297                break;
     298            case 0x12:  /* P=1, W=1 -> base is updated, pre-indexed */
     299                printk("\tPre-indexed\n");
     300                break;
     301            }
     302        }
     303        break;
     304    case INSN_LDRB:
     305        printk("\n\nINSN_LDRB\n");
     306        break;
     307    default:
     308        printk("\n\nUnrecognized instruction\n");
     309        break;
     310    }
     311   
     312    printk("data_abort at address 0x%x, instruction: 0x%x,   spsr = 0x%x\n",
     313           ctx->register_lr - 8, insn, spsr);
     314
     315    /* disable interrupts, wait forever */
     316    _CPU_ISR_Disable(tmp);
     317    while(1) {
     318        continue;
     319    }
     320    return;
     321}
     322
     323
     324   
  • cpukit/score/cpu/arm/cpu_asm.S

    r5ba286f rfa237002  
    3232 *  restores the ones from where r1 points.
    3333 *
    34  *
    35  *  NOTE:  The function should be able to only save/restore the registers
    36  *         that would be saved by a C function since the others have already
    37  *         been saved.
    38  *       
    39  *         It should also be able to use the stm/ldm instructions.
     34 *  Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
     35 *  a 16 bit data bus.
    4036 *       
    4137 */
    42 
    4338        .globl _CPU_Context_switch
    4439_CPU_Context_switch:
    45 /* FIXME: This should use load and store multiple instructions */
    4640/* Start saving context */
    47         str     r2,  [r0, #REG_R2]
    48         str     r3,  [r0, #REG_R3]
    49         str     r4,  [r0, #REG_R4]
    50         str     r5,  [r0, #REG_R5]
    51         str     r6,  [r0, #REG_R6]
    52         str     r7,  [r0, #REG_R7]
    53         str     r8,  [r0, #REG_R8]
    54         str     r9,  [r0, #REG_R9]
    55         str     r10, [r0, #REG_R10]
    56        
    57         str     r11, [r0, #REG_R11]
    58         str     r12, [r0, #REG_R12]     
    59        
    60         str     sp,  [r0, #REG_SP]
    61         str     lr,  [r0, #REG_PC]     /* save LR at PC's location */
    62        
    6341        mrs     r2, cpsr
    64         str     r2,  [r0, #REG_CPSR]
     42        stmia   r0,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
     43
    6544
    6645/* Start restoring context */
    67         
    68         ldr     r2,  [r1, #REG_CPSR]
     46_restore:       
     47        ldmia   r1,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    6948        msr     cpsr, r2
    70 
    71         ldr     r2,  [r1, #REG_R2]
    72         ldr     r3,  [r1, #REG_R3]
    73         ldr     r4,  [r1, #REG_R4]
    74         ldr     r5,  [r1, #REG_R5]
    75         ldr     r6,  [r1, #REG_R6]
    76         ldr     r7,  [r1, #REG_R7]
    77         ldr     r8,  [r1, #REG_R8]
    78         ldr     r9,  [r1, #REG_R9]
    79         ldr     r10, [r1, #REG_R10]     
    80         ldr     r11, [r1, #REG_R11]
    81         ldr     r12, [r1, #REG_R12]     
    82        
    83         ldr     sp,  [r1, #REG_SP]
    84         ldr     lr,  [r1, #REG_PC]     
    8549        mov     pc, lr
    8650
     
    9155 *  It must match _CPU_Context_switch()
    9256 *
    93  *  NOTE:  The function should be able to only save/restore the registers
    94  *         that would be saved by a C function since the others have already
    95  *         been saved.
    96  *       
    97  *         It should also be able to use the stm/ldm instructions.
    98  *       
    9957 */
    10058        .globl _CPU_Context_restore
    10159_CPU_Context_restore:
    102 /* FIXME: This should use load and store multiple instructions */
    103         ldr     r2,  [r0, #REG_CPSR]
    104         msr     cpsr, r2
     60        mov     r1, r0
     61        b       _restore
    10562
    106         ldr     r2,  [r0, #REG_R2]     
    107         ldr     r3,  [r0, #REG_R3]
    108         ldr     r4,  [r0, #REG_R4]
    109         ldr     r5,  [r0, #REG_R5]
    110         ldr     r6,  [r0, #REG_R6]
    111         ldr     r7,  [r0, #REG_R7]
    112         ldr     r8,  [r0, #REG_R8]
    113         ldr     r9,  [r0, #REG_R9]
    114         ldr     r10, [r0, #REG_R10]     
    115         ldr     r11, [r1, #REG_R11]
    116         ldr     r12, [r1, #REG_R12]     
    117                        
    118         ldr     sp,  [r0, #REG_SP]
    119         ldr     lr,  [r0, #REG_PC]
    120         mov     pc,  lr
    12163
    12264
     
    12668/* FIXME: This should use load and store multiple instructions */
    12769        sub     r13,r13,#SIZE_REGS
    128         str     r0,  [r13, #REG_R0]
    129         str     r1,  [r13, #REG_R1]
    130         str     r2,  [r13, #REG_R2]
    131         str     r3,  [r13, #REG_R3]
    13270        str     r4,  [r13, #REG_R4]
    13371        str     r5,  [r13, #REG_R5]
     
    13876        str     r10, [r13, #REG_R10]
    13977        str     r11, [r13, #REG_R11]
    140         str     r12, [r13, #REG_R12]
    14178        str     sp,  [r13, #REG_SP]
    14279        str     lr,  [r13, #REG_LR]
     
    15087        ldr     pc,[r1]                         /* call handler  */
    15188_go_back_1:
    152         ldr     r0,  [r13, #REG_R0]
    153         ldr     r1,  [r13, #REG_R1]
    154         ldr     r2,  [r13, #REG_R2]
    155         ldr     r3,  [r13, #REG_R3]
    15689        ldr     r4,  [r13, #REG_R4]
    15790        ldr     r5,  [r13, #REG_R5]
     
    16295        ldr     r10, [r13, #REG_R10]
    16396        ldr     r11, [r13, #REG_R11]
    164         ldr     r12, [r13, #REG_R12]
    16597        ldr     sp,  [r13, #REG_SP]
    16698        ldr     lr,  [r13, #REG_LR]
     
    173105/* FIXME: This should use load and store multiple instructions */
    174106        sub     r13,r13,#SIZE_REGS
    175         str     r0,  [r13, #REG_R0]
    176         str     r1,  [r13, #REG_R1]
    177         str     r2,  [r13, #REG_R2]
    178         str     r3,  [r13, #REG_R3]
    179107        str     r4,  [r13, #REG_R4]
    180108        str     r5,  [r13, #REG_R5]
     
    183111        str     r8,  [r13, #REG_R8]
    184112        str     r9,  [r13, #REG_R9]
    185         str     r10, [r13, #REG_R10]
    186113        str     sp,  [r13, #REG_R11]
    187         str     lr,  [r13, #REG_R12]
    188114        str     lr,  [r13, #REG_SP]
    189115        str     lr,  [r13, #REG_LR]
     
    197123        ldr     pc,[r1]                         /* call handler  */
    198124_go_back_2:
    199         ldr     r0,  [r13, #REG_R0]
    200         ldr     r1,  [r13, #REG_R1]
    201         ldr     r2,  [r13, #REG_R2]
    202         ldr     r3,  [r13, #REG_R3]
    203125        ldr     r4,  [r13, #REG_R4]
    204126        ldr     r5,  [r13, #REG_R5]
     
    209131        ldr     r10, [r13, #REG_R10]
    210132        ldr     sp,  [r13, #REG_R11]
    211         ldr     lr,  [r13, #REG_R12]
    212133        ldr     lr,  [r13, #REG_SP]
    213134        ldr     lr,  [r13, #REG_LR]
     
    215136        subs    pc,r14,#4                       /* return */
    216137       
     138        .globl _exc_data_abort
     139_exc_data_abort:
     140        sub     sp, sp, #SIZE_REGS              /* reserve register frame */
     141        stmia   sp, {r0-r12}
     142        str     lr, [sp, #REG_LR]
     143        mov     r1, lr
     144        ldr     r0, [r1, #-8]                   /* r0 = bad instruction */
     145        mrs     r1, spsr                        /* r1 = spsr */
     146        mov     r2, r13                         /* r2 = exception frame */
     147        bl      do_data_abort
     148       
     149        ldr     lr, [sp, #REG_LR]
     150        ldmia   sp, {r0-r12}
     151        add     sp, sp, #SIZE_REGS
     152
     153        subs    pc, r14, #4                     /* return to the instruction */
     154                                                /* _AFTER_ the aborted one */
  • cpukit/score/cpu/arm/rtems/score/arm.h

    r5ba286f rfa237002  
    3030 *  of the family.
    3131 */
    32 #if defined(__arm9__)
    33 #  define CPU_MODEL_NAME  "arm9"
    34 #  define ARM_HAS_FPU     0
    35 #elif defined(__arm9tdmi__)
    36 #  define CPU_MODEL_NAME  "arm9tdmi"
    37 #  define ARM_HAS_FPU     0
    38 #elif defined(__arm7__)
    39 #  define CPU_MODEL_NAME  "arm7"
    40 #  define ARM_HAS_FPU     0
    41 #elif defined(__arm7tdmi__)
    42 #  define CPU_MODEL_NAME  "arm7tdmi"
    43 #  define ARM_HAS_FPU     0
    44 #elif defined(__arm__)
    45 #  define CPU_MODEL_NAME  "unknown ARM"
    46 #  define ARM_HAS_FPU     0
     32#if defined(__ARM_ARCH_4__)
     33#  define CPU_MODEL_NAME  "ARMv4"
     34#  define ARM_HAS_CLZ     0
     35#  define ARM_HAS_THUMB   0
     36
     37#elif defined(__ARM_ARCH_4T__)
     38#  define CPU_MODEL_NAME  "ARMv4T"
     39#  define ARM_HAS_CLZ     0
     40#  define ARM_HAS_THUMB   1
     41
     42#elif defined(__ARM_ARCH_5__)
     43#  define CPU_MODEL_NAME  "ARMv5"
     44#  define ARM_HAS_CLZ     1
     45#  define ARM_HAS_THUMB   0
     46
     47#elif defined(__ARM_ARCH_5T__)
     48#  define CPU_MODEL_NAME  "ARMv5T"
     49#  define ARM_HAS_CLZ     1
     50#  define ARM_HAS_THUMB   1
     51
     52#elif defined(__ARM_ARCH_5E__)
     53#  define CPU_MODEL_NAME  "ARMv5E"
     54#  define ARM_HAS_CLZ     1
     55#  define ARM_HAS_THUMB   0
     56
     57#elif defined(__ARM_ARCH_5TE__)
     58#  define CPU_MODEL_NAME  "ARMv5TE"
     59#  define ARM_HAS_CLZ     1
     60#  define ARM_HAS_THUMB   1
     61
    4762#else
    4863#  error "Unsupported CPU Model"
     64
    4965#endif
     66
     67/* All ARM CPUs are assumed to not have floating point units */
     68#define ARM_HAS_FPU     0
    5069
    5170/*
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r5ba286f rfa237002  
    11/*
     2 * $RCSfile$
     3 *
    24 *  This include file contains information pertaining to the ARM
    35 *  processor.
    46 *
    5  *  COPYRIGHT (c) 2002 Advent Networks, Inc.
     7 *  Copyright (c) 2002 Advent Networks, Inc.
    68 *        Jay Monkman <jmonkman@adventnetworks.com>
    79 *
     
    1315 *  http://www.OARcorp.com/rtems/license.html.
    1416 *
    15  *  $Id$
    1617 */
    1718
     
    2627#include <rtems/score/arm.h>            /* pick up machine definitions */
    2728#ifndef ASM
    28 #include <rtems/score/types.h>
     29#include <rtems/score/armtypes.h>
    2930#endif
    3031
     
    104105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    105106 *
    106  *  Only one of CPU_HAS_SOFTWARE_INTERRU
     107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    107108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    108109 *  possible that both are FALSE for a particular CPU.  Although it
     
    123124 */
    124125
    125 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
     126#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    126127
    127128/*
     
    142143 *  the answer is TRUE.
    143144 *
    144  *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
     145 *  The macro name "ARM_HAS_FPU" should be made CPU specific.
    145146 *  It indicates whether or not this CPU model has FP support.  For
    146147 *  example, it would be possible to have an i386_nofp CPU model
     
    332333 *  a debugger such as gdb.  But that is another problem.
    333334 */
    334 
    335335typedef struct {
    336     unsigned32 register_r0;
    337     unsigned32 register_r1;
    338     unsigned32 register_r2;
    339     unsigned32 register_r3;
     336    unsigned32 register_cpsr;
    340337    unsigned32 register_r4;
    341338    unsigned32 register_r5;
     
    346343    unsigned32 register_r10;
    347344    unsigned32 register_fp;
    348     unsigned32 register_ip;
    349345    unsigned32 register_sp;
    350346    unsigned32 register_lr;
    351347    unsigned32 register_pc;
    352     unsigned32 register_cpsr;
    353348} Context_Control;
    354349
     
    357352} Context_Control_fp;
    358353
    359 typedef Context_Control CPU_Exception_frame;
     354typedef struct {
     355    unsigned32 register_r0;
     356    unsigned32 register_r1;
     357    unsigned32 register_r2;
     358    unsigned32 register_r3;
     359    unsigned32 register_ip;
     360    unsigned32 register_lr;
     361} CPU_Exception_frame;
    360362
    361363typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
     
    373375/*
    374376 *  The following table contains the information required to configure
    375  *  the ARM processor specific parameters.
     377 *  the XXX processor specific parameters.
    376378 */
    377379
     
    397399
    398400/*
    399  *  Macros to access NO_CPU specific additions to the CPU Table
     401 *  Macros to access ARM specific additions to the CPU Table
     402 *
     403 *  none required
    400404 */
    401405
     
    412416
    413417/*
    414  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    415  *  This stack is allocated by the Interrupt Manager and the switch
    416  *  is performed in _ISR_Handler.  These variables contain pointers
    417  *  to the lowest and highest addresses in the chunk of memory allocated
    418  *  for the interrupt stack.  Since it is unknown whether the stack
    419  *  grows up or down (in general), this give the CPU dependent
    420  *  code the option of picking the version it wants to use.
    421  *
    422  *  NOTE: These two variables are required if the macro
    423  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    424  */
    425 
    426 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    427 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    428 
    429 /*
    430  *  With some compilation systems, it is difficult if not impossible to
    431  *  call a high-level language routine from assembly language.  This
    432  *  is especially true of commercial Ada compilers and name mangling
    433  *  C++ ones.  This variable can be optionally defined by the CPU porter
    434  *  and contains the address of the routine _Thread_Dispatch.  This
    435  *  can make it easier to invoke that routine at the end of the interrupt
    436  *  sequence (if a dispatch is necessary).
    437  */
    438 
    439 SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
    440 
    441 /*
    442  *  Nothing prevents the porter from declaring more CPU specific variables.
    443  */
    444 
    445 /* XXX: if needed, put more variables here */
    446 
    447 /*
    448418 *  The size of the floating point context area.  On some CPUs this
    449419 *  will not be a "sizeof" because the format of the floating point
     
    482452 */
    483453
    484 #define CPU_STACK_MINIMUM_SIZE          (1024*16)
     454#define CPU_STACK_MINIMUM_SIZE          (1024*4)
    485455
    486456/*
     
    536506 */
    537507
    538 #define _CPU_Initialize_vectors()
     508#define _CPU_Initialize_vectors() 
    539509
    540510/*
     
    544514
    545515#define _CPU_ISR_Disable( _level )                \
    546   do {                                            \
    547     int reg;                                      \
    548     asm volatile ("MRS        %0, cpsr \n"        \
    549                   "ORR  %1, %0, #0xc0 \n"         \
    550                   "MSR  cpsr, %1 \n"              \
    551                   "AND  %0, %0, #0xc0 \n"         \
    552                    : "=r" (_level), "=r" (reg)    \
    553                    : "0" (_level), "1" (reg));    \
    554   } while (0)
     516  {                                               \
     517    int reg;                                       \
     518    asm volatile ("MRS  %0, cpsr \n"               \
     519                  "ORR  %1, %0, #0xc0 \n"          \
     520                  "MSR  cpsr, %1 \n"               \
     521                   : "=&r" (_level), "=&r" (reg)); \
     522  }
    555523
    556524/*
     
    561529
    562530#define _CPU_ISR_Enable( _level )               \
    563   do {                                          \
    564     int reg;                                    \
    565     asm volatile ("MRS        %0, cpsr \n"      \
    566                   "BIC  %0, %0, #0xc0 \n"       \
    567                   "ORR  %0, %0, %2 \n"          \
    568                   "MSR  cpsr, %0 \n"            \
    569                   : "=r" (reg)                  \
    570                   : "0" (reg), "r" (_level));   \
    571   } while (0)
     531  {                                             \
     532    asm volatile ("MSR  cpsr, %0 \n"            \
     533                  : : "r" (_level));            \
     534  }
    572535
    573536/*
     
    580543#define _CPU_ISR_Flash( _level ) \
    581544  { \
    582     int reg1;                                   \
    583     int reg2;                                   \
     545    int reg;                                    \
    584546    asm volatile ("MRS  %0, cpsr \n"            \
    585                   "BIC  %1, %0, #0xc0 \n"       \
    586                   "ORR  %1, %1, %4 \n"          \
    587547                  "MSR  cpsr, %1 \n"            \
    588548                  "MSR  cpsr, %0 \n"            \
    589                   : "=r" (reg1), "=r" (reg2)    \
    590                   : "0" (reg1), "1" (reg2),  "r" (_level));       \
     549                  : "=&r" (reg)                 \
     550                  : "r" (_level));              \
    591551  }
    592552
     
    604564 */
    605565
    606 #define _CPU_ISR_Set_level( new_level ) \
    607   { \
     566#define _CPU_ISR_Set_level( new_level )         \
     567  {                                             \
    608568    int reg;                                    \
    609569    asm volatile ("MRS  %0, cpsr \n"            \
    610                   "BIC  %0, %0, #0xc0 \n"            \
     570                  "BIC  %0, %0, #0xc0 \n"       \
    611571                  "ORR  %0, %0, %2 \n"          \
    612                   "MSR  cpsr_c, %0 \n"            \
    613                   : "=r" (reg)                 \
    614                   : "0" (reg), "r" (new_level)); \
     572                  "MSR  cpsr_c, %0 \n"          \
     573                  : "=r" (reg)                  \
     574                  : "r" (reg), "0" (reg));      \
    615575  }
    616576
     
    709669 */
    710670
    711 #define _CPU_Fatal_halt( _error ) \
    712   { \
    713   }
     671#define _CPU_Fatal_halt( _error )           \
     672   do {                                     \
     673     int _level;                            \
     674     _CPU_ISR_Disable( _level );            \
     675     asm volatile ("mov r0, %0\n"           \
     676                   : "=r" (_error)          \
     677                   : "0" (_error)           \
     678                   : "r0" );                \
     679     while(1) ;                             \
     680   } while(0);
     681 
    714682
    715683/* end of Fatal Error manager macros */
     
    771739 *      bit set
    772740 */
    773 
    774 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
    775 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
    776 
    777 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    778 
    779 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    780   { \
    781     (_output) = 0;   /* do something to prevent warnings */ \
    782   }
    783 
    784 #endif
     741#if (ARM_HAS_CLZ == 0)
     742#  define CPU_USE_GENERIC_BITFIELD_CODE TRUE
     743#  define CPU_USE_GENERIC_BITFIELD_DATA TRUE
     744#else
     745#  define CPU_USE_GENERIC_BITFIELD_CODE FALSE
     746#  define CPU_USE_GENERIC_BITFIELD_DATA FALSE
     747
     748#  define _CPU_Bitfield_Find_first_bit( _value, _output ) \
     749   { \
     750     (_output) = 0;   /* do something to prevent warnings */ \
     751   }
    785752
    786753/* end of Bitfield handler macros */
     
    792759 */
    793760
    794 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    795 
    796 #define _CPU_Priority_Mask( _bit_number ) \
    797   ( 1 << (_bit_number) )
    798 
    799 #endif
     761
     762#  define _CPU_Priority_Mask( _bit_number ) \
     763   ( 1 << (_bit_number) )
     764
    800765
    801766/*
     
    806771 */
    807772
    808 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    809 
    810 #define _CPU_Priority_bits_index( _priority ) \
    811   (_priority)
    812 
     773
     774#  define _CPU_Priority_bits_index( _priority ) \
     775   (_priority)
     776
     777#  error "Implement CLZ verson of priority bit functions for ARMv5"
    813778#endif
    814779
     
    864829
    865830/*
    866  *  _CPU_Thread_Idle_body
    867  *
    868  *  This routine is the CPU dependent IDLE thread body.
    869  *
    870  *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
    871  *         is TRUE.
    872  */
    873 
    874 void _CPU_Thread_Idle_body( void );
    875 
    876 /*
    877831 *  _CPU_Context_switch
    878832 *
     
    898852);
    899853
     854#if (ARM_HAS_FPU == 1)
    900855/*
    901856 *  _CPU_Context_save_fp
     
    917872  void **fp_context_ptr
    918873);
     874#endif /* (ARM_HAS_FPU == 1) */
    919875
    920876/*  The following routine swaps the endian format of an unsigned int.
     
    942898)
    943899{
    944   unsigned32 byte1, byte2, byte3, byte4, swapped;
    945  
    946   byte4 = (value >> 24) & 0xff;
    947   byte3 = (value >> 16) & 0xff;
    948   byte2 = (value >> 8)  & 0xff;
    949   byte1 =  value        & 0xff;
    950  
    951   swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    952   return( swapped );
     900    unsigned32 tmp;
     901    asm volatile ("EOR   %1, %0, %0, ROR #16\n"  \
     902                  "BIC   %1, %1, #0xff0000\n"    \
     903                  "MOV   %0, %0, ROR #8\n"       \
     904                  "EOR   %0, %0, %1, LSR #8\n"   \
     905                  : "=&r" (value), "=&r" (tmp)     \
     906                  : "0" (value));
     907
     908    return value;
    953909}
    954910
    955 #define CPU_swap_u16( value ) \
    956   (((value&0xff) << 8) | ((value >> 8)&0xff))
     911static inline unsigned16 CPU_swap_u16(unsigned16 value)
     912{
     913    unsigned32 tmp = value;   /* make compiler warnings go away */
     914    asm volatile ("MOV   %1, %0, LSR #8\n"       \
     915                  "BIC   %0, %0, #0xff00\n"      \
     916                  "MOV   %0, %0, LSL #8\n"       \
     917                  "ORR   %0, %0, %1\n"           \
     918                  : "=&r" (value), "=&r" (tmp)     \
     919                  : "0" (value));
     920    return value;
     921}
    957922
    958923#ifdef __cplusplus
  • cpukit/score/cpu/arm/rtems/score/cpu_asm.h

    r5ba286f rfa237002  
    1919
    2020/* Registers saved in context switch: */
    21 .set REG_R0,      0
    22 .set REG_R1,      4
    23 .set REG_R2,      8
    24 .set REG_R3,     12
    25 .set REG_R4,     16
    26 .set REG_R5,     20
    27 .set REG_R6,     24
    28 .set REG_R7,     28
    29 .set REG_R8,     32
    30 .set REG_R9,     36
    31 .set REG_R10,    40
    32 .set REG_R11,    44
    33 .set REG_R12,    48
    34 .set REG_SP,     52
    35 .set REG_LR,     56
    36 .set REG_PC,     60
    37 .set REG_CPSR,   64
    38 .set SIZE_REGS,  REG_CPSR + 4
    39 
     21.set REG_CPSR,   0
     22.set REG_R4,     4
     23.set REG_R5,     8
     24.set REG_R6,     12
     25.set REG_R7,     16
     26.set REG_R8,     20
     27.set REG_R9,     24
     28.set REG_R10,    28
     29.set REG_R11,    32
     30.set REG_SP,     36
     31.set REG_LR,     40
     32.set REG_PC,     44
     33.set SIZE_REGS,  REG_PC + 4
    4034
    4135#endif
  • cpukit/score/cpu/arm/rtems/score/types.h

    r5ba286f rfa237002  
    2626 */
    2727
    28 typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
    29 typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
    30 typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
    31 typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
     28typedef unsigned char      unsigned8;          /* unsigned 8-bit  integer */
     29typedef unsigned short     unsigned16;         /* unsigned 16-bit integer */
     30typedef unsigned int       unsigned32;         /* unsigned 32-bit integer */
     31typedef unsigned long long unsigned64;         /* unsigned 64-bit integer */
    3232
    33 typedef unsigned16     Priority_Bit_map_control;
     33typedef signed char        signed8;            /* 8-bit  signed integer */
     34typedef signed short       signed16;           /* 16-bit signed integer */
     35typedef signed int         signed32;           /* 32-bit signed integer */
     36typedef signed long long   signed64;           /* 64 bit signed integer */
    3437
    35 typedef signed char      signed8;      /* 8-bit  signed integer */
    36 typedef signed short     signed16;     /* 16-bit signed integer */
    37 typedef signed int       signed32;     /* 32-bit signed integer */
    38 typedef signed long long signed64;     /* 64 bit signed integer */
     38typedef unsigned32         boolean;            /* Boolean value   */
     39typedef unsigned16         Priority_Bit_map_control;
    3940
    40 typedef unsigned32 boolean;     /* Boolean value   */
     41typedef float              single_precision;   /* single precision float */
     42typedef double             double_precision;   /* double precision float */
    4143
    42 typedef float          single_precision;     /* single precision float */
    43 typedef double         double_precision;     /* double precision float */
    44 
    45 typedef void no_cpu_isr;
    46 typedef void ( *no_cpu_isr_entry )( void );
     44typedef void               arm_cpu_isr;
     45typedef void            ( *arm_cpu_isr_entry )( void );
    4746
    4847#ifdef __cplusplus
Note: See TracChangeset for help on using the changeset viewer.