Index: c/src/lib/libcpu/powerpc/ChangeLog
===================================================================
--- c/src/lib/libcpu/powerpc/ChangeLog	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ChangeLog	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -1,2 +1,16 @@
+2011-02-11	Ralf CorsÃ©pius <ralf.corsepius@rtems.org>
+
+	* e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
+	mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
+	mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
+	mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
+	mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
+	new-exceptions/bspsupport/ppc_exc_initialize.c,
+	ppc403/clock/clock.c, ppc403/console/console.c,
+	ppc403/console/console.c.polled, ppc403/console/console405.c,
+	ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
+	rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
+	Use "__asm__" instead of "asm" for improved c99-compliance.
+
 2011-02-02	Ralf CorsÃ©pius <ralf.corsepius@rtems.org>
 
Index: c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
===================================================================
--- c/src/lib/libcpu/powerpc/e500/mmu/mmu.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/e500/mmu/mmu.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -100,7 +100,7 @@
 #define __RDWRMAS(mas,rmas)	\
 	static inline uint32_t _read_MAS##mas(void)	                                 \
-	{ uint32_t x; asm volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
+	{ uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
 	static inline void _write_MAS##mas(uint32_t x)                             \
-	{             asm volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
+	{             __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
 
 __RDWRMAS(0,FSL_EIS_MAS0)
Index: c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -37,5 +37,5 @@
 {
 #define BIT_NUMBER(val, bit) \
-    asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
 
   int bit;
Index: c/src/lib/libcpu/powerpc/mpc505/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc505/timer/timer.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc505/timer/timer.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -23,5 +23,5 @@
 void benchmark_timer_initialize( void )
 {
-  asm volatile( " mftb %0": "=r" (lastInitValue) );
+  __asm__ volatile( " mftb %0": "=r" (lastInitValue) );
 }
 
@@ -44,5 +44,5 @@
 {
   uint32_t   value;
-  asm volatile ( " mftb %0": "=r" (value) );
+  __asm__ volatile ( " mftb %0": "=r" (value) );
   return value - lastInitValue;
 }
Index: c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -37,5 +37,5 @@
 {
 #define BIT_NUMBER(val, bit) \
-    asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
 
   int bit;
Index: c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -65,5 +65,5 @@
    uint32_t ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
Index: c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -142,6 +142,6 @@
 
 static void dummy(void) __attribute__((noinline));
-/* add (empty) asm statement to make sure this isn't optimized away */
-static void dummy(void) { asm volatile(""); }
+/* add (empty) __asm__ statement to make sure this isn't optimized away */
+static void dummy(void) { __asm__ volatile(""); }
 
 static unsigned probe_r1(void) __attribute__((noinline));
Index: c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -134,5 +134,5 @@
   register uint32_t flags;
   rtems_interrupt_disable(flags);
-  asm volatile (
+  __asm__ volatile (
     "mfdec %0; add %0, %0, %1; mtdec %0"
     : "=&r"(decr)
Index: c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -125,5 +125,5 @@
 set_hid0_sync (unsigned long val)
 {
-  asm volatile (
+  __asm__ volatile (
     "	sync			\n"
     "	isync			\n"
@@ -222,5 +222,5 @@
      */
 #define DSSALL	0x7e00066c      /* dssall opcode */
-    asm volatile ("	.long %0"::"i" (DSSALL));
+    __asm__ volatile ("	.long %0"::"i" (DSSALL));
 #undef  DSSALL
   }
@@ -288,5 +288,5 @@
     bit = 32;
   } else {
-    asm volatile ("	cntlzw %0, %1":"=r" (bit):"r" (size));
+    __asm__ volatile ("	cntlzw %0, %1":"=r" (bit):"r" (size));
     bit = 31 - bit;
     if (1 << bit != size)
Index: c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -66,5 +66,5 @@
 extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
 
-/* Do not use the asm routines; they are obsolete; use setdbat() instead */
+/* Do not use the __asm__ routines; they are obsolete; use setdbat() instead */
 extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
 extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
Index: c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -158,5 +158,5 @@
 seg2vsid (uint32_t ea)
 {
-  asm volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
+  __asm__ volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
   return ea & ((1 << LD_VSID_SIZE) - 1);
 }
@@ -540,7 +540,7 @@
               rtems_interrupt_disable (flags);
               /* order setting 'v' after writing everything else */
-              asm volatile ("eieio":::"memory");
+              __asm__ volatile ("eieio":::"memory");
               pte->v = 1;
-              asm volatile ("sync":::"memory");
+              __asm__ volatile ("sync":::"memory");
               rtems_interrupt_enable (flags);
             } else {
@@ -870,5 +870,5 @@
   pte->v = 0;
   do_dssall ();
-  asm volatile ("	sync		\n\t"
+  __asm__ volatile ("	sync		\n\t"
                 "	tlbie %0	\n\t"
                 "	eieio		\n\t"
@@ -917,5 +917,5 @@
      */
 #define DSSALL	0x7e00066c      /* dssall opcode */
-    asm volatile ("	.long %0"::"i" (DSSALL));
+    __asm__ volatile ("	.long %0"::"i" (DSSALL));
 #undef  DSSALL
   }
@@ -947,5 +947,5 @@
     return pte;
 
-  asm volatile ("mfmsr %0":"=r" (msr));
+  __asm__ volatile ("mfmsr %0":"=r" (msr));
 
   /* switch MMU and IRQs off */
@@ -954,12 +954,12 @@
   pte->v = 0;
   do_dssall ();
-  asm volatile ("sync":::"memory");
+  __asm__ volatile ("sync":::"memory");
   if (wimg >= 0)
     pte->wimg = wimg;
   if (pp >= 0)
     pte->pp = pp;
-  asm volatile ("tlbie %0; eieio"::"r" (ea):"memory");
+  __asm__ volatile ("tlbie %0; eieio"::"r" (ea):"memory");
   pte->v = 1;
-  asm volatile ("tlbsync; sync":::"memory");
+  __asm__ volatile ("tlbsync; sync":::"memory");
 
   /* restore, i.e., switch MMU and IRQs back on */
Index: c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -61,5 +61,5 @@
    uint32_t   ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
Index: c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -58,5 +58,5 @@
    uint32_t   ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
Index: c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
===================================================================
--- c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -31,6 +31,6 @@
 uint32_t ppc_exc_cache_wb_check = 1;
 
-#define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
-#define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
+#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
+#define MTIVOR(x, vec) __asm__ volatile ("mtivor"#x" %0" : : "r" (vec))
 
 static void ppc_exc_initialize_booke(void)
@@ -95,5 +95,5 @@
    * early init code put it there.
    */
-  asm volatile (
+  __asm__ volatile (
     "lis %0, _SDA_BASE_@h\n"
     "ori %0, %0, _SDA_BASE_@l\n"
@@ -175,5 +175,5 @@
      */
     p = (p + 31U) & ~31U;
-    asm volatile ("dcbz 0, %0"::"b" (p));
+    __asm__ volatile ("dcbz 0, %0"::"b" (p));
     /* If we make it thru here then things seem to be OK */
   }
Index: c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
===================================================================
--- c/src/lib/libcpu/powerpc/new-exceptions/cpu.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/new-exceptions/cpu.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -133,5 +133,5 @@
   { uint32_t    r2 = 0;
     unsigned    r13 = 0;
-    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
 
     the_context->gpr2 = r2;
@@ -141,5 +141,5 @@
   { uint32_t    r2 = 0;
     unsigned    r13 = 0;
-    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
 
     the_context->gpr2 = r2;
Index: c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/clock/clock.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/clock/clock.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -74,7 +74,7 @@
 
 #ifndef ppc405 /* this is a ppc403 */
-    asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
+    __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
 #else /* ppc405 */
-    asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
+    __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
 #endif /* ppc405 */
 
@@ -136,9 +136,9 @@
       }
 
-      asm volatile ("mtspr 0x3db, %0" :: "r"
+      __asm__ volatile ("mtspr 0x3db, %0" :: "r"
                          (clicks_til_next_interrupt)); /* PIT */
   }
 
-    asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
+    __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
 
     Clock_driver_ticks++;
@@ -161,5 +161,5 @@
     register uint32_t   tcr;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
 
     return (tcr & 0x04000000) != 0;
@@ -172,9 +172,9 @@
     register uint32_t   tcr;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
 
     tcr &= ~ 0x04400000;
 
-    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
 }
 
@@ -192,5 +192,5 @@
 
 #ifndef ppc405 /* this is a ppc403 */
-    asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
+    __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
     if (bsp_timer_internal_clock) {
 	iocr &= ~4; /* timer clocked from system clock */
@@ -199,7 +199,7 @@
 	iocr |= 4; /* select external timer clock */
     }
-    asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
-
-    asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
+    __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
+
+    __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
     if (((pvr & 0xffff0000) >> 16) != 0x0020)
       return; /* Not a ppc403 */
@@ -216,5 +216,5 @@
 
 #else /* ppc405 */
-    asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
+    __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
     if (bsp_timer_internal_clock) {
 	iocr &=~0x800000	;/* timer clocked from system clock CETE*/
@@ -223,5 +223,5 @@
 	iocr |= 0x800000; /* select external timer clock CETE*/
     }
-    asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
+    __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
 
      /*
@@ -239,5 +239,5 @@
       */
 
-    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
+    __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
 
      /*
@@ -247,8 +247,8 @@
     tick_time = get_itimer() + pit_value;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
 #if 1
-    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
 #endif
 
Index: c/src/lib/libcpu/powerpc/ppc403/console/console.c
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/console/console.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/console/console.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -352,10 +352,10 @@
    * select clock source
    */
-  asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
 
   tmp &= ~3;
   tmp |= (bsp_serial_external_clock ? 2 : 0) | 1;
 
-  asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
 
   /* clear any receive (error) status */
Index: c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -147,9 +147,9 @@
 
   /* Initialise the serial port */
-  asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
   tmp &= ~3;
   tmp |= (bsp_serial_external_clock ? 2 : 0) |
       (bsp_serial_cts_rts ? 1 : 0);
-  asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
   port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
          LSRParityError | LSRBreakInterrupt);
Index: c/src/lib/libcpu/powerpc/ppc403/console/console405.c
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/console/console405.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/console/console405.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -368,5 +368,5 @@
    */
 
-  asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
 
   /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
@@ -375,5 +375,5 @@
   tmp |= (bsp_serial_external_clock ?  0: ((UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
 
-  asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
 
   /* Disable port interrupts while changing hardware */
Index: c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -48,5 +48,5 @@
 clr_exisr(uint32_t   mask)
 {
-    asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
+    __asm__ volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
 }
 
@@ -59,5 +59,5 @@
     uint32_t   val;
 
-    asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
+    __asm__ volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
     return val;
 }
@@ -70,5 +70,5 @@
 {
     uint32_t   val;
-    asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
+    __asm__ volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
     return val;
 }
@@ -80,5 +80,5 @@
 set_exier(uint32_t   val)
 {
-    asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
+    __asm__ volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
 }
 
@@ -88,5 +88,5 @@
 clr_exisr(uint32_t   mask)
 {
-    asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
+    __asm__ volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
 }
 
@@ -99,5 +99,5 @@
     uint32_t   val;
 
-    asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
+    __asm__ volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
     return val;
 }
@@ -110,5 +110,5 @@
 {
     uint32_t   val;
-    asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
+    __asm__ volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
     return val;
 }
@@ -120,5 +120,5 @@
 set_exier(uint32_t   val)
 {
-    asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
+    __asm__ volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
 }
 #endif /* ppc405 */
Index: c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c
===================================================================
--- c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -360,5 +360,5 @@
    */
 
-  asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
 
   /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
@@ -367,5 +367,5 @@
   tmp |= (bsp_serial_external_clock ?  0: ((TTY0_UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
 
-  asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
 
   /* Disable tty0port interrupts while changing hardware */
Index: c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h
===================================================================
--- c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -14,5 +14,5 @@
   do { register void *__address = (_address); \
        register uint32_t   _zero = 0; \
-       asm volatile ( "dcbf %0,%1" : \
+       __asm__ volatile ( "dcbf %0,%1" : \
 		      "=r" (_zero), "=r" (__address) : \
                       "0" (_zero), "1" (__address) \
@@ -30,5 +30,5 @@
   do { register void *__address = (_address); \
        register uint32_t   _zero = 0; \
-       asm volatile ( "dcbi %0,%1" : \
+       __asm__ volatile ( "dcbi %0,%1" : \
 		      "=r" (_zero), "=r" (__address) : \
                       "0" (_zero), "1" (__address) \
Index: c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
===================================================================
--- c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -58,5 +58,5 @@
   uint8_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lbz %0, 0(%1)"
     : "=r" (value)
@@ -74,5 +74,5 @@
   uint16_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lhz %0, 0(%1)"
     : "=r" (value)
@@ -90,5 +90,5 @@
   uint32_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lwz %0, 0(%1)"
     : "=r" (value)
@@ -104,5 +104,5 @@
 static inline void ppc_write_byte(uint8_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "stb %0, 0(%1)"
     :
@@ -116,5 +116,5 @@
 static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "sth %0, 0(%1)"
     :
@@ -128,5 +128,5 @@
 static inline void ppc_write_word(uint32_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "stw %0, 0(%1)" :
     : "r" (value), "b" (dest)
@@ -139,5 +139,5 @@
   void *sp;
 
-  asm volatile (
+  __asm__ volatile (
     "mr %0, 1"
     : "=r" (sp)
@@ -149,5 +149,5 @@
 static inline void ppc_set_stack_pointer(void *sp)
 {
-  asm volatile (
+  __asm__ volatile (
     "mr 1, %0"
     :
@@ -160,5 +160,5 @@
   void *lr;
 
-  asm volatile (
+  __asm__ volatile (
     "mflr %0"
     : "=r" (lr)
@@ -170,5 +170,5 @@
 static inline void ppc_set_link_register(void *lr)
 {
-  asm volatile (
+  __asm__ volatile (
     "mtlr %0"
     :
@@ -181,5 +181,5 @@
   uint32_t msr;
 
-  asm volatile (
+  __asm__ volatile (
     "mfmsr %0"
     : "=r" (msr)
@@ -191,5 +191,5 @@
 static inline void ppc_set_machine_state_register(uint32_t msr)
 {
-  asm volatile (
+  __asm__ volatile (
     "mtmsr %0"
     :
@@ -202,5 +202,5 @@
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile ("sync");
+  __asm__ volatile ("sync");
 }
 
@@ -209,5 +209,5 @@
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile ("isync");
+  __asm__ volatile ("isync");
 }
 
@@ -225,5 +225,5 @@
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile (
+  __asm__ volatile (
     "mfmsr %0;"
     "ori %1, %0, 0x8000;"
@@ -267,8 +267,8 @@
  */
 #define CPU_Get_timebase_low( _value ) \
-    asm volatile( "mftb  %0" : "=r" (_value) )
+    __asm__ volatile( "mftb  %0" : "=r" (_value) )
 #else
 #define CPU_Get_timebase_low( _value ) \
-    asm volatile( "mfspr %0,268" : "=r" (_value) )
+    __asm__ volatile( "mfspr %0,268" : "=r" (_value) )
 #endif
 
@@ -301,9 +301,9 @@
 #define PPC_Set_decrementer( _clicks ) \
   do { \
-    asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
+    __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \
   } while (0)
 
 #define PPC_Get_decrementer( _clicks ) \
-    asm volatile( "mfdec  %0" : "=r" (_clicks) )
+    __asm__ volatile( "mfdec  %0" : "=r" (_clicks) )
 
 /*
@@ -321,11 +321,11 @@
 #if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
 /* See comment above (CPU_Get_timebase_low) */
-    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
-    asm volatile( "mftb  %0" : "=r" (tbr_low));
-    asm volatile( "mftbu %0" : "=r" (tbr_high));
+    __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old));
+    __asm__ volatile( "mftb  %0" : "=r" (tbr_low));
+    __asm__ volatile( "mftbu %0" : "=r" (tbr_high));
 #else
-    asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
-    asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
-    asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
+    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
+    __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low));
+    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high));
 #endif
   } while ( tbr_high_old != tbr_high );
@@ -344,6 +344,6 @@
   tbr_low = (uint32_t) tbr;
   tbr_high = (uint32_t) (tbr >> 32);
-  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
-  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
+  __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low));
+  __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high));
 
 }
@@ -376,5 +376,5 @@
   ({ \
     uint32_t val; \
-    asm volatile (\
+    __asm__ volatile (\
       "mfspr %0, " PPC_STRINGOF(spr) \
       : "=r" (val) \
@@ -389,5 +389,5 @@
 #define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
   do { \
-    asm volatile (\
+    __asm__ volatile (\
       "mtspr " PPC_STRINGOF(spr) ", %0" \
       : \
@@ -463,5 +463,5 @@
   ({ \
     uint32_t val; \
-    asm volatile (\
+    __asm__ volatile (\
       "mfdcr %0, " PPC_STRINGOF(dcr) \
       : "=r" (val) \
@@ -478,5 +478,5 @@
 #define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
   do { \
-    asm volatile (\
+    __asm__ volatile (\
       "mtdcr " PPC_STRINGOF(dcr) ", %0" \
       : \
Index: c/src/lib/libcpu/powerpc/shared/src/cache.c
===================================================================
--- c/src/lib/libcpu/powerpc/shared/src/cache.c	(revision b15e7dc33232a0285b8dac3272dbbfa13400bd7c)
+++ c/src/lib/libcpu/powerpc/shared/src/cache.c	(revision f9acc339fe66dce682d124d98956dd65af467676)
@@ -34,5 +34,5 @@
   do { \
       _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
+      __asm__ volatile( \
           "mfspr %0, 0x3f0;"     /* get HID0 */ \
           "isync" \
@@ -44,5 +44,5 @@
 #define PPC_Set_HID0( _value ) \
   do { \
-      asm volatile( \
+      __asm__ volatile( \
           "isync;" \
           "mtspr 0x3f0, %0;"     /* load HID0 */ \
@@ -270,5 +270,5 @@
 {
   register const void *__address = _address;
-  asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
+  __asm__ volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
 }
 
@@ -277,5 +277,5 @@
 {
   register const void *__address = _address;
-  asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
+  __asm__ volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
 }
 
@@ -285,5 +285,5 @@
 {
   register const void *__address = _address;
-  asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
+  __asm__ volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
 }
 
