Changeset f9acc33 in rtems


Ignore:
Timestamp:
Feb 11, 2011, 9:46:53 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.11, master
Children:
1531033d
Parents:
b15e7dc
Message:

2011-02-11 Ralf Corsépius <ralf.corsepius@…>

  • e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c, mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c, mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c, mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c, new-exceptions/bspsupport/ppc_exc_initialize.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console.c.polled, ppc403/console/console405.c, ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c: Use "asm" instead of "asm" for improved c99-compliance.
Location:
c/src/lib/libcpu/powerpc
Files:
24 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    rb15e7dc rf9acc33  
     12011-02-11      Ralf Corsépius <ralf.corsepius@rtems.org>
     2
     3        * e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
     4        mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
     5        mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
     6        mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
     7        mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
     8        new-exceptions/bspsupport/ppc_exc_initialize.c,
     9        ppc403/clock/clock.c, ppc403/console/console.c,
     10        ppc403/console/console.c.polled, ppc403/console/console405.c,
     11        ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
     12        rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
     13        Use "__asm__" instead of "asm" for improved c99-compliance.
     14
    1152011-02-02      Ralf Corsépius <ralf.corsepius@rtems.org>
    216
  • c/src/lib/libcpu/powerpc/e500/mmu/mmu.c

    rb15e7dc rf9acc33  
    100100#define __RDWRMAS(mas,rmas)     \
    101101        static inline uint32_t _read_MAS##mas(void)                                      \
    102         { uint32_t x; asm volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
     102        { uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
    103103        static inline void _write_MAS##mas(uint32_t x)                             \
    104         {             asm volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
     104        {             __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
    105105
    106106__RDWRMAS(0,FSL_EIS_MAS0)
  • c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c

    rb15e7dc rf9acc33  
    3737{
    3838#define BIT_NUMBER(val, bit) \
    39     asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
     39    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
    4040
    4141  int bit;
  • c/src/lib/libcpu/powerpc/mpc505/timer/timer.c

    rb15e7dc rf9acc33  
    2323void benchmark_timer_initialize( void )
    2424{
    25   asm volatile( " mftb %0": "=r" (lastInitValue) );
     25  __asm__ volatile( " mftb %0": "=r" (lastInitValue) );
    2626}
    2727
     
    4444{
    4545  uint32_t   value;
    46   asm volatile ( " mftb %0": "=r" (value) );
     46  __asm__ volatile ( " mftb %0": "=r" (value) );
    4747  return value - lastInitValue;
    4848}
  • c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c

    rb15e7dc rf9acc33  
    3737{
    3838#define BIT_NUMBER(val, bit) \
    39     asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
     39    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
    4040
    4141  int bit;
  • c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c

    rb15e7dc rf9acc33  
    6565   uint32_t ret;
    6666
    67    asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
     67   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
    6868
    6969   return ret;
  • c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c

    rb15e7dc rf9acc33  
    142142
    143143static void dummy(void) __attribute__((noinline));
    144 /* add (empty) asm statement to make sure this isn't optimized away */
    145 static void dummy(void) { asm volatile(""); }
     144/* add (empty) __asm__ statement to make sure this isn't optimized away */
     145static void dummy(void) { __asm__ volatile(""); }
    146146
    147147static unsigned probe_r1(void) __attribute__((noinline));
  • c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c

    rb15e7dc rf9acc33  
    134134  register uint32_t flags;
    135135  rtems_interrupt_disable(flags);
    136   asm volatile (
     136  __asm__ volatile (
    137137    "mfdec %0; add %0, %0, %1; mtdec %0"
    138138    : "=&r"(decr)
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c

    rb15e7dc rf9acc33  
    125125set_hid0_sync (unsigned long val)
    126126{
    127   asm volatile (
     127  __asm__ volatile (
    128128    "   sync                    \n"
    129129    "   isync                   \n"
     
    222222     */
    223223#define DSSALL  0x7e00066c      /* dssall opcode */
    224     asm volatile ("     .long %0"::"i" (DSSALL));
     224    __asm__ volatile (" .long %0"::"i" (DSSALL));
    225225#undef  DSSALL
    226226  }
     
    288288    bit = 32;
    289289  } else {
    290     asm volatile ("     cntlzw %0, %1":"=r" (bit):"r" (size));
     290    __asm__ volatile (" cntlzw %0, %1":"=r" (bit):"r" (size));
    291291    bit = 31 - bit;
    292292    if (1 << bit != size)
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h

    rb15e7dc rf9acc33  
    6666extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
    6767
    68 /* Do not use the asm routines; they are obsolete; use setdbat() instead */
     68/* Do not use the __asm__ routines; they are obsolete; use setdbat() instead */
    6969extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
    7070extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c

    rb15e7dc rf9acc33  
    158158seg2vsid (uint32_t ea)
    159159{
    160   asm volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
     160  __asm__ volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
    161161  return ea & ((1 << LD_VSID_SIZE) - 1);
    162162}
     
    540540              rtems_interrupt_disable (flags);
    541541              /* order setting 'v' after writing everything else */
    542               asm volatile ("eieio":::"memory");
     542              __asm__ volatile ("eieio":::"memory");
    543543              pte->v = 1;
    544               asm volatile ("sync":::"memory");
     544              __asm__ volatile ("sync":::"memory");
    545545              rtems_interrupt_enable (flags);
    546546            } else {
     
    870870  pte->v = 0;
    871871  do_dssall ();
    872   asm volatile ("       sync            \n\t"
     872  __asm__ volatile ("   sync            \n\t"
    873873                "       tlbie %0        \n\t"
    874874                "       eieio           \n\t"
     
    917917     */
    918918#define DSSALL  0x7e00066c      /* dssall opcode */
    919     asm volatile ("     .long %0"::"i" (DSSALL));
     919    __asm__ volatile (" .long %0"::"i" (DSSALL));
    920920#undef  DSSALL
    921921  }
     
    947947    return pte;
    948948
    949   asm volatile ("mfmsr %0":"=r" (msr));
     949  __asm__ volatile ("mfmsr %0":"=r" (msr));
    950950
    951951  /* switch MMU and IRQs off */
     
    954954  pte->v = 0;
    955955  do_dssall ();
    956   asm volatile ("sync":::"memory");
     956  __asm__ volatile ("sync":::"memory");
    957957  if (wimg >= 0)
    958958    pte->wimg = wimg;
    959959  if (pp >= 0)
    960960    pte->pp = pp;
    961   asm volatile ("tlbie %0; eieio"::"r" (ea):"memory");
     961  __asm__ volatile ("tlbie %0; eieio"::"r" (ea):"memory");
    962962  pte->v = 1;
    963   asm volatile ("tlbsync; sync":::"memory");
     963  __asm__ volatile ("tlbsync; sync":::"memory");
    964964
    965965  /* restore, i.e., switch MMU and IRQs back on */
  • c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c

    rb15e7dc rf9acc33  
    6161   uint32_t   ret;
    6262
    63    asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
     63   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
    6464
    6565   return ret;
  • c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c

    rb15e7dc rf9acc33  
    5858   uint32_t   ret;
    5959
    60    asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
     60   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
    6161
    6262   return ret;
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c

    rb15e7dc rf9acc33  
    3131uint32_t ppc_exc_cache_wb_check = 1;
    3232
    33 #define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
    34 #define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
     33#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
     34#define MTIVOR(x, vec) __asm__ volatile ("mtivor"#x" %0" : : "r" (vec))
    3535
    3636static void ppc_exc_initialize_booke(void)
     
    9595   * early init code put it there.
    9696   */
    97   asm volatile (
     97  __asm__ volatile (
    9898    "lis %0, _SDA_BASE_@h\n"
    9999    "ori %0, %0, _SDA_BASE_@l\n"
     
    175175     */
    176176    p = (p + 31U) & ~31U;
    177     asm volatile ("dcbz 0, %0"::"b" (p));
     177    __asm__ volatile ("dcbz 0, %0"::"b" (p));
    178178    /* If we make it thru here then things seem to be OK */
    179179  }
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu.c

    rb15e7dc rf9acc33  
    133133  { uint32_t    r2 = 0;
    134134    unsigned    r13 = 0;
    135     asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
     135    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
    136136
    137137    the_context->gpr2 = r2;
     
    141141  { uint32_t    r2 = 0;
    142142    unsigned    r13 = 0;
    143     asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
     143    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
    144144
    145145    the_context->gpr2 = r2;
  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    rb15e7dc rf9acc33  
    7474
    7575#ifndef ppc405 /* this is a ppc403 */
    76     asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
     76    __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
    7777#else /* ppc405 */
    78     asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
     78    __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
    7979#endif /* ppc405 */
    8080
     
    136136      }
    137137
    138       asm volatile ("mtspr 0x3db, %0" :: "r"
     138      __asm__ volatile ("mtspr 0x3db, %0" :: "r"
    139139                         (clicks_til_next_interrupt)); /* PIT */
    140140  }
    141141
    142     asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
     142    __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
    143143
    144144    Clock_driver_ticks++;
     
    161161    register uint32_t   tcr;
    162162
    163     asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     163    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    164164
    165165    return (tcr & 0x04000000) != 0;
     
    172172    register uint32_t   tcr;
    173173
    174     asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     174    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    175175
    176176    tcr &= ~ 0x04400000;
    177177
    178     asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     178    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    179179}
    180180
     
    192192
    193193#ifndef ppc405 /* this is a ppc403 */
    194     asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
     194    __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
    195195    if (bsp_timer_internal_clock) {
    196196        iocr &= ~4; /* timer clocked from system clock */
     
    199199        iocr |= 4; /* select external timer clock */
    200200    }
    201     asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
    202 
    203     asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
     201    __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
     202
     203    __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
    204204    if (((pvr & 0xffff0000) >> 16) != 0x0020)
    205205      return; /* Not a ppc403 */
     
    216216
    217217#else /* ppc405 */
    218     asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
     218    __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
    219219    if (bsp_timer_internal_clock) {
    220220        iocr &=~0x800000        ;/* timer clocked from system clock CETE*/
     
    223223        iocr |= 0x800000; /* select external timer clock CETE*/
    224224    }
    225     asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
     225    __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
    226226
    227227     /*
     
    239239      */
    240240
    241     asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
     241    __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
    242242
    243243     /*
     
    247247    tick_time = get_itimer() + pit_value;
    248248
    249     asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     249    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    250250    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
    251251#if 1
    252     asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     252    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    253253#endif
    254254
  • c/src/lib/libcpu/powerpc/ppc403/console/console.c

    rb15e7dc rf9acc33  
    352352   * select clock source
    353353   */
    354   asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
     354  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
    355355
    356356  tmp &= ~3;
    357357  tmp |= (bsp_serial_external_clock ? 2 : 0) | 1;
    358358
    359   asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
     359  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
    360360
    361361  /* clear any receive (error) status */
  • c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled

    rb15e7dc rf9acc33  
    147147
    148148  /* Initialise the serial port */
    149   asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
     149  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
    150150  tmp &= ~3;
    151151  tmp |= (bsp_serial_external_clock ? 2 : 0) |
    152152      (bsp_serial_cts_rts ? 1 : 0);
    153   asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
     153  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
    154154  port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
    155155         LSRParityError | LSRBreakInterrupt);
  • c/src/lib/libcpu/powerpc/ppc403/console/console405.c

    rb15e7dc rf9acc33  
    368368   */
    369369
    370   asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
     370  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
    371371
    372372  /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
     
    375375  tmp |= (bsp_serial_external_clock ?  0: ((UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
    376376
    377   asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
     377  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
    378378
    379379  /* Disable port interrupts while changing hardware */
  • c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c

    rb15e7dc rf9acc33  
    4848clr_exisr(uint32_t   mask)
    4949{
    50     asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
     50    __asm__ volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
    5151}
    5252
     
    5959    uint32_t   val;
    6060
    61     asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
     61    __asm__ volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
    6262    return val;
    6363}
     
    7070{
    7171    uint32_t   val;
    72     asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
     72    __asm__ volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
    7373    return val;
    7474}
     
    8080set_exier(uint32_t   val)
    8181{
    82     asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
     82    __asm__ volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
    8383}
    8484
     
    8888clr_exisr(uint32_t   mask)
    8989{
    90     asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
     90    __asm__ volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
    9191}
    9292
     
    9999    uint32_t   val;
    100100
    101     asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
     101    __asm__ volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
    102102    return val;
    103103}
     
    110110{
    111111    uint32_t   val;
    112     asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
     112    __asm__ volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
    113113    return val;
    114114}
     
    120120set_exier(uint32_t   val)
    121121{
    122     asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
     122    __asm__ volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
    123123}
    124124#endif /* ppc405 */
  • c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c

    rb15e7dc rf9acc33  
    360360   */
    361361
    362   asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
     362  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
    363363
    364364  /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
     
    367367  tmp |= (bsp_serial_external_clock ?  0: ((TTY0_UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
    368368
    369   asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
     369  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
    370370
    371371  /* Disable tty0port interrupts while changing hardware */
  • c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h

    rb15e7dc rf9acc33  
    1414  do { register void *__address = (_address); \
    1515       register uint32_t   _zero = 0; \
    16        asm volatile ( "dcbf %0,%1" : \
     16       __asm__ volatile ( "dcbf %0,%1" : \
    1717                      "=r" (_zero), "=r" (__address) : \
    1818                      "0" (_zero), "1" (__address) \
     
    3030  do { register void *__address = (_address); \
    3131       register uint32_t   _zero = 0; \
    32        asm volatile ( "dcbi %0,%1" : \
     32       __asm__ volatile ( "dcbi %0,%1" : \
    3333                      "=r" (_zero), "=r" (__address) : \
    3434                      "0" (_zero), "1" (__address) \
  • c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

    rb15e7dc rf9acc33  
    5858  uint8_t value;
    5959
    60   asm volatile (
     60  __asm__ volatile (
    6161    "lbz %0, 0(%1)"
    6262    : "=r" (value)
     
    7474  uint16_t value;
    7575
    76   asm volatile (
     76  __asm__ volatile (
    7777    "lhz %0, 0(%1)"
    7878    : "=r" (value)
     
    9090  uint32_t value;
    9191
    92   asm volatile (
     92  __asm__ volatile (
    9393    "lwz %0, 0(%1)"
    9494    : "=r" (value)
     
    104104static inline void ppc_write_byte(uint8_t value, volatile void *dest)
    105105{
    106   asm volatile (
     106  __asm__ volatile (
    107107    "stb %0, 0(%1)"
    108108    :
     
    116116static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
    117117{
    118   asm volatile (
     118  __asm__ volatile (
    119119    "sth %0, 0(%1)"
    120120    :
     
    128128static inline void ppc_write_word(uint32_t value, volatile void *dest)
    129129{
    130   asm volatile (
     130  __asm__ volatile (
    131131    "stw %0, 0(%1)" :
    132132    : "r" (value), "b" (dest)
     
    139139  void *sp;
    140140
    141   asm volatile (
     141  __asm__ volatile (
    142142    "mr %0, 1"
    143143    : "=r" (sp)
     
    149149static inline void ppc_set_stack_pointer(void *sp)
    150150{
    151   asm volatile (
     151  __asm__ volatile (
    152152    "mr 1, %0"
    153153    :
     
    160160  void *lr;
    161161
    162   asm volatile (
     162  __asm__ volatile (
    163163    "mflr %0"
    164164    : "=r" (lr)
     
    170170static inline void ppc_set_link_register(void *lr)
    171171{
    172   asm volatile (
     172  __asm__ volatile (
    173173    "mtlr %0"
    174174    :
     
    181181  uint32_t msr;
    182182
    183   asm volatile (
     183  __asm__ volatile (
    184184    "mfmsr %0"
    185185    : "=r" (msr)
     
    191191static inline void ppc_set_machine_state_register(uint32_t msr)
    192192{
    193   asm volatile (
     193  __asm__ volatile (
    194194    "mtmsr %0"
    195195    :
     
    202202  RTEMS_COMPILER_MEMORY_BARRIER();
    203203
    204   asm volatile ("sync");
     204  __asm__ volatile ("sync");
    205205}
    206206
     
    209209  RTEMS_COMPILER_MEMORY_BARRIER();
    210210
    211   asm volatile ("isync");
     211  __asm__ volatile ("isync");
    212212}
    213213
     
    225225  RTEMS_COMPILER_MEMORY_BARRIER();
    226226
    227   asm volatile (
     227  __asm__ volatile (
    228228    "mfmsr %0;"
    229229    "ori %1, %0, 0x8000;"
     
    267267 */
    268268#define CPU_Get_timebase_low( _value ) \
    269     asm volatile( "mftb  %0" : "=r" (_value) )
     269    __asm__ volatile( "mftb  %0" : "=r" (_value) )
    270270#else
    271271#define CPU_Get_timebase_low( _value ) \
    272     asm volatile( "mfspr %0,268" : "=r" (_value) )
     272    __asm__ volatile( "mfspr %0,268" : "=r" (_value) )
    273273#endif
    274274
     
    301301#define PPC_Set_decrementer( _clicks ) \
    302302  do { \
    303     asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
     303    __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \
    304304  } while (0)
    305305
    306306#define PPC_Get_decrementer( _clicks ) \
    307     asm volatile( "mfdec  %0" : "=r" (_clicks) )
     307    __asm__ volatile( "mfdec  %0" : "=r" (_clicks) )
    308308
    309309/*
     
    321321#if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
    322322/* See comment above (CPU_Get_timebase_low) */
    323     asm volatile( "mftbu %0" : "=r" (tbr_high_old));
    324     asm volatile( "mftb  %0" : "=r" (tbr_low));
    325     asm volatile( "mftbu %0" : "=r" (tbr_high));
     323    __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old));
     324    __asm__ volatile( "mftb  %0" : "=r" (tbr_low));
     325    __asm__ volatile( "mftbu %0" : "=r" (tbr_high));
    326326#else
    327     asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
    328     asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
    329     asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
     327    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
     328    __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low));
     329    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high));
    330330#endif
    331331  } while ( tbr_high_old != tbr_high );
     
    344344  tbr_low = (uint32_t) tbr;
    345345  tbr_high = (uint32_t) (tbr >> 32);
    346   asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
    347   asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
     346  __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low));
     347  __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high));
    348348
    349349}
     
    376376  ({ \
    377377    uint32_t val; \
    378     asm volatile (\
     378    __asm__ volatile (\
    379379      "mfspr %0, " PPC_STRINGOF(spr) \
    380380      : "=r" (val) \
     
    389389#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
    390390  do { \
    391     asm volatile (\
     391    __asm__ volatile (\
    392392      "mtspr " PPC_STRINGOF(spr) ", %0" \
    393393      : \
     
    463463  ({ \
    464464    uint32_t val; \
    465     asm volatile (\
     465    __asm__ volatile (\
    466466      "mfdcr %0, " PPC_STRINGOF(dcr) \
    467467      : "=r" (val) \
     
    478478#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
    479479  do { \
    480     asm volatile (\
     480    __asm__ volatile (\
    481481      "mtdcr " PPC_STRINGOF(dcr) ", %0" \
    482482      : \
  • c/src/lib/libcpu/powerpc/shared/src/cache.c

    rb15e7dc rf9acc33  
    3434  do { \
    3535      _value = 0;        /* to avoid warnings */ \
    36       asm volatile( \
     36      __asm__ volatile( \
    3737          "mfspr %0, 0x3f0;"     /* get HID0 */ \
    3838          "isync" \
     
    4444#define PPC_Set_HID0( _value ) \
    4545  do { \
    46       asm volatile( \
     46      __asm__ volatile( \
    4747          "isync;" \
    4848          "mtspr 0x3f0, %0;"     /* load HID0 */ \
     
    270270{
    271271  register const void *__address = _address;
    272   asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
     272  __asm__ volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
    273273}
    274274
     
    277277{
    278278  register const void *__address = _address;
    279   asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
     279  __asm__ volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
    280280}
    281281
     
    285285{
    286286  register const void *__address = _address;
    287   asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
     287  __asm__ volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
    288288}
    289289
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