Index: c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -1,2 +1,9 @@
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* Makefile.am, configure.ac, bootloader/Makefile.am, include/bsp.h,
+	wrapup/Makefile.am: Add MVME2100 BSP and MPC8240 support. There was
+	also a significant amount of spelling and whitespace cleanup.
+	* README.MVME2100: New file.
+
 2004-11-05	Joel Sherrill <joel@OARcorp.com>
 
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -26,4 +26,5 @@
 include_HEADERS += ../../powerpc/shared/include/nvram.h
 include_HEADERS += ../../shared/include/coverhd.h
+include_HEADERS += ../../shared/tod.h
 
 EXTRA_DIST = ../../powerpc/shared/start/start.S
@@ -57,4 +58,18 @@
 
 noinst_DATA += startup$(LIB_VARIANT).rel
+
+EXTRA_PROGRAMS += tod.rel
+CLEANFILES += tod.rel
+tod_rel_SOURCES = ../../shared/tod.c ../../powerpc/shared/tod/todcfg.c
+tod_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+tod_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += tod_g.rel
+CLEANFILES += tod_g.rel
+tod_g_rel_SOURCES = $(tod_rel_SOURCES)
+tod_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+tod_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += tod$(LIB_VARIANT).rel
 
 EXTRA_PROGRAMS += pclock.rel
@@ -230,5 +245,6 @@
 all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES)
 
-EXTRA_DIST += BOOTING README.MVME2300 README.OTHERBOARDS README.dec21140
+EXTRA_DIST += BOOTING README.mtx603e README.MVME2100 README.MVME2300 \
+    README.OTHERBOARDS README.mcp750 README.MVME2307 README.dec21140
 EXTRA_DIST += times.mcp750 times.mvme2307
 
@@ -276,4 +292,8 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
 
+$(PROJECT_INCLUDE)/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tod.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tod.h
+
 $(PROJECT_LIB)/start$(LIB_VARIANT).$(OBJEXT): start$(LIB_VARIANT).$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/start$(LIB_VARIANT).$(OBJEXT)
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2100
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2100	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2100	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -0,0 +1,123 @@
+#
+# $Id$
+#
+
+The MVME2100 is a Motorola VMEbus board which is similar to the other
+Motorola PowerPC boards supported by this BSP.  But it does not support
+the Motorola CPU Configuration Register.  This makes it impossible to
+dynamically probe and determine that you are executing on this board
+variant.  So this BSP variant must be explicitly built to only support
+the MVME2100.  The complete list of differences found so far is:
+
+  * No CPU Configuration Register
+  * one COM port
+  * COM port is on PCI IRQ not ISA IRQ
+  * limited on RAM (32 or 64 MB)
+  * uses the EPIC interrupt controller on the MPC8240
+  * does not have an ISA bus but has an ISA I/O address space
+  * cannot set DBAT2 in bspstart like other variants because
+    there are PCI/ISA Interrupt Acknowledge registers at this space
+    This BSP may have left some PCI memory uncovered
+  * PPCBug starts programs with vectors still in ROM
+
+Supported Features:
+  - Interrupt driven console using termios
+  - Network device driver
+  - Real-Time Clock driver
+  - Clock Tick Device Driver
+
+Things to address:
+  - Does not return to monitor
+  - Level 1 cache is disabled for now
+  - Check on trying to read CPU Configuration Register for CHRP/Prep for PCI
+    and report a failure if in the wrong mode.  May be able to set the model
+    but it may be hard to test if we break PPCBug.
+  - Use NVRAM for network configuration information
+
+BSP Features Not Implemented:
+  - VMEbus mapped in but untested
+  - OpenPIC features not required for BSP are not supported
+
+Memory Map
+==========
+                                                     BAT Mapping
+
+    ffff ffff   |------------------------------------| ----- ffff ffff
+                | ROM/FLASH Bank 0                   |   |
+    fff0 0000   |------------------------------------|   |
+                | System I/O                         |   |
+    ffe0 0000   |------------------------------------|   |
+                | Replicated ROM/FLASH Bank 0        |   |
+                | Replicated System I/O              |   |
+    ff80 0000   |------------------------------------|   |
+                | ROM/FLASH Bank 1                   | DBAT3
+    ff00 0000   |------------------------------------|  - Supervisor R/W
+                | PCI Interrupt Acknowledge          |  - Cache Inhibited
+    fef0 0000   |------------------------------------|  - Guarded
+                | PCI Configuration Data Register    |   |
+    fee0 0000   |------------------------------------|   | 
+                | PCI Configuration Address Register |   | 
+    fec0 0000   |------------------------------------|   | 
+                | PCI I/O Space                      |   | 
+    fe80 0000   |------------------------------------|   | 
+                | PCI/ISA I/O Space                  |   | 
+    fe00 0000   |------------------------------------|   | 
+                | PCI/ISA Memory Space               |   | 
+    fd00 0000   |------------------------------------|   | 
+                |                                    |   | 
+                |                      xxxxxxxxxxxxxx| ----- f000 0000
+                |                      x not mapped  |
+                |                      xxxxxxxxxxxxxx| ----- 9000 0000
+                |                                    |   |
+                |                                    |   |
+                | PCI Memory Space                   | DBAT2
+                |                                    |  - Supervisor R/W
+                |                                    |  - Cache Inhibited 
+                |                                    |  - Guarded
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+    8000 0000   |------------------------------------| ----- 8000 0000
+                |                      x             |   
+                |                      x not mapped  |
+                | Reserved             xxxxxxxxxxxxxx| ----- 1000 0000
+                |                                    |   |
+                |                                    |   |
+    0200 0000   |------------------------------------|   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                | DRAM (32MB)                        | DBAT1/IBAT1
+                |                                    |  - Supervisor R/W
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+    0000 0000   |------------------------------------| ----- 0000 0000
+                
+
+TTCP Performance on First Day Run
+=================================
+Fedora Core 1 on (according to /proc/cpuinfo) a 300 Mhz P3 using Netgear
+10/100 CardBus NIC on a dedicated 10BaseT LAN.  
+
+ON MVME2100:            ttcp -t -s 192.168.2.107
+REPORTED ON MVME2100:
+ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5001  tcp  -> 192.168.2.107
+ttcp-t: socket
+ttcp-t: connect
+ttcp-t: 16777216 bytes in 20.80 real seconds = 787.69 KB/sec +++
+ttcp-t: 2048 I/O calls, msec/call = 10.40, calls/sec = 98.46
+ttcp-t: 0.0user 20.8sys 0:20real 100% 0i+0d 0maxrss 0+0pf 0+0csw
+
+ON MVME2100:            ttcp -t -s 192.168.2.107
+REPORTED ON MVME2100:
+ttcp -r -s
+ttcp-r: buflen=8192, nbuf=2048, align=16384/0, port=5001  tcp
+ttcp-r: socket
+ttcp-r: accept from 192.168.2.107
+ttcp-r: 16777216 bytes in 15.41 real seconds = 1063.21 KB/sec +++
+ttcp-r: 11588 I/O calls, msec/call = 1.36, calls/sec = 751.98
+ttcp-r: 0.0user 15.4sys 0:15real 100% 0i+0d 0maxrss 0+0pf 0+0csw
+
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/bootloader/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/bootloader/Makefile.am	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/bootloader/Makefile.am	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -30,5 +30,5 @@
 # Remove references to EABI when compiling bootloader
 BOOTLOADER_CPU_FLAGS=$(subst -msdata=eabi,,$(subst -meabi,,$(CPU_CFLAGS)))
-AM_CPPFLAGS = -D__BOOT__ -DDEBUG
+AM_CPPFLAGS = -D__BOOT__
 AM_CFLAGS = $(GCC_SPECS) -specs bsp_specs -qrtems -mrelocatable -msoft-float \
     -mstrict-align -fno-builtin -Wall -mmultiple -mstring -O2 \
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -32,4 +32,14 @@
  The BSP actually contains the call that enables this.])
 
+RTEMS_BSPOPTS_SET([mvme2100],[mvme2100],[1])
+RTEMS_BSPOPTS_SET([mvme2100],[*],[])
+RTEMS_BSPOPTS_HELP([mvme2100],
+[Defined for MVME2100 -- undefined for others])
+
+RTEMS_BSPOPTS_SET([mpc8240],[mvme2100],[1])
+RTEMS_BSPOPTS_SET([mpc8240],[*],[])
+RTEMS_BSPOPTS_HELP([mpc8240],
+[Defined for boards with MPC8240 -- undefined for others])
+
 ## HACK: This should better be propagated through the BSP's bsp.h.
 ## however, this BSP doesn't have one :(
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -27,9 +27,21 @@
  */
 
+#if !defined(mvme2100)
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
+#endif
+
 #define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
 
-/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
-#define	_IO_BASE			PREP_ISA_IO_BASE
+/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
+#if defined(mvme2100)
+#define	_IO_BASE		CHRP_ISA_IO_BASE
+#define	_ISA_MEM_BASE		CHRP_ISA_MEM_BASE
+/* address of our ram on the PCI bus   */
+#define	PCI_DRAM_OFFSET		CHRP_PCI_DRAM_OFFSET
+#define PCI_MEM_BASE		0x80000000 
+#define PCI_MEM_BASE_ADJUSTMENT	0
+
+#else
+#define	_IO_BASE		PREP_ISA_IO_BASE
 #define	_ISA_MEM_BASE		PREP_ISA_MEM_BASE
 /* address of our ram on the PCI bus   */
@@ -37,13 +49,33 @@
 /* offset of pci memory as seen from the CPU */
 #define PCI_MEM_BASE		PREP_ISA_MEM_BASE
+#define PCI_MEM_BASE_ADJUSTMENT	PREP_ISA_MEM_BASE
+#endif
+
 
 /*
- *  base address definitions for several devices
+ *  Base address definitions for several devices
  *
+ *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
+ *  implementation of OpenPIC controller.  It also cannot be probed to
+ *  find out what it is which is VERY different from other Motorola boards.
  */
+
+#if defined(mvme2100)
+#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
+/* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
+#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
+
+#define MVME_HAS_DEC21140
+#else
 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
 #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
+
 #define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
 #define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
+
+#if defined(mvme2300)
+#define MVME_HAS_DEC21140
+#endif
+#endif
 
 #define BSP_CONSOLE_PORT	BSP_UART_COM1
@@ -61,7 +93,9 @@
 #define inport_word(port,value) (value = inw(port))
 #define inport_long(port,value) (value = inl(port))
+
 /*
  * Vital Board data Start using DATA RESIDUAL
  */
+
 /*
  * Total memory using RESIDUAL DATA
Index: c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.am	(revision d8682992821192ae52dfe0eeff5d814073041091)
+++ c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.am	(revision f9877d257769bd19f38189024fc38b14fe5460ca)
@@ -13,5 +13,5 @@
     ../pci$(LIB_VARIANT).rel ../residual$(LIB_VARIANT).rel \
     ../vectors$(LIB_VARIANT).rel ../motorola$(LIB_VARIANT).rel \
-    ../vme$(LIB_VARIANT).rel
+    ../tod$(LIB_VARIANT).rel ../vme$(LIB_VARIANT).rel
 ___libbsp_a_LIBADD += \
     ../../../../libcpu/@RTEMS_CPU@/shared/cpuIdent$(LIB_VARIANT).rel \
