![[RTEMS Logo]](/images/logo.png){kind=logo}
Changeset f8f370b6 in rtems
- Timestamp:
- Apr 16, 1997, 5:45:35 PM (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- f9f375e
- Parents:
- 34217ccf
- Location:
- c/src/lib/libbsp/m68k/gen68360
- Files:
-
- 8 edited
-
README (modified) (4 diffs)
-
clock/ckinit.c (modified) (1 diff)
-
include/bsp.h (modified) (1 diff)
-
start/start360.s (modified) (2 diffs)
-
start360/start360.s (modified) (2 diffs)
-
startup/init68360.c (modified) (7 diffs)
-
startup/linkcmds (modified) (5 diffs)
-
startup/linkcmds.bootp (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/gen68360/README
r34217ccf rf8f370b6 25 25 # phase by setting the Makefile LDFLAGS definition appropriately. 26 26 # 27 # Decisions to be made a link-edit time include: 28 # - The version of hardware on which the application is to run. 29 # This is selected by defining the MC68360HardwareType variable. 30 # Supported values are: 31 # MC68360HardwareTypeMotorolaGeneric (default) 32 # MC68360HardwareTypeAtlasHSB 33 # To select the Atlas Computer Equipment HSB, 34 # --defsym MC68360HardwareType=MC68360HardwareTypeAtlasHSB 35 # 27 # Decisions made at compile time include: 28 # - If the CPU is a member of the 68040 family, the BSP is 29 # compiled for a generic 68040/68360 system as described 30 # in Chapter 9 of the MC68360 User's Manual. 31 # - If the preprocessor symbol M68360_ATLAS_HSB is defined, 32 # the BSP is compiled for an Atlas HSB card. 33 # - Otherwise, the BSP is compiled for a generic 68360 system 34 # as described in Chapter 9 of the MC68360 User's Manual. 35 # 36 # Decisions to be made a link-edit time are: 36 37 # - The amount of dynamic RAM in the system. This value applies 37 38 # only to hardware versions which support different sizes of RAM. … … 46 47 # --defsym HeapSize=0x40000 47 48 # 48 49 BSP NAME: gen68360 49 # - The Ethernet address for network boot proms. 50 51 BSP NAME: gen68360 or gen68360_040 50 52 BOARD: Generic 68360 as described in Motorola MC68360 User's Manual 51 53 BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB) 52 54 BOARD: Atlas Computer Equipment Inc. Advanced Communication Engine (ACE) 55 BOARD: Arnewsh SBC360 68040/68360 card 53 56 BUS: none 54 CPU FAMILY: Motorola CPU32+ 57 CPU FAMILY: Motorola CPU32+, Motorola 68040 55 58 COPROCESSORS: none 56 59 MODE: not applicable … … 101 104 binutils-2.6 102 105 103 Verification 104 ------------ 106 Verification (Standalone 68360) 107 ------------------------------- 105 108 Single processor tests: Passed 106 109 Multi-processort tests: not applicable … … 291 294 Ethernet interface on SCC1 292 295 293 The board support package has been tested with a home-built board and with an 294 ACE360A board produced by: 295 Atlas Computer Equipment 296 703 Colina Lane 297 Santa Barbara, CA 93103 296 The board support package has been tested with: 297 A home-built 68360 board 298 An ACE360A and an HSB board produced by: 299 Atlas Computer Equipment 300 703 Colina Lane 301 Santa Barbara, CA 93103 302 A 68040/68360 board (SBC360) produced by: 303 Arnewsh Inc. 304 P.O. Box 270352 305 Fort Collins, CO 80527-0352 -
c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c
r34217ccf rf8f370b6 58 58 Clock_isr (rtems_vector_number vector) 59 59 { 60 /* 61 * Perform a dummy read of DPRAM. 62 * This works around a bug in Rev. B of the 68360 63 */ 64 m360.dpram0[0]; 65 66 /* 67 * Announce the clock tick 68 */ 60 69 Clock_driver_ticks++; 61 70 rtems_clock_tick(); -
c/src/lib/libbsp/m68k/gen68360/include/bsp.h
r34217ccf rf8f370b6 133 133 */ 134 134 extern void *_RomBase, *_RamBase, *_RamSize; 135 extern void *_MC68360HardwareType;136 extern void *_MC68360HardwareTypeMotorolaGeneric;137 extern void *_MC68360HardwareTypeAtlasHSB;138 135 139 136 /* -
c/src/lib/libbsp/m68k/gen68360/start/start360.s
r34217ccf rf8f370b6 1 /* entry.s1 /* 2 2 * 3 3 * This file contains the entry point for the application. … … 312 312 .long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address 313 313 314 .global start 314 315 /* 315 316 * Initial PC 316 317 */ 317 .global start318 318 start: 319 319 /* 320 320 * Step 2: Stay in Supervisor Mode 321 * (i.e. just do nothing for this step) 322 */ 321 */ 322 #if ( M68K_HAS_SEPARATE_STACKS == 1 ) 323 oriw #0x3000,sr | Switch to Master Stack Pointer 324 lea SYM(m360)+1024-64,a7 | Load stack pointer with space 325 | for the Interrupt Stack 326 #endif 323 327 324 328 /* -
c/src/lib/libbsp/m68k/gen68360/start360/start360.s
r34217ccf rf8f370b6 1 /* entry.s1 /* 2 2 * 3 3 * This file contains the entry point for the application. … … 312 312 .long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address 313 313 314 .global start 314 315 /* 315 316 * Initial PC 316 317 */ 317 .global start318 318 start: 319 319 /* 320 320 * Step 2: Stay in Supervisor Mode 321 * (i.e. just do nothing for this step) 322 */ 321 */ 322 #if ( M68K_HAS_SEPARATE_STACKS == 1 ) 323 oriw #0x3000,sr | Switch to Master Stack Pointer 324 lea SYM(m360)+1024-64,a7 | Load stack pointer with space 325 | for the Interrupt Stack 326 #endif 323 327 324 328 /* -
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
r34217ccf rf8f370b6 33 33 * Initialize MC68360 34 34 */ 35 36 35 void _Init68360 (void) 37 36 { 38 37 int i; 39 unsigned long l;40 38 m68k_isr_entry *vbr; 41 39 extern void _CopyDataClearBSSAndStart (void); 40 41 #if (defined (m68040) || defined (m68lc040) || defined (m68ec040)) 42 /* 43 ******************************************* 44 * Motorola 68040 and companion-mode 68360 * 45 ******************************************* 46 */ 42 47 43 48 /* … … 49 54 * else if (Double bus fault, watchdog or soft reset) 50 55 * Skip to step 12 51 * else (must be a CPU32+reset command)56 * else (must be a reset command) 52 57 * Skip to step 14 53 58 */ … … 58 63 * Change if you're not using an external 25 MHz oscillator. 59 64 */ 60 m360.clkocr = 0x8 F; /* No more writes, no clock outputs*/65 m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */ 61 66 m360.pllcr = 0xD000; /* PLL, no writes, no prescale, 62 67 no LPSTOP slowdown, PLL X1 */ … … 68 73 * Watchdog causes system reset 69 74 * Slowest watchdog timeout 70 * Enable double bus fault monitor75 * Disable double bus fault monitor 71 76 * Enable bus monitor external 72 * 1 28clocks for external timeout73 */ 74 m360.sypcr = 0x7 F;77 * 1024 clocks for external timeout 78 */ 79 m360.sypcr = 0x74; 75 80 76 81 /* … … 87 92 /* 88 93 * Step 10: Write PEPAR 89 * SINTOUT not used (CPU32+ mode)90 * CF1MODE= 00 (CONFIG1 input)91 * RAS1* double drive92 * WE0* - WE3*93 * OE*output94 * SINTOUT standard M68000 family interrupt level encoding 95 * CF1MODE=10 (BCLRO* output) 96 * No RAS1* double drive 97 * A31 - A28 98 * AMUX output 94 99 * CAS2* - CAS3* 95 100 * CAS0* - CAS1* 96 101 * CS7* 97 102 * AVEC* 98 * HARDWARE: 99 * Change if you are using a different memory configuration 100 * (static RAM, external address multiplexing, etc). 101 */ 102 m360.pepar = 0x0180; 103 */ 104 m360.pepar = 0x3440; 103 105 104 106 /* 105 107 * Step 11: Remap Chip Select 0 (CS0*), set up GMR 106 108 */ 107 if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) { 108 m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN | 109 M360_GMR_RCYC(0) | M360_GMR_PGS(1) | 110 M360_GMR_DPS_32BIT | M360_GMR_DWQ | 111 M360_GMR_GAMX; 112 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 113 M360_MEMC_BR_V; 114 m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | 115 M360_MEMC_OR_8BIT; 116 } 117 else { 118 /* 119 * 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips) 120 * 60 nsec DRAM 121 * 180 nsec ROM (3 wait states) 122 */ 123 switch ((unsigned long)&_RamSize) { 124 default: 125 case 4*1024*1024: 126 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 127 M360_GMR_RCYC(0) | M360_GMR_PGS(3) | 128 M360_GMR_DPS_32BIT | M360_GMR_NCS | 129 M360_GMR_GAMX; 130 break; 131 132 case 16*1024*1024: 133 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 134 M360_GMR_RCYC(0) | M360_GMR_PGS(5) | 135 M360_GMR_DPS_32BIT | M360_GMR_NCS | 136 M360_GMR_GAMX; 137 break; 138 139 case 64*1024*1024: 140 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 141 M360_GMR_RCYC(0) | M360_GMR_PGS(7) | 142 M360_GMR_DPS_32BIT | M360_GMR_NCS | 143 M360_GMR_GAMX; 144 break; 145 } 146 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 147 M360_MEMC_BR_V; 148 m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | 149 M360_MEMC_OR_8BIT; 150 } 109 /* 110 * 512 addresses per DRAM page (256K DRAM chips) 111 * 70 nsec DRAM 112 * 180 nsec ROM (3 wait states) 113 */ 114 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 115 M360_GMR_RCYC(0) | M360_GMR_PGS(1) | 116 M360_GMR_DPS_32BIT | M360_GMR_NCS | 117 M360_GMR_TSS40; 118 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 119 M360_MEMC_BR_V; 120 m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | 121 M360_MEMC_OR_32BIT; 151 122 152 123 /* 153 124 * Step 12: Initialize the system RAM 154 125 */ 155 if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) { 156 /* first bank 1MByte DRAM */ 157 m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | 158 M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; 159 m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; 160 161 /* second bank 1MByte DRAM */ 162 m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | 163 M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; 164 m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) | 126 /* 127 * Set up option/base registers 128 * 1M DRAM 129 * 70 nsec DRAM 130 * Enable burst mode 131 * No parity checking 132 * Wait for chips to power up 133 * Perform 8 read cycles 134 */ 135 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 136 M360_MEMC_OR_1MB | 137 M360_MEMC_OR_DRAM; 138 m360.memc[1].br = (unsigned long)&_RamBase | 139 M360_MEMC_BR_BACK40 | 165 140 M360_MEMC_BR_V; 166 167 /* flash rom socket U6 on CS5 */ 168 m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP | 169 M360_MEMC_BR_V; 170 m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | 171 M360_MEMC_OR_8BIT; 172 173 /* CSRs on CS7 */ 174 m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB | 175 M360_MEMC_OR_8BIT; 176 m360.memc[7].br = ATLASHSB_ESR | 0x01; 177 for (i = 0; i < 50000; i++) 178 continue; 179 for (i = 0; i < 8; ++i) 180 *((volatile unsigned long *)(unsigned long)&_RamBase); 181 } 182 else { 183 /* 184 * Set up option/base registers 185 * 4M/16M/64M DRAM 186 * 60 nsec DRAM 187 * Wait for chips to power up 188 * Perform 8 read cycles 189 * Set all parity bits to correct state 190 * Enable parity checking 191 */ 192 switch ((unsigned long)&_RamSize) { 193 default: 194 case 4*1024*1024: 195 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 196 M360_MEMC_OR_4MB | 197 M360_MEMC_OR_DRAM; 198 break; 199 200 case 16*1024*1024: 201 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 202 M360_MEMC_OR_16MB | 203 M360_MEMC_OR_DRAM; 204 break; 205 206 case 64*1024*1024: 207 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 208 M360_MEMC_OR_64MB | 209 M360_MEMC_OR_DRAM; 210 break; 211 } 212 m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; 213 for (i = 0; i < 50000; i++) 214 continue; 215 for (i = 0; i < 8; ++i) 216 *((volatile unsigned long *)(unsigned long)&_RamBase); 217 for (l = 0 ; l < (unsigned long)&_RamSize ; l += sizeof (unsigned long)) { 218 volatile unsigned long *lp; 219 lp = (unsigned long *)((unsigned char *)&_RamBase + i); 220 *lp = *lp; 221 } 222 m360.memc[1].br = (unsigned long)&_RamBase | 223 M360_MEMC_BR_PAREN | M360_MEMC_BR_V; 224 } 141 for (i = 0; i < 50000; i++) 142 continue; 143 for (i = 0; i < 8; ++i) 144 *((volatile unsigned long *)(unsigned long)&_RamBase); 225 145 226 146 /* … … 254 174 /* 255 175 * Step 15: Set module configuration register 176 * Bus request MC68040 Arbitration ID 3 177 * Bus asynchronous timing mode (work around bug in Rev. B) 178 * Arbitration asynchronous timing mode 179 * Disable timers during FREEZE 180 * Disable bus monitor during FREEZE 181 * BCLRO* arbitration level 3 182 * No show cycles 183 * User/supervisor access 184 * Bus clear in arbitration ID level 3 185 * SIM60 interrupt sources higher priority than CPM 186 */ 187 m360.mcr = 0x6000EC3F; 188 189 #elif (defined (M68360_ATLAS_HSB)) 190 /* 191 ****************************************** 192 * Standalone Motorola 68360 -- ATLAS HSB * 193 ****************************************** 194 */ 195 196 /* 197 * Step 6: Is this a power-up reset? 198 * For now we just ignore this and do *all* the steps 199 * Someday we might want to: 200 * if (Hard, Loss of Clock, Power-up) 201 * Do all steps 202 * else if (Double bus fault, watchdog or soft reset) 203 * Skip to step 12 204 * else (must be a CPU32+ reset command) 205 * Skip to step 14 206 */ 207 208 /* 209 * Step 7: Deal with clock synthesizer 210 * HARDWARE: 211 * Change if you're not using an external 25 MHz oscillator. 212 */ 213 m360.clkocr = 0x8F; /* No more writes, no clock outputs */ 214 m360.pllcr = 0xD000; /* PLL, no writes, no prescale, 215 no LPSTOP slowdown, PLL X1 */ 216 m360.cdvcr = 0x8000; /* No more writes, no clock division */ 217 218 /* 219 * Step 8: Initialize system protection 220 * Disable watchdog FIXME: Should use watchdog!!!! 221 * Watchdog causes system reset 222 * Slowest watchdog timeout 223 * Enable double bus fault monitor 224 * Enable bus monitor external 225 * 128 clocks for external timeout 226 */ 227 m360.sypcr = 0x7F; 228 229 /* 230 * Step 9: Clear parameter RAM and reset communication processor module 231 */ 232 for (i = 0 ; i < 192 ; i += sizeof (long)) { 233 *((long *)((char *)&m360 + 0xC00 + i)) = 0; 234 *((long *)((char *)&m360 + 0xD00 + i)) = 0; 235 *((long *)((char *)&m360 + 0xE00 + i)) = 0; 236 *((long *)((char *)&m360 + 0xF00 + i)) = 0; 237 } 238 M360ExecuteRISC (M360_CR_RST); 239 240 /* 241 * Step 10: Write PEPAR 242 * SINTOUT not used (CPU32+ mode) 243 * CF1MODE=00 (CONFIG1 input) 244 * RAS1* double drive 245 * WE0* - WE3* 246 * OE* output 247 * CAS2* - CAS3* 248 * CAS0* - CAS1* 249 * CS7* 250 * AVEC* 251 * HARDWARE: 252 * Change if you are using a different memory configuration 253 * (static RAM, external address multiplexing, etc). 254 */ 255 m360.pepar = 0x0180; 256 257 /* 258 * Step 11: Remap Chip Select 0 (CS0*), set up GMR 259 */ 260 m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN | 261 M360_GMR_RCYC(0) | M360_GMR_PGS(1) | 262 M360_GMR_DPS_32BIT | M360_GMR_DWQ | 263 M360_GMR_GAMX; 264 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 265 M360_MEMC_BR_V; 266 m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | 267 M360_MEMC_OR_8BIT; 268 269 /* 270 * Step 12: Initialize the system RAM 271 */ 272 /* first bank 1MByte DRAM */ 273 m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | 274 M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; 275 m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; 276 277 /* second bank 1MByte DRAM */ 278 m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | 279 M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; 280 m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) | 281 M360_MEMC_BR_V; 282 283 /* flash rom socket U6 on CS5 */ 284 m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP | 285 M360_MEMC_BR_V; 286 m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | 287 M360_MEMC_OR_8BIT; 288 289 /* CSRs on CS7 */ 290 m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB | 291 M360_MEMC_OR_8BIT; 292 m360.memc[7].br = ATLASHSB_ESR | 0x01; 293 for (i = 0; i < 50000; i++) 294 continue; 295 for (i = 0; i < 8; ++i) 296 *((volatile unsigned long *)(unsigned long)&_RamBase); 297 298 /* 299 * Step 13: Copy the exception vector table to system RAM 300 */ 301 m68k_get_vbr (vbr); 302 for (i = 0; i < 256; ++i) 303 M68Kvec[i] = vbr[i]; 304 m68k_set_vbr (M68Kvec); 305 306 /* 307 * Step 14: More system initialization 308 * SDCR (Serial DMA configuration register) 309 * Disable SDMA during FREEZE 310 * Give SDMA priority over all interrupt handlers 311 * Set DMA arbiration level to 4 312 * CICR (CPM interrupt configuration register): 313 * SCC1 requests at SCCa position 314 * SCC2 requests at SCCb position 315 * SCC3 requests at SCCc position 316 * SCC4 requests at SCCd position 317 * Interrupt request level 4 318 * Maintain original priority order 319 * Vector base 128 320 * SCCs priority grouped at top of table 321 */ 322 m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4; 323 m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | 324 (4 << 13) | (0x1F << 8) | (128); 325 326 /* 327 * Step 15: Set module configuration register 256 328 * Disable timers during FREEZE 257 329 * Enable bus monitor during FREEZE … … 264 336 m360.mcr = 0x4C7F; 265 337 338 #else 339 /* 340 *************************************************** 341 * Generic Standalone Motorola 68360 * 342 * As described in MC68360 User's Manual * 343 * Atlas ACE360 * 344 *************************************************** 345 */ 346 347 /* 348 * Step 6: Is this a power-up reset? 349 * For now we just ignore this and do *all* the steps 350 * Someday we might want to: 351 * if (Hard, Loss of Clock, Power-up) 352 * Do all steps 353 * else if (Double bus fault, watchdog or soft reset) 354 * Skip to step 12 355 * else (must be a CPU32+ reset command) 356 * Skip to step 14 357 */ 358 359 /* 360 * Step 7: Deal with clock synthesizer 361 * HARDWARE: 362 * Change if you're not using an external 25 MHz oscillator. 363 */ 364 m360.clkocr = 0x8F; /* No more writes, no clock outputs */ 365 m360.pllcr = 0xD000; /* PLL, no writes, no prescale, 366 no LPSTOP slowdown, PLL X1 */ 367 m360.cdvcr = 0x8000; /* No more writes, no clock division */ 368 369 /* 370 * Step 8: Initialize system protection 371 * Disable watchdog FIXME: Should use watchdog!!!! 372 * Watchdog causes system reset 373 * Slowest watchdog timeout 374 * Enable double bus fault monitor 375 * Enable bus monitor external 376 * 128 clocks for external timeout 377 */ 378 m360.sypcr = 0x7F; 379 380 /* 381 * Step 9: Clear parameter RAM and reset communication processor module 382 */ 383 for (i = 0 ; i < 192 ; i += sizeof (long)) { 384 *((long *)((char *)&m360 + 0xC00 + i)) = 0; 385 *((long *)((char *)&m360 + 0xD00 + i)) = 0; 386 *((long *)((char *)&m360 + 0xE00 + i)) = 0; 387 *((long *)((char *)&m360 + 0xF00 + i)) = 0; 388 } 389 M360ExecuteRISC (M360_CR_RST); 390 391 /* 392 * Step 10: Write PEPAR 393 * SINTOUT not used (CPU32+ mode) 394 * CF1MODE=00 (CONFIG1 input) 395 * RAS1* double drive 396 * WE0* - WE3* 397 * OE* output 398 * CAS2* - CAS3* 399 * CAS0* - CAS1* 400 * CS7* 401 * AVEC* 402 * HARDWARE: 403 * Change if you are using a different memory configuration 404 * (static RAM, external address multiplexing, etc). 405 */ 406 m360.pepar = 0x0180; 407 408 /* 409 * Step 11: Remap Chip Select 0 (CS0*), set up GMR 410 */ 411 /* 412 * 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips) 413 * 60 nsec DRAM 414 * 180 nsec ROM (3 wait states) 415 */ 416 switch ((unsigned long)&_RamSize) { 417 default: 418 case 4*1024*1024: 419 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 420 M360_GMR_RCYC(0) | M360_GMR_PGS(3) | 421 M360_GMR_DPS_32BIT | M360_GMR_NCS | 422 M360_GMR_GAMX; 423 break; 424 425 case 16*1024*1024: 426 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 427 M360_GMR_RCYC(0) | M360_GMR_PGS(5) | 428 M360_GMR_DPS_32BIT | M360_GMR_NCS | 429 M360_GMR_GAMX; 430 break; 431 432 case 64*1024*1024: 433 m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | 434 M360_GMR_RCYC(0) | M360_GMR_PGS(7) | 435 M360_GMR_DPS_32BIT | M360_GMR_NCS | 436 M360_GMR_GAMX; 437 break; 438 } 439 m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | 440 M360_MEMC_BR_V; 441 m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | 442 M360_MEMC_OR_8BIT; 443 444 /* 445 * Step 12: Initialize the system RAM 446 */ 447 /* 448 * Set up option/base registers 449 * 4M/16M/64M DRAM 450 * 60 nsec DRAM 451 * Wait for chips to power up 452 * Perform 8 read cycles 453 * Set all parity bits to correct state 454 * Enable parity checking 455 */ 456 switch ((unsigned long)&_RamSize) { 457 default: 458 case 4*1024*1024: 459 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 460 M360_MEMC_OR_4MB | 461 M360_MEMC_OR_DRAM; 462 break; 463 464 case 16*1024*1024: 465 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 466 M360_MEMC_OR_16MB | 467 M360_MEMC_OR_DRAM; 468 break; 469 470 case 64*1024*1024: 471 m360.memc[1].or = M360_MEMC_OR_TCYC(0) | 472 M360_MEMC_OR_64MB | 473 M360_MEMC_OR_DRAM; 474 break; 475 } 476 m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; 477 for (i = 0; i < 50000; i++) 478 continue; 479 for (i = 0; i < 8; ++i) 480 *((volatile unsigned long *)(unsigned long)&_RamBase); 481 for (i = 0 ; i < (unsigned long)&_RamSize ; i += sizeof (unsigned long)) { 482 volatile unsigned long *lp; 483 lp = (unsigned long *)((unsigned char *)&_RamBase + i); 484 *lp = *lp; 485 } 486 m360.memc[1].br = (unsigned long)&_RamBase | 487 M360_MEMC_BR_PAREN | M360_MEMC_BR_V; 488 489 /* 490 * Step 13: Copy the exception vector table to system RAM 491 */ 492 m68k_get_vbr (vbr); 493 for (i = 0; i < 256; ++i) 494 M68Kvec[i] = vbr[i]; 495 m68k_set_vbr (M68Kvec); 496 497 /* 498 * Step 14: More system initialization 499 * SDCR (Serial DMA configuration register) 500 * Disable SDMA during FREEZE 501 * Give SDMA priority over all interrupt handlers 502 * Set DMA arbiration level to 4 503 * CICR (CPM interrupt configuration register): 504 * SCC1 requests at SCCa position 505 * SCC2 requests at SCCb position 506 * SCC3 requests at SCCc position 507 * SCC4 requests at SCCd position 508 * Interrupt request level 4 509 * Maintain original priority order 510 * Vector base 128 511 * SCCs priority grouped at top of table 512 */ 513 m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4; 514 m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | 515 (4 << 13) | (0x1F << 8) | (128); 516 517 /* 518 * Step 15: Set module configuration register 519 * Disable timers during FREEZE 520 * Enable bus monitor during FREEZE 521 * BCLRO* arbitration level 3 522 * No show cycles 523 * User/supervisor access 524 * Bus clear interrupt service level 7 525 * SIM60 interrupt sources higher priority than CPM 526 */ 527 m360.mcr = 0x4C7F; 528 #endif 529 266 530 /* 267 531 * Copy data, clear BSS, switch stacks and call main() -
c/src/lib/libbsp/m68k/gen68360/startup/linkcmds
r34217ccf rf8f370b6 1 1 /* 2 2 * This file contains GNU linker directives for a generic MC68360 board. 3 * Variations in hardware type and dynamic memory size can be made4 * byoverriding some values with linker command-line arguments.3 * Variations in memory size and allocation can be made by 4 * overriding some values with linker command-line arguments. 5 5 * 6 6 * Saskatchewan Accelerator Laboratory … … 23 23 24 24 /* 25 * Declare hardware type26 */27 MC68360HardwareTypeMotorolaGeneric = 0;28 MC68360HardwareTypeAtlasHSB = 1;29 MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;30 31 /*32 25 * Declare on-board memory. 33 26 * It would be nice if the ram length could be given as … … 37 30 MEMORY { 38 31 ram : ORIGIN = 0x00000000, LENGTH = 64M 39 rom : ORIGIN = 0x FF000000, LENGTH = 1M40 dpram : ORIGIN = 0x FE000000, LENGTH = 8k32 rom : ORIGIN = 0x0F000000, LENGTH = 1M 33 dpram : ORIGIN = 0x0E000000, LENGTH = 8k 41 34 } 42 35 … … 45 38 */ 46 39 ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12; 47 48 /*49 * Declare hardware type.50 * Acceptable values are:51 * 0 - Generic system as described in the MC68360 User's Manual52 * (MC68360UM/AD Rev. 1).53 * 1 - ATLAS Computer Equipment Incorporated ACE360/HSB.54 */55 MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;56 40 57 41 /* … … 64 48 _RamSize = RamSize; 65 49 __RamSize = RamSize; 66 _MC68360HardwareType = MC68360HardwareType;67 __MC68360HardwareType = MC68360HardwareType;68 _MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;69 __MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;70 _MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;71 __MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;72 50 73 51 /* -
c/src/lib/libbsp/m68k/gen68360/startup/linkcmds.bootp
r34217ccf rf8f370b6 5 5 * 6 6 * These linker directives are for producing a PROM version. 7 * To create the PROM image from the linker output you must use objcopy 8 * (--adjust-section-vma) to place the data segment at the end of the text 9 * segment in the PROM. The start-up code takes care of copying this region 10 * to RAM. 7 * The data segment is placed at the end of the text segment in the PROM. 8 * The start-up code takes care of copying this region to RAM. 11 9 * 12 10 * Saskatchewan Accelerator Laboratory … … 14 12 * Saskatoon, Saskatchewan, CANADA 15 13 * eric@skatter.usask.ca 16 * 14 * 17 15 * $Id$ 18 16 */ … … 29 27 30 28 /* 31 * Declare hardware type32 */33 MC68360HardwareTypeMotorolaGeneric = 0;34 MC68360HardwareTypeAtlasHSB = 1;35 MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;36 37 /*38 29 * Declare on-board memory. 39 30 * It would be nice if the ram length could be given as … … 44 35 ram : ORIGIN = 0x00000000, LENGTH = 64M 45 36 myram : ORIGIN = 4M-512k, LENGTH = 512k 46 rom : ORIGIN = 0x FF000000, LENGTH = 1M47 dpram : ORIGIN = 0x FE000000, LENGTH = 8k37 rom : ORIGIN = 0x0F000000, LENGTH = 1M 38 dpram : ORIGIN = 0x0E000000, LENGTH = 8k 48 39 } 49 40 … … 52 43 */ 53 44 ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12; 54 55 /*56 * Declare hardware type.57 * Acceptable values are:58 * 0 - Generic system as described in the MC68360 User's Manual59 * (MC68360UM/AD Rev. 1).60 * 1 - ATLAS Computer Equipment Incorporated ACE360/HSB.61 */62 MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;63 45 64 46 /* … … 71 53 _RamSize = RamSize; 72 54 __RamSize = RamSize; 73 _MC68360HardwareType = MC68360HardwareType;74 __MC68360HardwareType = MC68360HardwareType;75 _MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;76 __MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;77 _MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;78 __MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;79 55 80 56 /*
Note: See TracChangeset
for help on using the changeset viewer.
