Changeset f8ad5bb2 in rtems


Ignore:
Timestamp:
Aug 28, 2020, 3:13:47 AM (13 months ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
cb2afd2
Parents:
1480c3f
git-author:
Kinsey Moore <kinsey.moore@…> (08/28/20 03:13:47)
git-committer:
Joel Sherrill <joel@…> (10/05/20 21:11:39)
Message:

bsps: Break out AArch32 GICv3 support

This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.

Files:
1 added
17 edited
5 moved

Legend:

Unmodified
Added
Removed
  • bsps/arm/altera-cyclone-v/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    2828
    2929#include <bsp/arm-a9mpcore-irq.h>
    30 #include <bsp/arm-gic-irq.h>
     30#include <dev/irq/arm-gic-irq.h>
    3131#include <bsp/alt_interrupt_common.h>
    3232
  • bsps/arm/altera-cyclone-v/include/tm27.h

    r1480c3f rf8ad5bb2  
    3434 */
    3535
    36 #include <bsp/arm-gic-tm27.h>
     36#include <dev/irq/arm-gic-tm27.h>
    3737
    3838/** @} */
  • bsps/arm/headers.am

    r1480c3f rf8ad5bb2  
    1818include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h
    1919include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h
    20 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h
    21 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
    22 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
    23 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
    2420include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
    2521include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
  • bsps/arm/imx/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    2121#include <rtems/irq-extension.h>
    2222
    23 #include <bsp/arm-gic-irq.h>
     23#include <dev/irq/arm-gic-irq.h>
    2424
    2525#ifdef __cplusplus
  • bsps/arm/imx/include/tm27.h

    r1480c3f rf8ad5bb2  
    2020#define __tm27_h
    2121
    22 #include <bsp/arm-gic-tm27.h>
     22#include <dev/irq/arm-gic-tm27.h>
    2323
    2424#endif /* __tm27_h */
  • bsps/arm/include/bsp/arm-a9mpcore-start.h

    r1480c3f rf8ad5bb2  
    3232#include <bsp/arm-a9mpcore-regs.h>
    3333#include <bsp/arm-errata.h>
    34 #include <bsp/arm-gic-irq.h>
     34#include <dev/irq/arm-gic-irq.h>
    3535
    3636#ifdef __cplusplus
  • bsps/arm/realview-pbx-a9/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    3030
    3131#include <bsp/arm-a9mpcore-irq.h>
    32 #include <bsp/arm-gic-irq.h>
     32#include <dev/irq/arm-gic-irq.h>
    3333
    3434/**
  • bsps/arm/realview-pbx-a9/include/tm27.h

    r1480c3f rf8ad5bb2  
    3737#define __tm27_h
    3838
    39 #include <bsp/arm-gic-tm27.h>
     39#include <dev/irq/arm-gic-tm27.h>
    4040
    4141#endif /* __tm27_h */
  • bsps/arm/shared/irq/irq-gic.c

    r1480c3f rf8ad5bb2  
    1313 */
    1414
    15 #include <bsp/arm-gic.h>
     15#include <dev/irq/arm-gic.h>
    1616
    1717#include <rtems/score/armv4.h>
  • bsps/arm/xen/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    3535#include <rtems/irq-extension.h>
    3636
    37 #include <bsp/arm-gic-irq.h>
     37#include <dev/irq/arm-gic-irq.h>
    3838
    3939#ifdef __cplusplus
  • bsps/arm/xen/include/tm27.h

    r1480c3f rf8ad5bb2  
    3434#define __tm27_h
    3535
    36 #include <bsp/arm-gic-tm27.h>
     36#include <dev/irq/arm-gic-tm27.h>
    3737
    3838#endif /* __tm27_h */
  • bsps/arm/xilinx-zynq/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    4141
    4242#include <bsp/arm-a9mpcore-irq.h>
    43 #include <bsp/arm-gic-irq.h>
     43#include <dev/irq/arm-gic-irq.h>
    4444
    4545#ifdef __cplusplus
  • bsps/arm/xilinx-zynq/include/tm27.h

    r1480c3f rf8ad5bb2  
    4545 */
    4646
    47 #include <bsp/arm-gic-tm27.h>
     47#include <dev/irq/arm-gic-tm27.h>
    4848
    4949#endif /* __tm27_h */
  • bsps/arm/xilinx-zynqmp/include/bsp/irq.h

    r1480c3f rf8ad5bb2  
    4545#include <rtems/irq-extension.h>
    4646
    47 #include <bsp/arm-gic-irq.h>
     47#include <dev/irq/arm-gic-irq.h>
    4848
    4949#ifdef __cplusplus
  • bsps/arm/xilinx-zynqmp/include/tm27.h

    r1480c3f rf8ad5bb2  
    5050 */
    5151
    52 #include <bsp/arm-gic-tm27.h>
     52#include <dev/irq/arm-gic-tm27.h>
    5353
    5454#endif /* __tm27_h */
  • bsps/headers.am

    r1480c3f rf8ad5bb2  
    2121include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
    2222include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
     23
     24include_dev_irqdir = $(includedir)/dev/irq
     25include_dev_irq_HEADERS =
     26include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-irq.h
     27include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-regs.h
     28include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-tm27.h
     29include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic.h
    2330
    2431include_dev_serialdir = $(includedir)/dev/serial
  • bsps/include/dev/irq/arm-gic-irq.h

    r1480c3f rf8ad5bb2  
    2525
    2626#include <bsp.h>
    27 #include <bsp/arm-gic.h>
     27#include <dev/irq/arm-gic.h>
    2828#include <rtems/score/processormask.h>
    2929
     
    109109}
    110110
     111/**
     112 * This architecture-specific function sets the exception vector for handling
     113 * IRQs.
     114 */
     115void arm_interrupt_facility_set_exception_handler(void);
     116
     117/**
     118 * This architecture-specific function dispatches a triggered IRQ.
     119 *
     120 * @param[in] vector The vector on which the IRQ occurred.
     121 */
     122void arm_interrupt_handler_dispatch(rtems_vector_number vector);
     123
     124/**
     125 * This is the GICv3 interrupt dispatcher that is to be called from the
     126 * architecture-specific implementation of the IRQ handler.
     127 */
     128void gicv3_interrupt_dispatch(void);
     129
    111130static inline uint32_t arm_gic_irq_processor_count(void)
    112131{
  • bsps/include/dev/irq/arm-gic.h

    r1480c3f rf8ad5bb2  
    2424#define LIBBSP_ARM_SHARED_ARM_GIC_H
    2525
    26 #include <bsp/arm-gic-regs.h>
     26#include <dev/irq/arm-gic-regs.h>
    2727
    2828#include <stdbool.h>
  • bsps/shared/dev/irq/arm-gicv3.c

    r1480c3f rf8ad5bb2  
    2626 */
    2727
    28 #include <bsp/arm-gic.h>
    29 
    30 #include <rtems/score/armv4.h>
    31 
    32 #include <libcpu/arm-cp15.h>
     28#include <dev/irq/arm-gic.h>
    3329
    3430#include <bsp/irq.h>
     
    3834#define PRIORITY_DEFAULT 127
    3935
    40 /* cpuif->iccicr */
    41 #define ICC_CTLR    "p15, 0, %0, c12, c12, 4"
    42 
    43 /* cpuif->iccpmr */
    44 #define ICC_PMR     "p15, 0, %0,  c4,  c6, 0"
    45 
    46 /* cpuif->iccbpr */
    47 #define ICC_BPR0    "p15, 0, %0, c12,  c8, 3"
    48 #define ICC_BPR1    "p15, 0, %0, c12, c12, 3"
    49 
    50 /* cpuif->icciar */
    51 #define ICC_IAR0    "p15, 0, %0, c12,  c8, 0"
    52 #define ICC_IAR1    "p15, 0, %0, c12, c12, 0"
    53 
    54 /* cpuif->icceoir */
    55 #define ICC_EOIR0   "p15, 0, %0, c12,  c8, 1"
    56 #define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
    57 
    58 #define ICC_SRE     "p15, 0, %0, c12, c12, 5"
    59 
    60 #define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
    61 #define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
    62 
    63 #define ICC_SGI1    "p15, 0, %Q0, %R0, c12"
     36#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
     37#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
     38#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
     39#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
     40#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
     41#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
     42#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
     43#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
     44#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
    6445
    6546#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
     
    8061#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
    8162
     63#ifdef ARM_MULTILIB_ARCH_V4
     64/* cpuif->iccicr */
     65#define ICC_CTLR    "p15, 0, %0, c12, c12, 4"
     66
     67/* cpuif->iccpmr */
     68#define ICC_PMR     "p15, 0, %0,  c4,  c6, 0"
     69
     70/* cpuif->iccbpr */
     71#define ICC_BPR0    "p15, 0, %0, c12,  c8, 3"
     72#define ICC_BPR1    "p15, 0, %0, c12, c12, 3"
     73
     74/* cpuif->icciar */
     75#define ICC_IAR0    "p15, 0, %0, c12,  c8, 0"
     76#define ICC_IAR1    "p15, 0, %0, c12, c12, 0"
     77
     78/* cpuif->icceoir */
     79#define ICC_EOIR0   "p15, 0, %0, c12,  c8, 1"
     80#define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
     81
     82#define ICC_SRE     "p15, 0, %0, c12, c12, 5"
     83
     84#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
     85#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
     86
    8287#define MPIDR       "p15, 0, %0, c0, c0, 5"
    83 
    84 #define MPIDR_AFFINITY3(val) BSP_FLD64(val, 25, 29)
    85 #define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 25, 29)
    86 #define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 25, 29)
    87 #define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
    88 #define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
    89 #define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
    90 #define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
    91 #define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
    92 #define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
    93 #define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
    94 #define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
    95 #define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
    9688
    9789#define READ_SR(SR_NAME) \
     
    10597    __asm__ volatile("mcr    " SR_NAME "  \n" : : "r" (VALUE) );
    10698
     99#define ICC_SGI1    "p15, 0, %Q0, %R0, c12"
    107100#define WRITE64_SR(SR_NAME, VALUE) \
    108101    __asm__ volatile("mcrr    " SR_NAME "  \n" : : "r" (VALUE) );
    109102
     103#else /* ARM_MULTILIB_ARCH_V4 */
     104
     105/* AArch64 GICv3 registers are not named in GCC */
     106#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
     107#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
     108#define ICC_PMR     "S3_0_C4_C6_0, %0"
     109#define ICC_EOIR1   "S3_0_C12_C12_1, %0"
     110#define ICC_SRE     "S3_0_C12_C12_5, %0"
     111#define ICC_BPR0    "S3_0_C12_C8_3, %0"
     112#define ICC_CTLR    "S3_0_C12_C12_4, %0"
     113#define ICC_IAR1    "%0, S3_0_C12_C12_0"
     114#define MPIDR       "%0, mpidr_el1"
     115#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
     116#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
     117#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
     118
     119#define ICC_SGI1    "S3_0_C12_C11_5, %0"
     120#define WRITE64_SR(SR_NAME, VALUE) \
     121    __asm__ volatile("msr    " SR_NAME "  \n" : : "r" (VALUE) );
     122#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
     123
     124#define READ_SR(SR_NAME) \
     125({ \
     126  uint64_t value; \
     127  __asm__ volatile("mrs    " SR_NAME : "=&r" (value) ); \
     128  value; \
     129})
     130
     131
     132#endif /* ARM_MULTILIB_ARCH_V4 */
     133
    110134#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
    111135#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16))))
    112136
    113 void bsp_interrupt_dispatch(void)
     137void gicv3_interrupt_dispatch(void)
    114138{
    115139  uint32_t icciar = READ_SR(ICC_IAR1);
     
    118142
    119143  if (vector != spurious) {
    120     uint32_t psr = _ARMV4_Status_irq_enable();
    121     bsp_interrupt_handler_dispatch(vector);
    122 
    123     _ARMV4_Status_restore(psr);
     144    arm_interrupt_handler_dispatch(vector);
    124145
    125146    WRITE_SR(ICC_EOIR1, icciar);
     
    200221  uint32_t id;
    201222
    202   arm_cp15_set_exception_handler(
    203     ARM_EXCEPTION_IRQ,
    204     _ARMV4_Exception_interrupt
    205   );
     223  arm_interrupt_facility_set_exception_handler();
    206224
    207225  dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S
     
    320338   * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
    321339   * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF */
    322   uint32_t mpidr = READ_SR(MPIDR);
    323   uint64_t value = ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr))
    324                  | ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
     340#ifndef ARM_MULTILIB_ARCH_V4
     341  uint64_t mpidr;
     342#else
     343  uint32_t mpidr;
     344#endif
     345  mpidr = READ_SR(MPIDR);
     346  uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
    325347                 | ICC_SGIR_INTID(vector)
    326348                 | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
    327349                 | ICC_SGIR_CPU_TARGET_LIST(1);
     350#ifndef ARM_MULTILIB_ARCH_V4
     351  value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
     352#endif
    328353  WRITE64_SR(ICC_SGI1, value);
    329354}
  • spec/build/bsps/arm/grp.yml

    r1480c3f rf8ad5bb2  
    2323  - bsps/arm/include/bsp/arm-cp15-start.h
    2424  - bsps/arm/include/bsp/arm-errata.h
    25   - bsps/arm/include/bsp/arm-gic-irq.h
    26   - bsps/arm/include/bsp/arm-gic-regs.h
    27   - bsps/arm/include/bsp/arm-gic-tm27.h
    28   - bsps/arm/include/bsp/arm-gic.h
    2925  - bsps/arm/include/bsp/arm-pl050-regs.h
    3026  - bsps/arm/include/bsp/arm-pl050.h
     
    4339  - bsps/arm/include/bsp/zynq-uart-regs.h
    4440  - bsps/arm/include/bsp/zynq-uart.h
     41- destination: ${BSP_INCLUDEDIR}/dev/irq
     42  source:
     43  - bsps/include/dev/irq/arm-gic-irq.h
     44  - bsps/include/dev/irq/arm-gic-regs.h
     45  - bsps/include/dev/irq/arm-gic-tm27.h
     46  - bsps/include/dev/irq/arm-gic.h
    4547- destination: ${BSP_INCLUDEDIR}/libcpu
    4648  source:
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