Changeset f8a5d54e in rtems


Ignore:
Timestamp:
Jul 18, 1998, 5:46:33 PM (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
a4d34dd2
Parents:
c53e1df4
Message:

Addresses for SCC were wrong. A and B ports were swapped.

Deleted CSS interface related items.

Added items required to access DMA Control and Status Register so we
could figure out dynamically what the clock speed of the SCC really is.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h

    rc53e1df4 rf8a5d54e  
    5353
    5454/* base address for the SCC (85C30) */
    55 #define Z85C30_ADDR       0xfb000000
    56 #define Z85C30_CTRL_A     0xfb000000
    57 #define Z85C30_DATA_A     0xfb000008
    58 #define Z85C30_CTRL_B     0xfb000010
    59 #define Z85C30_DATA_B     0xfb000018
    60 #define Z85C30_CLOCK      (8 * 1024 * 1024)
     55#define Z85C30_ADDR       0xfb000010
     56#define Z85C30_CTRL_A     0xfb000010
     57#define Z85C30_DATA_A     0xfb000018
     58#define Z85C30_CTRL_B     0xfb000000
     59#define Z85C30_DATA_B     0xfb000008
     60#define Z85C30_CLOCK_10   (10485760)      /* 10 Mhz */
     61#define Z85C30_CLOCK_2    (2581175)       /* 2.4616 Mhz */
    6162
    6263/* base address for the SCV64 */
     
    7576#define DMV170_READ( _reg, _data ) \
    7677   (_data) = *((volatile rtems_unsigned16 *)(_reg))
     78
     79/*
     80 *  The following defines the bits in the DMA Control and Status Register
     81 */
     82
     83/* XXX fill in the other bits */
     84
     85#define DMV170_DMA_CONTROL_STATUS_REG                     0xfc000090
     86
     87#define DMV170_SCC_10MHZ                                  0x00010000
    7788
    7889/*
     
    122133 *  The following defines the bits in the Timer Control Register.
    123134 */
     135
    124136#define DMV170_TIMER0_ENABLE_MASK                         0x0001
    125137#define DMV170_TIMER0_IS_ENABLED                          0x0001
     
    148160#define DMV170_TIMER2_INTERRUPT_CLEAR                     0x0000
    149161
    150 
    151 
    152 /* The Following definethe bits for the Card Resource Register      */
     162/*
     163 *  The Following define the bits for the Card Resource Register.
     164 */
     165
    153166#define DMV170_DUART_INTERRUPT_MASK    0x0001  /* DUART Interrupt Sense Bit  */
    154167#define DMV170_DUART_INTERRUPT_NEGATE  0x0001
     
    197210
    198211/*
    199  * DUART Baud Rate Definations.
    200  */
     212 * DUART Baud Rate Definitions.
     213 */
     214
    201215#define DMV170_DUART_9621     MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ 
    202216
     
    209223 *       Local Control and Status Register.
    210224 */
     225
    211226#define DMV170_IRQ_FIRST                       ( PPC_IRQ_LAST +  1 )
    212227
     
    240255#define DMV170_PERIPHERAL_IRQ                  ( DMV170_IRQ_FIRST + 12)
    241256
     257#define MAX_BOARD_IRQS                         DMV170_PERIPHERAL_IRQ
    242258
    243259#define SCV64_Is_IRQ0( _status ) (_status&0x01)
     
    256272rtems_unsigned32 SCV64_Get_Interrupt_Enable();
    257273
    258 /*
    259  *  css_iface.c
    260  */
    261 
    262 void Init_Css();
    263 
    264 rtems_unsigned32 Css_Id(
    265   rtems_vector_number vector        /* vector number      */
    266 );
    267 
    268 rtems_vector_number Vector_id(
    269   rtems_unsigned32 id
    270 );
    271 
    272 void enable_card_interrupt(
    273   rtems_vector_number vector        /* vector number      */
    274 );
    275 
    276 rtems_vector_number Get_interrupt();
    277 
    278 void Clear_interrupt(
    279   rtems_vector_number vector
    280 );
    281 
    282 
    283 #define MAX_BOARD_IRQS                         DMV170_PERIPHERAL_IRQ
    284274#ifdef __cplusplus
    285275}
     
    289279/* end of include file */
    290280
    291 
    292 
    293 
    294 
    295 
    296 
    297 
    298 
    299 
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