Changeset f7f420e in rtems


Ignore:
Timestamp:
Sep 6, 2017, 5:42:06 AM (23 months ago)
Author:
Christian Mauderer <Christian.Mauderer@…>
Branches:
master
Children:
4e0ba7e
Parents:
bdbf1ffa
git-author:
Christian Mauderer <Christian.Mauderer@…> (09/06/17 05:42:06)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/07/17 07:26:05)
Message:

bsp/atsam: Fix MPU sections.

The nocache section has been hard coded which could lead to problems
when a bigger region should be used. Fix that.

The internal SRAM has not been set up correctly. A duplicate external
SDRAM has been set up instead.

Remove a lot of other hard coded sections too.

Location:
c/src/lib/libbsp/arm/atsam
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c

    rbdbf1ffa rf7f420e  
    9393            END_Addr:-    0x003FFFFFUL
    9494        ****************************************************/
     95
    9596        dwRegionBaseAddr =
    9697                ITCM_START_ADDRESS |
     
    9899                MPU_DEFAULT_ITCM_REGION;        // 1
    99100
     101#ifdef __rtems__
     102        if (ITCM_END_ADDRESS + 1 != ITCM_START_ADDRESS) {
     103#endif /* __rtems__ */
    100104        dwRegionAttr =
    101105                MPU_AP_PRIVILEGED_READ_WRITE |
    102106                MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
    103107                MPU_REGION_ENABLE;
    104 
    105         MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     108#ifdef __rtems__
     109        } else {
     110                dwRegionAttr = MPU_REGION_DISABLE;
     111        }
     112#endif /* __rtems__ */
     113
     114        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     115
    106116
    107117        /****************************************************
     
    137147                MPU_DEFAULT_DTCM_REGION;         //3
    138148
     149#ifdef __rtems__
     150        if (DTCM_END_ADDRESS + 1 != DTCM_START_ADDRESS) {
     151#endif /* __rtems__ */
    139152        dwRegionAttr =
    140153                MPU_AP_PRIVILEGED_READ_WRITE |
     
    142155                MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
    143156                MPU_REGION_ENABLE;
    144 
    145         MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     157#ifdef __rtems__
     158        } else {
     159                dwRegionAttr = MPU_REGION_DISABLE;
     160        }
     161#endif /* __rtems__ */
     162
     163        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     164
    146165
    147166        /****************************************************
     
    184203
    185204        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     205#else /* __rtems__ */
     206        /* NOTE: The first SRAM region is increased so it covers the whole SRAM. If
     207         * the SRAM is something odd (like 384k on the SAME70Q21), the next higher
     208         * power of two will be used (in the example: 512k). That removes the need of
     209         * the second SRAM region. There is currently no memory after the SRAM so that
     210         * shouldn't be a problem. */
    186211#endif /* __rtems__ */
    187212
     
    219244        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
    220245
     246#ifdef __rtems__
     247        dwRegionBaseAddr =
     248                SYSTEM_START_ADDRESS |
     249                MPU_REGION_VALID |
     250                MPU_SYSTEM_REGION;
     251
     252        dwRegionAttr = MPU_AP_FULL_ACCESS |
     253                                   MPU_REGION_EXECUTE_NEVER |
     254                                   SHAREABLE_DEVICE_TYPE |
     255                                   MPU_CalMPURegionSize(SYSTEM_END_ADDRESS - SYSTEM_START_ADDRESS)
     256                                   | MPU_REGION_ENABLE;
     257
     258        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     259#endif /* __rtems__ */
    221260
    222261        /****************************************************
     
    268307                MPU_QSPIMEM_REGION;              //8
    269308
     309#ifdef __rtems__
     310        if (QSPI_END_ADDRESS + 1 != QSPI_START_ADDRESS) {
     311#endif /* __rtems__ */
    270312        dwRegionAttr =
    271313                MPU_AP_FULL_ACCESS |
     
    273315                MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
    274316                MPU_REGION_ENABLE;
     317#ifdef __rtems__
     318        } else {
     319                dwRegionAttr = MPU_REGION_DISABLE;
     320        }
     321#endif /* __rtems__ */
    275322
    276323        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
     
    302349
    303350        /* Enable the MPU region */
     351#ifndef __rtems__
    304352        MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
     353#else /* __rtems__ */
     354        MPU_Enable(MPU_ENABLE);
     355#endif /* __rtems__ */
    305356
    306357        memory_sync();
  • c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h

    rbdbf1ffa rf7f420e  
    5555        #define MPU_NOCACHE_SRAM_REGION                 (11)
    5656#endif
     57#define MPU_SYSTEM_REGION                       (12)
    5758
    5859#define MPU_REGION_VALID                        (0x10)
     
    102103
    103104/********* IFLASH memory macros *********************/
     105#ifdef __rtems__
     106#define ITCM_START_ADDRESS                  ((uintptr_t) atsam_memory_itcm_begin)
     107#define ITCM_END_ADDRESS                    ((uintptr_t) atsam_memory_itcm_end - 1)
     108#define IFLASH_START_ADDRESS                ((uintptr_t) atsam_memory_intflash_begin)
     109#define IFLASH_END_ADDRESS                  ((uintptr_t) atsam_memory_intflash_end - 1)
     110#else /* !__rtems__ */
    104111#define ITCM_START_ADDRESS                  0x00000000UL
    105112#define ITCM_END_ADDRESS                    0x003FFFFFUL
    106113#define IFLASH_START_ADDRESS                0x00400000UL
    107114#define IFLASH_END_ADDRESS                  0x005FFFFFUL
     115#endif /* __rtems__ */
    108116
    109117
     
    115123
    116124/**************** DTCM  *******************************/
     125#ifdef __rtems__
     126#define DTCM_START_ADDRESS                  ((uintptr_t) atsam_memory_dtcm_begin)
     127#define DTCM_END_ADDRESS                    ((uintptr_t) atsam_memory_dtcm_end - 1)
     128#else /* !__rtems__ */
    117129#define DTCM_START_ADDRESS                  0x20000000UL
    118130#define DTCM_END_ADDRESS                    0x203FFFFFUL
     131#endif /* __rtems__ */
    119132
    120133
    121134/******* SRAM memory macros ***************************/
    122135
     136#ifdef __rtems__
     137#define SRAM_START_ADDRESS                  ((uintptr_t) atsam_memory_intsram_begin)
     138#define SRAM_END_ADDRESS                    ((uintptr_t) atsam_memory_intsram_end - 1)
     139#else /* !__rtems__ */
    123140#define SRAM_START_ADDRESS                  0x20400000UL
    124141#define SRAM_END_ADDRESS                    0x2045FFFFUL
    125 
     142#endif /* __rtems__ */
     143
     144#ifndef __rtems__
    126145#if defined MPU_HAS_NOCACHE_REGION
    127146        #define NOCACHE_SRAM_REGION_SIZE            0x1000
    128147#endif
     148#endif /* __rtems__ */
    129149
    130150/* Regions should be a 2^(N+1)  where 4 < N < 31 */
    131151#ifdef __rtems__
    132 #define SRAM_FIRST_START_ADDRESS            ((uintptr_t) atsam_memory_sdram_begin)
    133 #define SRAM_FIRST_END_ADDRESS              ((uintptr_t) atsam_memory_sdram_end - 1)
    134 #else /* __rtems__ */
     152#define SRAM_FIRST_START_ADDRESS            ((uintptr_t) atsam_memory_intsram_begin)
     153#define SRAM_FIRST_END_ADDRESS              ((uintptr_t) atsam_memory_intsram_end - 1)
     154#else /* !__rtems__ */
    135155#define SRAM_FIRST_START_ADDRESS            (SRAM_START_ADDRESS)
    136156#define SRAM_FIRST_END_ADDRESS              (SRAM_FIRST_START_ADDRESS + 0x3FFFF)        // (2^18) 256 KB
     
    141161        #define SRAM_NOCACHE_START_ADDRESS          ((uintptr_t) atsam_memory_nocache_begin)
    142162        #define SRAM_NOCACHE_END_ADDRESS            ((uintptr_t) atsam_memory_nocache_end - 1)
    143 #else /* __rtems__ */
     163        #define NOCACHE_SRAM_REGION_SIZE            (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
     164#else /* !__rtems__ */
    144165        #define SRAM_SECOND_START_ADDRESS           (SRAM_FIRST_END_ADDRESS+1)
    145166        #define SRAM_SECOND_END_ADDRESS             (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE)              // (2^17) 128 - 0x1000 KB
     
    156177#define PERIPHERALS_START_ADDRESS            0x40000000UL
    157178#define PERIPHERALS_END_ADDRESS              0x5FFFFFFFUL
     179#ifdef __rtems__
     180#define SYSTEM_START_ADDRESS                 0xE0000000UL
     181#define SYSTEM_END_ADDRESS                   0xFFFFFFFFUL
     182#endif /* __rtems__ */
    158183
    159184/******* Ext EBI memory macros ***************************/
     
    162187
    163188/******* Ext-SRAM memory macros ***************************/
     189#ifdef __rtems__
     190#define SDRAM_START_ADDRESS                  ((uintptr_t) atsam_memory_sdram_begin)
     191#define SDRAM_END_ADDRESS                    ((uintptr_t) atsam_memory_sdram_end - 1)
     192#else /* !__rtems__ */
    164193#define SDRAM_START_ADDRESS                  0x70000000UL
    165194#define SDRAM_END_ADDRESS                    0x7FFFFFFFUL
     195#endif /* __rtems__ */
    166196
    167197/******* QSPI macros ***************************/
     198#ifdef __rtems__
     199#define QSPI_START_ADDRESS                   ((uintptr_t) atsam_memory_qspiflash_begin)
     200#define QSPI_END_ADDRESS                     ((uintptr_t) atsam_memory_qspiflash_end - 1)
     201#else /* !__rtems__ */
    168202#define QSPI_START_ADDRESS                   0x80000000UL
    169203#define QSPI_END_ADDRESS                     0x9FFFFFFFUL
     204#endif /* __rtems__ */
    170205
    171206/************** USBHS_RAM region macros ******************/
  • c/src/lib/libbsp/arm/atsam/startup/linkcmds.memory.in

    rbdbf1ffa rf7f420e  
    88        QSPIFLASH  : ORIGIN = 0x80000000, LENGTH = @ATSAM_MEMORY_QSPIFLASH_SIZE@
    99}
     10
     11/* Must be used only for MPU definitions */
    1012
    1113atsam_memory_itcm_begin = ORIGIN (ITCM);
Note: See TracChangeset for help on using the changeset viewer.