Timestamp:
Jul 31, 2013, 7:45:59 AM (7 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, 5, master
Children:
0b03ca39
Parents:
4953b724
git-author:
Ralf Kirchner <ralf.kirchner@…> (07/31/13 07:45:59)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/13/14 15:22:00)
Message:

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
File:
1 added

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