Changeset f715433 in rtems


Ignore:
Timestamp:
Feb 4, 2014, 3:44:50 PM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
5ff6a9ca
Parents:
a54179d2
git-author:
Sebastian Huber <sebastian.huber@…> (02/04/14 15:44:50)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/04/14 15:57:58)
Message:

bsps/sparc: Order load/store by increasing offsets

This may increase the cache hit performance.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    ra54179d2 rf715433  
    423423        GET_SELF_CPU_CONTROL %l5, %l7
    424424
    425         ld       [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
    426         ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
     425        ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
     426        ld       [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
     427
     428        add      %l7, 1, %l7
     429        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    427430
    428431        add      %l6, 1, %l6
    429432        st       %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
    430 
    431         add      %l7, 1, %l7
    432         st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    433433
    434434        /*
     
    582582         */
    583583
     584        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
     585
    584586        sub      %l6, 1, %l6
    585587        st       %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
    586 
    587         st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    588588
    589589        /*
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