Changeset f70598c7 in rtems
- Timestamp:
- 10/26/99 01:34:42 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 99826740
- Parents:
- 3a0a97a
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/i386/i386ex/start/start.S
r3a0a97a rf70598c7 36 36 */ 37 37 38 38 39 #include "asm.h" 39 40 #include "macros.inc" 40 41 #include "80386ex.inc" 41 42 43 42 44 /* 43 45 * NEW_GAS Needed for binutils 2.9.1.0.7 and higher … … 50 52 PUBLIC (Interrupt_descriptor_table) 51 53 PUBLIC ( SYM(IDTR) ) 52 PUBLIC( SYM(_initInternalRegisters) ) 54 /* PUBLIC( SYM(_initInternalRegisters) ) */ 53 55 54 56 BEGIN_DATA … … 81 83 */ 82 84 83 85 .code16 84 86 .section .reset 85 86 87 PUBLIC ( SYM(reset) ) 87 SYM(reset): 88 SYM(reset): 88 89 nop 89 90 cli 90 91 jmp SYM(_initInternalRegisters) /* different section in this file */ 91 .code32 /*in case this section moves */92 /* .code32 in case this section moves */ 92 93 nop /* required by CHIP LAB to pad out size */ 93 94 nop … … 95 96 nop 96 97 nop 97 98 98 nop 99 nop 100 nop 101 nop 102 nop 103 nop 99 104 100 105 .section .initial 101 nop /* nops required to correct 32 bit jmp relative */ 102 nop /* offset from .reset section */ 103 106 /* nop */ /* required for linker -- initial jump is to "label - 2" */ 107 /* nop */ /* ie. _initInternalRegisters -2 ( which now == .initial ) */ 104 108 /* 105 109 * Enable access to peripheral register at expanded I/O addresses 106 110 */ 107 111 SYM(_initInternalRegisters): 108 .code16 112 113 /* .code16 */ 109 114 movw $0x8000 , ax 110 115 outb al , $REMAPCFGH … … 112 117 outb al,$REMAPCFGL 113 118 outw ax, $REMAPCFG ; 114 115 116 119 /* 117 120 * Configure operation of the A20 Address Line … … 124 127 orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. 125 128 outb al , dx 129 126 130 127 131 SYM(Watchdog): … … 243 247 244 248 SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 245 SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200249 SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud, 0x28=19.2k, 0x7 -> 115.2k 246 250 SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud 247 251 SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible … … 311 315 312 316 cli # ! 313 317 /* SetExRegByte(OCW3S, 0x20) # address the Slave status port 318 movw $OCW3S , dx 319 inb dx , al # Read the IRR. 320 321 SetExRegByte(OCW3M, 0x20) # address the Master status port 322 movw $OCW3M , dx 323 inb dx , al # Read the IRR. 324 */ 325 314 326 SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED 315 327 SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master … … 320 332 SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 321 333 SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally 322 SetExRegByte(ICW4M , 0x01 ) # idem 323 324 SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde 334 SetExRegByte(ICW4M , 0x01 ) # fully nested mode 335 336 SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. 337 # for IR5 and IR0 active use 0xde 338 # for IR0 and IR2 use 0xfa 325 339 SetExRegByte(INTCFG , 0x00 ) 326 340 327 /*328 * The addr32 override should ensure that the address for329 * i8259s_cache is put in 32-bit address space.330 */331 332 #if defined(NEW_GAS)333 addr32 movw $0xFFFB, SYM(i8259s_cache) # set up same values in cache334 #else335 movw $0xFFFB, SYM(i8259s_cache) # set up same values in cache336 #endif337 341 338 342 SYM(SetCS4): … … 352 356 * So, move the whole data section down. 353 357 ********************************************************/ 354 358 355 359 movw $ _ram_data_offset , di 356 360 movw $ _ram_data_segment, cx … … 382 386 SetExRegWord(UCSMSKH, 0x0007) 383 387 SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select 384 388 389 /* 390 * SRAM chip select: 16 bit bus size,starting 16Mb, size 512k, 391 * 4 waits 392 */ 393 394 #ifdef UT_I386EX 395 396 SYM(SetCS1): 397 SetExRegWord(CS1ADL, 0x0000) 398 SetExRegWord(CS1ADH, 0x000E) 399 SetExRegWord(CS1MSKH, 0x0000) 400 SetExRegWord(CS1MSKL, 0x0001) 401 402 SYM(SetCS2): 403 SetExRegWord(CS2ADL, 0x0704) 404 SetExRegWord(CS2ADH, 0x0100) 405 SetExRegWord(CS2MSKH, 0x0003) 406 SetExRegWord(CS2MSKL, 0xfc01) 407 408 /* 409 * Real-time clock: 8 bit bus size, starting@16Mb+512K, size 32k 410 * 4 waits 411 */ 412 SYM(SetCS3): 413 SetExRegWord(CS3ADL, 0x0504) 414 SetExRegWord(CS3ADH, 0x0108) 415 SetExRegWord(CS3MSKH, 0x0000) 416 SetExRegWord(CS3MSKL, 0x7c01) 417 418 #endif 385 419 /*************************** 386 420 * Switch to Protected Mode 387 421 ***************************/ 422 388 423 mov cr0, eax 389 424 orw $0x1, ax … … 419 454 movl $stack_origin, esp # this is the high starting address 420 455 movl $stack_origin, ebp 456 421 457 /* 422 458 * Zero out the BSS segment … … 433 469 stosl # clear a long in the bss 434 470 471 435 472 /* 436 473 * Transfer control to User's Board Support Package … … 439 476 pushl $0 # argv 440 477 pushl $0 # argc 478 479 movw $0xFFFB, SYM(i8259s_cache) # ICU mask values reflect 480 # initial ICU state 441 481 call SYM(boot_card) 442 482 addl $12,esp
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