Ignore:
Timestamp:
May 19, 2011, 12:09:04 PM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
76134c5
Parents:
00d95ce0
Message:

2011-05-19 Sebastian Huber <sebastian.huber@…>

  • shared/lpc/include/lpc-emc.h, shared/lpc/include/lpc-lcd.h: New files.
  • shared/lpc/include/lpc-dma.h: API changes.
  • shared/lpc/clock/lpc-clock-config.c: Fixed nano seconds extension.
  • shared/lpc/network/lpc-ethernet.c: Format. Multicast hash filter support.
Location:
c/src/lib/libbsp/arm/shared/lpc/include
Files:
2 added
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h

    r00d95ce0 rf6083f0  
    44 * @ingroup lpc_dma
    55 *
    6  * @brief DMA API.
     6 * @brief DMA support API.
    77 */
    88
    99/*
    10  * Copyright (c) 2010
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    2324#define LIBBSP_ARM_SHARED_LPC_DMA_H
    2425
    25 #include <stdint.h>
     26#include <bsp/utility.h>
    2627
    2728#ifdef __cplusplus
     
    3233 * @defgroup lpc_dma DMA Support
    3334 *
    34  * @ingroup lpc
     35 * @ingroup lpc24xx
     36 * @ingroup lpc32xx
    3537 *
    3638 * @brief DMA support.
     
    8183
    8284/**
    83  * @name DMA Configuration Register Defines
    84  *
    85  * @{
    86  */
    87 
    88 #define LPC_DMA_CFG_EN (1U << 0)
    89 #define LPC_DMA_CFG_M_0 (1U << 1)
    90 #define LPC_DMA_CFG_M_1 (1U << 2)
    91 
    92 /** @} */
    93 
    94 /**
    95  * @name DMA Channel Control Register Defines
    96  *
    97  * @{
    98  */
    99 
    100 #define LPC_DMA_CH_CTRL_TSZ_MASK 0xfffU
    101 #define LPC_DMA_CH_CTRL_TSZ_MAX 0xfffU
    102 
    103 #define LPC_DMA_CH_CTRL_SB_MASK (0x7U << 12)
    104 #define LPC_DMA_CH_CTRL_SB_1 (0x0U << 12)
    105 #define LPC_DMA_CH_CTRL_SB_4 (0x1U << 12)
    106 #define LPC_DMA_CH_CTRL_SB_8 (0x2U << 12)
    107 #define LPC_DMA_CH_CTRL_SB_16 (0x3U << 12)
    108 #define LPC_DMA_CH_CTRL_SB_32 (0x4U << 12)
    109 #define LPC_DMA_CH_CTRL_SB_64 (0x5U << 12)
    110 #define LPC_DMA_CH_CTRL_SB_128 (0x6U << 12)
    111 #define LPC_DMA_CH_CTRL_SB_256 (0x7U << 12)
    112 
    113 #define LPC_DMA_CH_CTRL_DB_MASK (0x7U << 15)
    114 #define LPC_DMA_CH_CTRL_DB_1 (0x0U << 15)
    115 #define LPC_DMA_CH_CTRL_DB_4 (0x1U << 15)
    116 #define LPC_DMA_CH_CTRL_DB_8 (0x2U << 15)
    117 #define LPC_DMA_CH_CTRL_DB_16 (0x3U << 15)
    118 #define LPC_DMA_CH_CTRL_DB_32 (0x4U << 15)
    119 #define LPC_DMA_CH_CTRL_DB_64 (0x5U << 15)
    120 #define LPC_DMA_CH_CTRL_DB_128 (0x6U << 15)
    121 #define LPC_DMA_CH_CTRL_DB_256 (0x7U << 15)
    122 
    123 #define LPC_DMA_CH_CTRL_SW_MASK (0x7U << 18)
    124 #define LPC_DMA_CH_CTRL_SW_8 (0x0U << 18)
    125 #define LPC_DMA_CH_CTRL_SW_16 (0x1U << 18)
    126 #define LPC_DMA_CH_CTRL_SW_32 (0x2U << 18)
    127 
    128 #define LPC_DMA_CH_CTRL_DW_MASK (0x7U << 21)
    129 #define LPC_DMA_CH_CTRL_DW_8 (0x0U << 21)
    130 #define LPC_DMA_CH_CTRL_DW_16 (0x1U << 21)
    131 #define LPC_DMA_CH_CTRL_DW_32 (0x2U << 21)
    132 
    133 #define LPC_DMA_CH_CTRL_SM_0 (0U << 24)
    134 #define LPC_DMA_CH_CTRL_SM_1 (1U << 24)
    135 
    136 #define LPC_DMA_CH_CTRL_DM_0 (0U << 25)
    137 #define LPC_DMA_CH_CTRL_DM_1 (1U << 25)
    138 
    139 #define LPC_DMA_CH_CTRL_SI (1U << 26)
    140 #define LPC_DMA_CH_CTRL_DI (1U << 27)
    141 #define LPC_DMA_CH_CTRL_ITC (1U << 31)
    142 
    143 /** @} */
    144 
    145 /**
    146  * @name DMA Channel Configuration Register Defines
    147  *
    148  * @{
    149  */
    150 
    151 #define LPC_DMA_CH_CFG_EN (1U << 0)
    152 
    153 #define LPC_DMA_CH_CFG_SPER_MASK (0xfU << 1)
    154 #define LPC_DMA_CH_CFG_SPER_SHIFT 1
    155 #define LPC_DMA_CH_CFG_SPER_0 (0x0U << 1)
    156 #define LPC_DMA_CH_CFG_SPER_1 (0x1U << 1)
    157 #define LPC_DMA_CH_CFG_SPER_2 (0x2U << 1)
    158 #define LPC_DMA_CH_CFG_SPER_3 (0x3U << 1)
    159 #define LPC_DMA_CH_CFG_SPER_4 (0x4U << 1)
    160 #define LPC_DMA_CH_CFG_SPER_5 (0x5U << 1)
    161 #define LPC_DMA_CH_CFG_SPER_6 (0x6U << 1)
    162 #define LPC_DMA_CH_CFG_SPER_7 (0x7U << 1)
    163 #define LPC_DMA_CH_CFG_SPER_8 (0x8U << 1)
    164 #define LPC_DMA_CH_CFG_SPER_9 (0x9U << 1)
    165 #define LPC_DMA_CH_CFG_SPER_10 (0xaU << 1)
    166 #define LPC_DMA_CH_CFG_SPER_11 (0xbU << 1)
    167 #define LPC_DMA_CH_CFG_SPER_12 (0xcU << 1)
    168 #define LPC_DMA_CH_CFG_SPER_13 (0xdU << 1)
    169 #define LPC_DMA_CH_CFG_SPER_14 (0xeU << 1)
    170 #define LPC_DMA_CH_CFG_SPER_15 (0xfU << 1)
    171 
    172 #define LPC_DMA_CH_CFG_DPER_MASK (0xfU << 6)
    173 #define LPC_DMA_CH_CFG_DPER_SHIFT 6
    174 #define LPC_DMA_CH_CFG_DPER_0 (0x0U << 6)
    175 #define LPC_DMA_CH_CFG_DPER_1 (0x1U << 6)
    176 #define LPC_DMA_CH_CFG_DPER_2 (0x2U << 6)
    177 #define LPC_DMA_CH_CFG_DPER_3 (0x3U << 6)
    178 #define LPC_DMA_CH_CFG_DPER_4 (0x4U << 6)
    179 #define LPC_DMA_CH_CFG_DPER_5 (0x5U << 6)
    180 #define LPC_DMA_CH_CFG_DPER_6 (0x6U << 6)
    181 #define LPC_DMA_CH_CFG_DPER_7 (0x7U << 6)
    182 #define LPC_DMA_CH_CFG_DPER_8 (0x8U << 6)
    183 #define LPC_DMA_CH_CFG_DPER_9 (0x9U << 6)
    184 #define LPC_DMA_CH_CFG_DPER_10 (0xaU << 6)
    185 #define LPC_DMA_CH_CFG_DPER_11 (0xbU << 6)
    186 #define LPC_DMA_CH_CFG_DPER_12 (0xcU << 6)
    187 #define LPC_DMA_CH_CFG_DPER_13 (0xdU << 6)
    188 #define LPC_DMA_CH_CFG_DPER_14 (0xeU << 6)
    189 #define LPC_DMA_CH_CFG_DPER_15 (0xfU << 6)
    190 
    191 #define LPC_DMA_CH_CFG_FLOW_MASK (0x7U << 11)
    192 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA (0x0U << 11)
    193 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_DMA (0x1U << 11)
    194 #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_DMA (0x2U << 11)
    195 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DMA (0x3U << 11)
    196 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DEST (0x4U << 11)
    197 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_PER (0x5U << 11)
    198 #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_PER (0x6U << 11)
    199 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_SRC (0x7U << 11)
    200 
    201 #define LPC_DMA_CH_CFG_IE (1U << 14)
    202 #define LPC_DMA_CH_CFG_ITC (1U << 15)
    203 #define LPC_DMA_CH_CFG_LOCK (1U << 16)
    204 #define LPC_DMA_CH_CFG_ACTIVE (1U << 17)
    205 #define LPC_DMA_CH_CFG_HALT (1U << 18)
     85 * @name DMA Configuration Register
     86 *
     87 * @{
     88 */
     89
     90#define DMA_CFG_E BSP_BIT32(0)
     91#define DMA_CFG_M_0 BSP_BIT32(1)
     92#define DMA_CFG_M_1 BSP_BIT32(2)
     93
     94/** @} */
     95
     96/**
     97 * @name DMA Channel Control Register
     98 *
     99 * @{
     100 */
     101
     102#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
     103#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
     104
     105#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
     106#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
     107#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
     108#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
     109#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
     110#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
     111#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
     112#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
     113#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
     114
     115#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
     116#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
     117#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
     118#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
     119#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
     120#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
     121#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
     122#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
     123#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
     124
     125#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
     126#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
     127#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
     128#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
     129
     130#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
     131#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
     132#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
     133#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
     134
     135#define DMA_CH_CTRL_S BSP_BIT32(24)
     136#define DMA_CH_CTRL_D BSP_BIT32(25)
     137#define DMA_CH_CTRL_SI BSP_BIT32(26)
     138#define DMA_CH_CTRL_DI BSP_BIT32(27)
     139#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
     140#define DMA_CH_CTRL_I BSP_BIT32(31)
     141
     142/** @} */
     143
     144/**
     145 * @name DMA Channel Configuration Register
     146 *
     147 * @{
     148 */
     149
     150#define DMA_CH_CFG_E BSP_BIT32(0)
     151#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
     152#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
     153
     154#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
     155#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
     156#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
     157#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
     158#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
     159#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
     160#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
     161#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
     162#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
     163
     164#define DMA_CH_CFG_IE BSP_BIT32(14)
     165#define DMA_CH_CFG_ITC BSP_BIT32(15)
     166#define DMA_CH_CFG_L BSP_BIT32(16)
     167#define DMA_CH_CFG_A BSP_BIT32(17)
     168#define DMA_CH_CFG_H BSP_BIT32(18)
     169
     170/** @} */
     171
     172/**
     173 * @name LPC24XX DMA Peripherals
     174 *
     175 * @{
     176 */
     177
     178#define LPC24XX_DMA_PER_SSP_0_TX 0
     179#define LPC24XX_DMA_PER_SSP_0_RX 1
     180#define LPC24XX_DMA_PER_SSP_1_TX 2
     181#define LPC24XX_DMA_PER_SSP_1_RX 3
     182#define LPC24XX_DMA_PER_SD_MMC 4
     183#define LPC24XX_DMA_PER_I2S_CH_0 5
     184#define LPC24XX_DMA_PER_I2S_CH_1 6
     185
     186/** @} */
     187
     188/**
     189 * @name LPC32XX DMA Peripherals
     190 *
     191 * @{
     192 */
     193
     194#define LPC32XX_DMA_PER_I2S_0_CH_0 0
     195#define LPC32XX_DMA_PER_I2S_0_CH_1 13
     196#define LPC32XX_DMA_PER_I2S_1_CH_0 2
     197#define LPC32XX_DMA_PER_I2S_1_CH_1 10
     198#define LPC32XX_DMA_PER_NAND_0 1
     199#define LPC32XX_DMA_PER_NAND_1 12
     200#define LPC32XX_DMA_PER_SD_MMC 4
     201#define LPC32XX_DMA_PER_SSP_0_RX 14
     202#define LPC32XX_DMA_PER_SSP_0_TX 15
     203#define LPC32XX_DMA_PER_SSP_1_RX 3
     204#define LPC32XX_DMA_PER_SSP_1_TX 11
     205#define LPC32XX_DMA_PER_UART_1_RX 6
     206#define LPC32XX_DMA_PER_UART_1_TX 5
     207#define LPC32XX_DMA_PER_UART_2_RX 8
     208#define LPC32XX_DMA_PER_UART_2_TX 7
     209#define LPC32XX_DMA_PER_UART_7_RX 10
     210#define LPC32XX_DMA_PER_UART_7_TX 9
    206211
    207212/** @} */
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