- Timestamp:
- 05/19/11 12:09:04 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 76134c5
- Parents:
- 00d95ce0
- Location:
- c/src/lib/libbsp/arm
- Files:
-
- 2 added
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/ChangeLog
r00d95ce0 rf6083f0 1 2011-05-19 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * shared/lpc/include/lpc-emc.h, shared/lpc/include/lpc-lcd.h: New 4 files. 5 * shared/lpc/include/lpc-dma.h: API changes. 6 * shared/lpc/clock/lpc-clock-config.c: Fixed nano seconds extension. 7 * shared/lpc/network/lpc-ethernet.c: Format. Multicast hash filter 8 support. 9 1 10 2011-03-29 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 11 -
c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c
r00d95ce0 rf6083f0 8 8 9 9 /* 10 * Copyright (c) 2009 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * <rtems@embedded-brains.de> 10 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Obere Lagerstr. 30 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be … … 26 27 rtems_isr Clock_isr(rtems_vector_number vector); 27 28 28 static volatile lpc_timer *const lpc_clock = 29 static volatile lpc_timer *const lpc_clock = 29 30 (volatile lpc_timer *) LPC_CLOCK_TIMER_BASE; 30 31 … … 103 104 static uint32_t lpc_clock_nanoseconds_since_last_tick(void) 104 105 { 105 uint64_t clock = LPC_CLOCK_REFERENCE; 106 uint64_t clicks = lpc_clock->tc; 107 uint64_t ns = (clicks * 1000000000) / clock; 106 uint64_t k = (1000000000ULL << 32) / LPC_CLOCK_REFERENCE; 107 uint64_t c = lpc_clock->tc; 108 108 109 return (uint32_t) ns; 109 if ((lpc_clock->ir & LPC_TIMER_IR_MR0) != 0) { 110 c = lpc_clock->tc + lpc_clock->mr0; 111 } 112 113 return (uint32_t) ((c * k) >> 32); 110 114 } 111 115 -
c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h
r00d95ce0 rf6083f0 4 4 * @ingroup lpc_dma 5 5 * 6 * @brief DMA API.6 * @brief DMA support API. 7 7 */ 8 8 9 9 /* 10 * Copyright (c) 2010 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * <rtems@embedded-brains.de> 10 * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Obere Lagerstr. 30 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be … … 23 24 #define LIBBSP_ARM_SHARED_LPC_DMA_H 24 25 25 #include < stdint.h>26 #include <bsp/utility.h> 26 27 27 28 #ifdef __cplusplus … … 32 33 * @defgroup lpc_dma DMA Support 33 34 * 34 * @ingroup lpc 35 * @ingroup lpc24xx 36 * @ingroup lpc32xx 35 37 * 36 38 * @brief DMA support. … … 81 83 82 84 /** 83 * @name DMA Configuration Register Defines 84 * 85 * @{ 86 */ 87 88 #define LPC_DMA_CFG_EN (1U << 0) 89 #define LPC_DMA_CFG_M_0 (1U << 1) 90 #define LPC_DMA_CFG_M_1 (1U << 2) 91 92 /** @} */ 93 94 /** 95 * @name DMA Channel Control Register Defines 96 * 97 * @{ 98 */ 99 100 #define LPC_DMA_CH_CTRL_TSZ_MASK 0xfffU 101 #define LPC_DMA_CH_CTRL_TSZ_MAX 0xfffU 102 103 #define LPC_DMA_CH_CTRL_SB_MASK (0x7U << 12) 104 #define LPC_DMA_CH_CTRL_SB_1 (0x0U << 12) 105 #define LPC_DMA_CH_CTRL_SB_4 (0x1U << 12) 106 #define LPC_DMA_CH_CTRL_SB_8 (0x2U << 12) 107 #define LPC_DMA_CH_CTRL_SB_16 (0x3U << 12) 108 #define LPC_DMA_CH_CTRL_SB_32 (0x4U << 12) 109 #define LPC_DMA_CH_CTRL_SB_64 (0x5U << 12) 110 #define LPC_DMA_CH_CTRL_SB_128 (0x6U << 12) 111 #define LPC_DMA_CH_CTRL_SB_256 (0x7U << 12) 112 113 #define LPC_DMA_CH_CTRL_DB_MASK (0x7U << 15) 114 #define LPC_DMA_CH_CTRL_DB_1 (0x0U << 15) 115 #define LPC_DMA_CH_CTRL_DB_4 (0x1U << 15) 116 #define LPC_DMA_CH_CTRL_DB_8 (0x2U << 15) 117 #define LPC_DMA_CH_CTRL_DB_16 (0x3U << 15) 118 #define LPC_DMA_CH_CTRL_DB_32 (0x4U << 15) 119 #define LPC_DMA_CH_CTRL_DB_64 (0x5U << 15) 120 #define LPC_DMA_CH_CTRL_DB_128 (0x6U << 15) 121 #define LPC_DMA_CH_CTRL_DB_256 (0x7U << 15) 122 123 #define LPC_DMA_CH_CTRL_SW_MASK (0x7U << 18) 124 #define LPC_DMA_CH_CTRL_SW_8 (0x0U << 18) 125 #define LPC_DMA_CH_CTRL_SW_16 (0x1U << 18) 126 #define LPC_DMA_CH_CTRL_SW_32 (0x2U << 18) 127 128 #define LPC_DMA_CH_CTRL_DW_MASK (0x7U << 21) 129 #define LPC_DMA_CH_CTRL_DW_8 (0x0U << 21) 130 #define LPC_DMA_CH_CTRL_DW_16 (0x1U << 21) 131 #define LPC_DMA_CH_CTRL_DW_32 (0x2U << 21) 132 133 #define LPC_DMA_CH_CTRL_SM_0 (0U << 24) 134 #define LPC_DMA_CH_CTRL_SM_1 (1U << 24) 135 136 #define LPC_DMA_CH_CTRL_DM_0 (0U << 25) 137 #define LPC_DMA_CH_CTRL_DM_1 (1U << 25) 138 139 #define LPC_DMA_CH_CTRL_SI (1U << 26) 140 #define LPC_DMA_CH_CTRL_DI (1U << 27) 141 #define LPC_DMA_CH_CTRL_ITC (1U << 31) 142 143 /** @} */ 144 145 /** 146 * @name DMA Channel Configuration Register Defines 147 * 148 * @{ 149 */ 150 151 #define LPC_DMA_CH_CFG_EN (1U << 0) 152 153 #define LPC_DMA_CH_CFG_SPER_MASK (0xfU << 1) 154 #define LPC_DMA_CH_CFG_SPER_SHIFT 1 155 #define LPC_DMA_CH_CFG_SPER_0 (0x0U << 1) 156 #define LPC_DMA_CH_CFG_SPER_1 (0x1U << 1) 157 #define LPC_DMA_CH_CFG_SPER_2 (0x2U << 1) 158 #define LPC_DMA_CH_CFG_SPER_3 (0x3U << 1) 159 #define LPC_DMA_CH_CFG_SPER_4 (0x4U << 1) 160 #define LPC_DMA_CH_CFG_SPER_5 (0x5U << 1) 161 #define LPC_DMA_CH_CFG_SPER_6 (0x6U << 1) 162 #define LPC_DMA_CH_CFG_SPER_7 (0x7U << 1) 163 #define LPC_DMA_CH_CFG_SPER_8 (0x8U << 1) 164 #define LPC_DMA_CH_CFG_SPER_9 (0x9U << 1) 165 #define LPC_DMA_CH_CFG_SPER_10 (0xaU << 1) 166 #define LPC_DMA_CH_CFG_SPER_11 (0xbU << 1) 167 #define LPC_DMA_CH_CFG_SPER_12 (0xcU << 1) 168 #define LPC_DMA_CH_CFG_SPER_13 (0xdU << 1) 169 #define LPC_DMA_CH_CFG_SPER_14 (0xeU << 1) 170 #define LPC_DMA_CH_CFG_SPER_15 (0xfU << 1) 171 172 #define LPC_DMA_CH_CFG_DPER_MASK (0xfU << 6) 173 #define LPC_DMA_CH_CFG_DPER_SHIFT 6 174 #define LPC_DMA_CH_CFG_DPER_0 (0x0U << 6) 175 #define LPC_DMA_CH_CFG_DPER_1 (0x1U << 6) 176 #define LPC_DMA_CH_CFG_DPER_2 (0x2U << 6) 177 #define LPC_DMA_CH_CFG_DPER_3 (0x3U << 6) 178 #define LPC_DMA_CH_CFG_DPER_4 (0x4U << 6) 179 #define LPC_DMA_CH_CFG_DPER_5 (0x5U << 6) 180 #define LPC_DMA_CH_CFG_DPER_6 (0x6U << 6) 181 #define LPC_DMA_CH_CFG_DPER_7 (0x7U << 6) 182 #define LPC_DMA_CH_CFG_DPER_8 (0x8U << 6) 183 #define LPC_DMA_CH_CFG_DPER_9 (0x9U << 6) 184 #define LPC_DMA_CH_CFG_DPER_10 (0xaU << 6) 185 #define LPC_DMA_CH_CFG_DPER_11 (0xbU << 6) 186 #define LPC_DMA_CH_CFG_DPER_12 (0xcU << 6) 187 #define LPC_DMA_CH_CFG_DPER_13 (0xdU << 6) 188 #define LPC_DMA_CH_CFG_DPER_14 (0xeU << 6) 189 #define LPC_DMA_CH_CFG_DPER_15 (0xfU << 6) 190 191 #define LPC_DMA_CH_CFG_FLOW_MASK (0x7U << 11) 192 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA (0x0U << 11) 193 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_DMA (0x1U << 11) 194 #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_DMA (0x2U << 11) 195 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DMA (0x3U << 11) 196 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DEST (0x4U << 11) 197 #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_PER (0x5U << 11) 198 #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_PER (0x6U << 11) 199 #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_SRC (0x7U << 11) 200 201 #define LPC_DMA_CH_CFG_IE (1U << 14) 202 #define LPC_DMA_CH_CFG_ITC (1U << 15) 203 #define LPC_DMA_CH_CFG_LOCK (1U << 16) 204 #define LPC_DMA_CH_CFG_ACTIVE (1U << 17) 205 #define LPC_DMA_CH_CFG_HALT (1U << 18) 85 * @name DMA Configuration Register 86 * 87 * @{ 88 */ 89 90 #define DMA_CFG_E BSP_BIT32(0) 91 #define DMA_CFG_M_0 BSP_BIT32(1) 92 #define DMA_CFG_M_1 BSP_BIT32(2) 93 94 /** @} */ 95 96 /** 97 * @name DMA Channel Control Register 98 * 99 * @{ 100 */ 101 102 #define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11) 103 #define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff) 104 105 #define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14) 106 #define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0) 107 #define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1) 108 #define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2) 109 #define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3) 110 #define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4) 111 #define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5) 112 #define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6) 113 #define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7) 114 115 #define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17) 116 #define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0) 117 #define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1) 118 #define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2) 119 #define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3) 120 #define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4) 121 #define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5) 122 #define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6) 123 #define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7) 124 125 #define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20) 126 #define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0) 127 #define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1) 128 #define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2) 129 130 #define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23) 131 #define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0) 132 #define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1) 133 #define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2) 134 135 #define DMA_CH_CTRL_S BSP_BIT32(24) 136 #define DMA_CH_CTRL_D BSP_BIT32(25) 137 #define DMA_CH_CTRL_SI BSP_BIT32(26) 138 #define DMA_CH_CTRL_DI BSP_BIT32(27) 139 #define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30) 140 #define DMA_CH_CTRL_I BSP_BIT32(31) 141 142 /** @} */ 143 144 /** 145 * @name DMA Channel Configuration Register 146 * 147 * @{ 148 */ 149 150 #define DMA_CH_CFG_E BSP_BIT32(0) 151 #define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5) 152 #define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10) 153 154 #define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13) 155 #define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0) 156 #define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1) 157 #define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2) 158 #define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3) 159 #define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4) 160 #define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5) 161 #define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6) 162 #define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7) 163 164 #define DMA_CH_CFG_IE BSP_BIT32(14) 165 #define DMA_CH_CFG_ITC BSP_BIT32(15) 166 #define DMA_CH_CFG_L BSP_BIT32(16) 167 #define DMA_CH_CFG_A BSP_BIT32(17) 168 #define DMA_CH_CFG_H BSP_BIT32(18) 169 170 /** @} */ 171 172 /** 173 * @name LPC24XX DMA Peripherals 174 * 175 * @{ 176 */ 177 178 #define LPC24XX_DMA_PER_SSP_0_TX 0 179 #define LPC24XX_DMA_PER_SSP_0_RX 1 180 #define LPC24XX_DMA_PER_SSP_1_TX 2 181 #define LPC24XX_DMA_PER_SSP_1_RX 3 182 #define LPC24XX_DMA_PER_SD_MMC 4 183 #define LPC24XX_DMA_PER_I2S_CH_0 5 184 #define LPC24XX_DMA_PER_I2S_CH_1 6 185 186 /** @} */ 187 188 /** 189 * @name LPC32XX DMA Peripherals 190 * 191 * @{ 192 */ 193 194 #define LPC32XX_DMA_PER_I2S_0_CH_0 0 195 #define LPC32XX_DMA_PER_I2S_0_CH_1 13 196 #define LPC32XX_DMA_PER_I2S_1_CH_0 2 197 #define LPC32XX_DMA_PER_I2S_1_CH_1 10 198 #define LPC32XX_DMA_PER_NAND_0 1 199 #define LPC32XX_DMA_PER_NAND_1 12 200 #define LPC32XX_DMA_PER_SD_MMC 4 201 #define LPC32XX_DMA_PER_SSP_0_RX 14 202 #define LPC32XX_DMA_PER_SSP_0_TX 15 203 #define LPC32XX_DMA_PER_SSP_1_RX 3 204 #define LPC32XX_DMA_PER_SSP_1_TX 11 205 #define LPC32XX_DMA_PER_UART_1_RX 6 206 #define LPC32XX_DMA_PER_UART_1_TX 5 207 #define LPC32XX_DMA_PER_UART_2_RX 8 208 #define LPC32XX_DMA_PER_UART_2_TX 7 209 #define LPC32XX_DMA_PER_UART_7_RX 10 210 #define LPC32XX_DMA_PER_UART_7_TX 9 206 211 207 212 /** @} */ -
c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c
r00d95ce0 rf6083f0 361 361 } else { 362 362 lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT 363 | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 363 | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 364 364 | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST; 365 365 } … … 503 503 504 504 /* Cache flush of descriptor */ 505 rtems_cache_flush_multiple_data_lines((void *)&desc [i], 506 sizeof(desc [0])); 505 rtems_cache_flush_multiple_data_lines( 506 (void *) &desc [i], 507 sizeof(desc [0]) 508 ); 507 509 508 510 /* Add mbuf to table */ … … 617 619 618 620 /* Fragment status */ 619 rtems_cache_invalidate_multiple_data_lines 620 ((void *)&status [receive_index],621 622 621 rtems_cache_invalidate_multiple_data_lines( 622 (void *) &status [receive_index], 623 sizeof(status [0]) 624 ); 623 625 stat = status [receive_index].info; 624 626 … … 945 947 desc [produce_index].start = mtod(m, uint32_t); 946 948 desc [produce_index].control = ctrl; 947 rtems_cache_flush_multiple_data_lines 948 ((void *)&desc [produce_index],949 950 949 rtems_cache_flush_multiple_data_lines( 950 (void *) &desc [produce_index], 951 sizeof(desc [0]) 952 ); 951 953 mbufs [produce_index] = m; 952 954 … … 1019 1021 1020 1022 /* Cache flush of descriptor */ 1021 rtems_cache_flush_multiple_data_lines 1022 ((void *)&desc [produce_index],1023 1024 1023 rtems_cache_flush_multiple_data_lines( 1024 (void *) &desc [produce_index], 1025 sizeof(desc [0]) 1026 ); 1025 1027 1026 1028 /* Next produce index */ … … 1286 1288 } 1287 1289 1290 static int lpc_eth_multicast_control( 1291 bool add, 1292 struct ifreq *ifr, 1293 struct arpcom *ac 1294 ) 1295 { 1296 int eno = 0; 1297 1298 if (add) { 1299 eno = ether_addmulti(ifr, ac); 1300 } else { 1301 eno = ether_delmulti(ifr, ac); 1302 } 1303 1304 if (eno == ENETRESET) { 1305 struct ether_multistep step; 1306 struct ether_multi *enm; 1307 1308 eno = 0; 1309 1310 lpc_eth->hashfilterl = 0; 1311 lpc_eth->hashfilterh = 0; 1312 1313 ETHER_FIRST_MULTI(step, ac, enm); 1314 while (enm != NULL) { 1315 uint64_t addrlo = 0; 1316 uint64_t addrhi = 0; 1317 1318 memcpy(&addrlo, enm->enm_addrlo, ETHER_ADDR_LEN); 1319 memcpy(&addrhi, enm->enm_addrhi, ETHER_ADDR_LEN); 1320 while (addrlo <= addrhi) { 1321 /* XXX: ether_crc32_le() does not work, why? */ 1322 uint32_t crc = ether_crc32_be((uint8_t *) &addrlo, ETHER_ADDR_LEN); 1323 uint32_t index = (crc >> 23) & 0x3f; 1324 1325 if (index < 32) { 1326 lpc_eth->hashfilterl |= 1U << index; 1327 } else { 1328 lpc_eth->hashfilterh |= 1U << (index - 32); 1329 } 1330 ++addrlo; 1331 } 1332 ETHER_NEXT_MULTI(step, enm); 1333 } 1334 } 1335 1336 return eno; 1337 } 1338 1288 1339 static int lpc_eth_interface_ioctl( 1289 1340 struct ifnet *ifp, 1290 ioctl_command_t c ommand,1341 ioctl_command_t cmd, 1291 1342 caddr_t data 1292 1343 ) … … 1298 1349 LPC_ETH_PRINTF("%s\n", __func__); 1299 1350 1300 switch (c ommand) {1351 switch (cmd) { 1301 1352 case SIOCGIFMEDIA: 1302 1353 case SIOCSIFMEDIA: 1303 rtems_mii_ioctl(&e->mdio, e, c ommand, (int *) data);1354 rtems_mii_ioctl(&e->mdio, e, cmd, (int *) data); 1304 1355 break; 1305 1356 case SIOCGIFADDR: 1306 1357 case SIOCSIFADDR: 1307 ether_ioctl(ifp, c ommand, data);1358 ether_ioctl(ifp, cmd, data); 1308 1359 break; 1309 1360 case SIOCSIFFLAGS: … … 1317 1368 break; 1318 1369 case SIOCADDMULTI: 1319 case SIOCDELMULTI: { 1320 eno = (command == SIOCADDMULTI) ? ether_addmulti(ifr, &e->arpcom) 1321 : ether_delmulti(ifr, &e->arpcom); 1322 if (eno == ENETRESET) { 1323 /* TODO: Use imperfect hash filter */ 1324 eno = 0; 1325 } 1370 case SIOCDELMULTI: 1371 eno = lpc_eth_multicast_control(cmd == SIOCADDMULTI, ifr, &e->arpcom); 1326 1372 break; 1327 }1328 1373 case SIO_RTEMS_SHOW_STATS: 1329 1374 lpc_eth_interface_stats(e);
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