Changeset f5c10645 in rtems


Ignore:
Timestamp:
Oct 16, 2013, 8:39:05 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
a502d677
Parents:
34568acf
git-author:
Ralf Kirchner <ralf.kirchner@…> (10/16/13 08:39:05)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/13/14 15:10:52)
Message:

bsp/arm: Invalidate SCU

Location:
c/src/lib/libbsp/arm/shared/include
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h

    r34568acf rf5c10645  
    4747  uint32_t pwrst;
    4848  uint32_t invss;
     49#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
     50#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
     51#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
     52#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
     53#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
     54#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
     55#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
     56#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
     57#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
     58#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
     59#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
     60#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
    4961  uint32_t reserved_10[12];
    5062  uint32_t fltstart;
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h

    r34568acf rf5c10645  
    88
    99/*
    10  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    7171}
    7272
     73BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate(
     74  volatile a9mpcore_scu *scu,
     75  uint32_t cpu_id,
     76  uint32_t ways
     77)
     78{
     79  scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
     80}
     81
    7382BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
    7483{
     
    8796
    8897  cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
     98
     99  arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
     100
    89101  if (cpu_id != 0) {
    90102    arm_a9mpcore_start_set_vector_base();
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