Changeset f52885b in rtems


Ignore:
Timestamp:
Sep 18, 2015, 9:53:31 PM (4 years ago)
Author:
Martin Galvan <martin.galvan@…>
Branches:
master
Children:
1f7c5c88
Parents:
7263a50
git-author:
Martin Galvan <martin.galvan@…> (09/18/15 21:53:31)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/23/15 12:53:25)
Message:

ARMv7M: Improve exception handler routine and add comments on SP selection

This patch adds a brief description of how context state is saved into the
SP on exception entry, and makes a few changes to _ARMV7M_Exception_default
in order to make it a bit more efficient. I also removed the unused 'v7mfsz'
input parameter.

This should apply over Sudarshan's patch.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/armv7m-exception-default.c

    r7263a50 rf52885b  
    2323void __attribute__((naked)) _ARMV7M_Exception_default( void )
    2424{
     25    /* On exception entry, ARMv7M saves context state onto a stack pointed to
     26     * by either MSP or PSP. The value stored in LR indicates whether we were
     27     * in Thread or Handler mode, whether we were using the FPU (if any),
     28     * and which stack pointer we were using.
     29     * In particular, bit 2 of LR will be 0 if we were using MSP.
     30     *
     31     * For a more detailed explanation, see the Exception Entry Behavior
     32     * section of the ARMv7M Architecture Reference Manual.
     33     */
     34
     35    /* As we're in Handler mode here, we'll always operate on MSP.
     36     * However, we need to store the right SP in our CPU_Exception_frame.
     37     */
    2538  __asm__ volatile (
    26     "sub sp, %[cpufsz]\n"
     39    "sub sp, %[cpufsz]\n"   /* Allocate space for a CPU_Exception_frame. */
    2740    "stm sp, {r0-r12}\n"
    28     "mov r2, lr\n"
    29     "mrs r1, msp\n"
    30     "mrs r0, psp\n"
    31     "tst lr, #4\n"
    32     "itt eq\n"
    33     "moveq r0, r1\n"
    34     "addeq r0, %[cpufsz]\n"
     41    "tst lr, #4\n"          /* Check if bit 2 of LR is zero. If so, PSR.Z = 1 */
     42    "itte eq\n"             /* IF bit 2 of LR is zero... (PSR.Z == 1) */
     43    "mrseq r0, msp\n"       /* THEN we were using MSP. */
     44    "addeq r0, %[cpufsz]\n" /* THEN, set r0 = old MSP value. */
     45    "mrsne r0, psp\n"       /* ELSE it's not zero; we were using PSP. */
    3546    "add r2, r0, %[v7mlroff]\n"
    3647    "add r1, sp, %[cpulroff]\n"
    37     "ldm r2, {r3-r5}\n"
    38     "stm r1, {r3-r5}\n"
     48    "ldm r2, {r3-r5}\n"     /* Grab LR, PC and PSR from the stack.. */
     49    "stm r1, {r3-r5}\n"     /* ..and store them in our CPU_Exception_frame. */
    3950    "mrs r1, ipsr\n"
    4051    "str r1, [sp, %[cpuvecoff]]\n"
     
    7586    :
    7687    : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
    77       [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)),
    7888      [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
    7989      [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
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