- Timestamp:
- 03/28/11 09:00:01 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- c4d9f313
- Parents:
- 305234f7
- Location:
- c/src/lib/libbsp/arm/lpc32xx
- Files:
-
- 15 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/lpc32xx/ChangeLog
r305234f7 rf437107 1 2011-03-29 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * configure.ac, include/bspopts.h.in: New BSP option 4 LPC32XX_SCRATCH_AREA_SIZE. Disable BSP option 5 LPC32XX_DISABLE_READ_ONLY_PROTECTION for all BSPs. 6 * include/boot.h: Removed application specific defines. 7 * include/nand-mlc.h, misc/nand-mlc.c: Changed configuration layout. 8 * include/mmu.h, misc/mmu.c: Documentation. Bugfix. 9 * include/bsp.h, startup/bspstarthooks.c, misc/restart.c, 10 startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1, 11 startup/linkcmds.lpc32xx_mzx_stage_2, 12 startup/linkcmds.lpc32xx_phycore: Support for scratch area. Moved 13 code into macros for reusability. 14 1 15 2011-02-21 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 16 -
c/src/lib/libbsp/arm/lpc32xx/configure.ac
r305234f7 rf437107 74 74 RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[disable cache for read-write data sections]) 75 75 76 RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[lpc32xx_mzx*],[1])77 76 RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[*],[]) 78 77 RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[disable MMU protection of read-only sections]) 78 79 RTEMS_BSPOPTS_SET([LPC32XX_SCRATCH_AREA_SIZE],[lpc32xx_mzx*],[4096]) 80 RTEMS_BSPOPTS_HELP([LPC32XX_SCRATCH_AREA_SIZE],[size of scratch area]) 79 81 80 82 RTEMS_BSPOPTS_SET([LPC32XX_STOP_GPDMA],[*],[1]) -
c/src/lib/libbsp/arm/lpc32xx/include/boot.h
r305234f7 rf437107 56 56 */ 57 57 58 #define LPC32XX_BOOT_STAGE_1_BLOCK_0 0 59 #define LPC32XX_BOOT_STAGE_1_BLOCK_1 1 60 #define LPC32XX_BOOT_STAGE_2_BLOCK_0 2 58 #define LPC32XX_BOOT_BLOCK_0 0 59 #define LPC32XX_BOOT_BLOCK_1 1 61 60 62 61 #define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0 -
c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
r305234f7 rf437107 136 136 extern uint32_t lpc32xx_magic_zero_size []; 137 137 138 #ifdef LPC32XX_SCRATCH_AREA_SIZE 139 /** 140 * @rief Scratch area. 141 * 142 * The usage is application specific. 143 */ 144 extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]; 145 #endif 146 147 #define LPC32XX_DO_STOP_GPDMA \ 148 do { \ 149 if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \ 150 if ((lpc32xx.dma.cfg & LPC_DMA_CFG_EN) != 0) { \ 151 int i = 0; \ 152 for (i = 0; i < 8; ++i) { \ 153 lpc32xx.dma.channels [i].cfg = 0; \ 154 } \ 155 lpc32xx.dma.cfg &= ~LPC_DMA_CFG_EN; \ 156 } \ 157 LPC32XX_DMACLK_CTRL = 0; \ 158 } \ 159 } while (0) 160 161 #define LPC32XX_DO_STOP_ETHERNET \ 162 do { \ 163 if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \ 164 lpc32xx.eth.command = 0x38; \ 165 lpc32xx.eth.mac1 = 0xcf00; \ 166 lpc32xx.eth.mac1 = 0; \ 167 LPC32XX_MAC_CLK_CTRL = 0; \ 168 } \ 169 } while (0) 170 171 #define LPC32XX_DO_STOP_USB \ 172 do { \ 173 if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \ 174 LPC32XX_OTG_CLK_CTRL = 0; \ 175 LPC32XX_USB_CTRL = 0x80000; \ 176 } \ 177 } while (0) 178 179 #define LPC32XX_DO_RESTART(addr) \ 180 do { \ 181 ARM_SWITCH_REGISTERS; \ 182 rtems_interrupt_level level; \ 183 uint32_t ctrl = 0; \ 184 \ 185 rtems_interrupt_disable(level); \ 186 \ 187 arm_cp15_data_cache_test_and_clean(); \ 188 arm_cp15_instruction_cache_invalidate(); \ 189 \ 190 ctrl = arm_cp15_get_control(); \ 191 ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \ 192 arm_cp15_set_control(ctrl); \ 193 \ 194 __asm__ volatile ( \ 195 ARM_SWITCH_TO_ARM \ 196 "mov pc, %[addr]\n" \ 197 ARM_SWITCH_BACK \ 198 : ARM_SWITCH_OUTPUT \ 199 : [addr] "r" (addr) \ 200 ); \ 201 } while (0) 202 138 203 /** @} */ 139 204 -
c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
r305234f7 rf437107 64 64 #undef LPC32XX_PERIPH_CLK 65 65 66 /* size of scratch area */ 67 #undef LPC32XX_SCRATCH_AREA_SIZE 68 66 69 /* stop Ethernet controller at start-up to avoid DMA interference */ 67 70 #undef LPC32XX_STOP_ETHERNET -
c/src/lib/libbsp/arm/lpc32xx/include/mmu.h
r305234f7 rf437107 8 8 9 9 /* 10 * Copyright (c) 2009 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * <rtems@embedded-brains.de> 10 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Obere Lagerstr. 30 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be … … 56 57 (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) 57 58 58 void lpc32xx_set_translation_table_entries( 59 /** 60 * @brief Sets the @a section_flags for the address range [@a begin, @a end). 61 * 62 * @return Previous section flags of the first modified entry. 63 */ 64 uint32_t lpc32xx_set_translation_table_entries( 59 65 const void *begin, 60 66 const void *end, -
c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
r305234f7 rf437107 182 182 */ 183 183 typedef struct { 184 /** 185 * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) 186 * or large pages (2048 Bytes user data and 64 Bytes spare data). 187 */ 188 bool small_pages; 189 190 /** 191 * @brief Selects 3/4 address cycles for small pages/large pages or 4/5 192 * address cycles. 193 */ 194 bool many_address_cycles; 195 196 /** 197 * @brief Selects 64 or 128 pages per block in case of large pages. 198 */ 199 bool normal_blocks; 184 uint32_t flags; 200 185 201 186 uint32_t block_count; … … 206 191 uint32_t time; 207 192 } lpc32xx_mlc_config; 193 194 /** 195 * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) 196 * or large pages (2048 Bytes user data and 64 Bytes spare data). 197 */ 198 #define MLC_SMALL_PAGES 0x1U 199 200 /** 201 * @Brief Selects 3/4 address cycles for small pages/large pages or 4/5 202 * address cycles. 203 */ 204 #define MLC_MANY_ADDRESS_CYCLES 0x2U 205 206 /** 207 * @brief Selects 64 or 128 pages per block in case of large pages. 208 */ 209 #define MLC_NORMAL_BLOCKS 0x4U 208 210 209 211 /** -
c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c
r305234f7 rf437107 8 8 9 9 /* 10 * Copyright (c) 2010 embedded brains GmbH. All rights reserved.10 * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. 11 11 * 12 12 * embedded brains GmbH … … 23 23 #include <bsp/mmu.h> 24 24 25 void lpc32xx_set_translation_table_entries( 25 static uint32_t disable_mmu(void) 26 { 27 uint32_t ctrl = 0; 28 29 arm_cp15_data_cache_test_and_clean_and_invalidate(); 30 31 ctrl = arm_cp15_get_control(); 32 arm_cp15_set_control(ctrl & ~ARM_CP15_CTRL_M); 33 34 arm_cp15_tlb_invalidate(); 35 36 return ctrl; 37 } 38 39 static void restore_mmu_control(uint32_t ctrl) 40 { 41 arm_cp15_set_control(ctrl); 42 } 43 44 uint32_t set_translation_table_entries( 26 45 const void *begin, 27 46 const void *end, … … 32 51 uint32_t i = ARM_MMU_SECT_GET_INDEX(begin); 33 52 uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end)); 53 uint32_t ctrl = disable_mmu(); 54 uint32_t section_flags_of_first_entry = ttb [i]; 34 55 35 56 while (i < iend) { … … 37 58 ++i; 38 59 } 60 61 restore_mmu_control(ctrl); 62 63 return section_flags_of_first_entry; 39 64 } 65 66 uint32_t lpc32xx_set_translation_table_entries( 67 const void *begin, 68 const void *end, 69 uint32_t section_flags 70 ) 71 { 72 rtems_interrupt_level level; 73 uint32_t section_flags_of_first_entry = 0; 74 75 rtems_interrupt_disable(level); 76 section_flags_of_first_entry = 77 set_translation_table_entries(begin, end, section_flags); 78 rtems_interrupt_enable(level); 79 80 return section_flags_of_first_entry; 81 } -
c/src/lib/libbsp/arm/lpc32xx/misc/nand-mlc.c
r305234f7 rf437107 25 25 static volatile lpc32xx_nand_mlc *const mlc = &lpc32xx.nand_mlc; 26 26 27 static bool mlc_small_pages; 28 29 static bool mlc_many_address_cycles; 30 31 static bool mlc_normal_blocks; 27 static uint32_t mlc_flags; 32 28 33 29 static uint32_t mlc_block_count; … … 35 31 static uint32_t mlc_page_count; 36 32 33 static bool mlc_small_pages(void) 34 { 35 return (mlc_flags & MLC_SMALL_PAGES) != 0; 36 } 37 38 static bool mlc_many_address_cycles(void) 39 { 40 return (mlc_flags & MLC_MANY_ADDRESS_CYCLES) != 0; 41 } 42 43 static bool mlc_normal_blocks(void) 44 { 45 return (mlc_flags & MLC_NORMAL_BLOCKS) != 0; 46 } 47 37 48 uint32_t lpc32xx_mlc_page_size(void) 38 49 { 39 if (mlc_small_pages ) {50 if (mlc_small_pages()) { 40 51 return 512; 41 52 } else { … … 46 57 uint32_t lpc32xx_mlc_pages_per_block(void) 47 58 { 48 if (mlc_small_pages ) {59 if (mlc_small_pages()) { 49 60 return 32; 50 61 } else { 51 if (mlc_normal_blocks ) {62 if (mlc_normal_blocks()) { 52 63 return 64; 53 64 } else { … … 100 111 static void mlc_set_block_address(uint32_t block_index) 101 112 { 102 if (mlc_small_pages ) {113 if (mlc_small_pages()) { 103 114 mlc->addr = (uint8_t) (block_index << 5); 104 115 mlc->addr = (uint8_t) (block_index >> 3); 105 if (mlc_many_address_cycles ) {116 if (mlc_many_address_cycles()) { 106 117 mlc->addr = (uint8_t) (block_index >> 11); 107 118 } 108 119 } else { 109 if (mlc_normal_blocks ) {120 if (mlc_normal_blocks()) { 110 121 mlc->addr = (uint8_t) (block_index << 6); 111 122 mlc->addr = (uint8_t) (block_index >> 2); 112 if (mlc_many_address_cycles ) {123 if (mlc_many_address_cycles()) { 113 124 mlc->addr = (uint8_t) (block_index >> 10); 114 125 } … … 116 127 mlc->addr = (uint8_t) (block_index << 7); 117 128 mlc->addr = (uint8_t) (block_index >> 1); 118 if (mlc_many_address_cycles ) {129 if (mlc_many_address_cycles()) { 119 130 mlc->addr = (uint8_t) (block_index >> 9); 120 131 } … … 126 137 { 127 138 mlc->addr = 0; 128 if (mlc_small_pages ) {139 if (mlc_small_pages()) { 129 140 mlc->addr = (uint8_t) page_index; 130 141 mlc->addr = (uint8_t) (page_index >> 8); 131 if (mlc_many_address_cycles ) {142 if (mlc_many_address_cycles()) { 132 143 mlc->addr = (uint8_t) (page_index >> 16); 133 144 } … … 136 147 mlc->addr = (uint8_t) page_index; 137 148 mlc->addr = (uint8_t) (page_index >> 8); 138 if (mlc_many_address_cycles ) {149 if (mlc_many_address_cycles()) { 139 150 mlc->addr = (uint8_t) (page_index >> 16); 140 151 } … … 146 157 uint32_t icr = 0; 147 158 148 mlc_small_pages = cfg->small_pages; 149 mlc_many_address_cycles = cfg->many_address_cycles; 150 mlc_normal_blocks = cfg->normal_blocks; 159 mlc_flags = cfg->flags; 151 160 mlc_block_count = cfg->block_count; 152 161 mlc_page_count = cfg->block_count * lpc32xx_mlc_pages_per_block(); … … 160 169 161 170 /* Configuration */ 162 if (!mlc_small_pages ) {171 if (!mlc_small_pages()) { 163 172 icr |= MLC_ICR_LARGE_PAGES; 164 173 } 165 if (mlc_many_address_cycles ) {174 if (mlc_many_address_cycles()) { 166 175 icr |= MLC_ICR_ADDR_WORD_COUNT_4_5; 167 176 } … … 192 201 { 193 202 rtems_status_code sc = RTEMS_SUCCESSFUL; 194 size_t small_pages_count = mlc_small_pages ? 1 : MLC_SMALL_PAGES_PER_LARGE_PAGE;203 size_t small_pages_count = mlc_small_pages() ? 1 : MLC_SMALL_PAGES_PER_LARGE_PAGE; 195 204 size_t sp = 0; 196 205 size_t i = 0; … … 203 212 mlc_wait_until_ready(); 204 213 mlc->cmd = 0x00; 205 if (!mlc_small_pages ) {214 if (!mlc_small_pages()) { 206 215 mlc->cmd = 0x30; 207 216 } … … 285 294 { 286 295 rtems_status_code sc = RTEMS_IO_ERROR; 287 size_t small_pages_count = mlc_small_pages ? 1 : MLC_SMALL_PAGES_PER_LARGE_PAGE;296 size_t small_pages_count = mlc_small_pages() ? 1 : MLC_SMALL_PAGES_PER_LARGE_PAGE; 288 297 size_t sp = 0; 289 298 size_t i = 0; -
c/src/lib/libbsp/arm/lpc32xx/misc/restart.c
r305234f7 rf437107 31 31 void bsp_restart(void *addr) 32 32 { 33 ARM_SWITCH_REGISTERS; 34 rtems_interrupt_level level; 35 uint32_t ctrl = 0; 36 37 rtems_interrupt_disable(level); 38 39 arm_cp15_data_cache_test_and_clean(); 40 arm_cp15_instruction_cache_invalidate(); 41 42 ctrl = arm_cp15_get_control(); 43 ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); 44 arm_cp15_set_control(ctrl); 45 46 __asm__ volatile ( 47 ARM_SWITCH_TO_ARM 48 "mov pc, %[addr]\n" 49 ARM_SWITCH_BACK 50 : ARM_SWITCH_OUTPUT 51 : [addr] "r" (addr) 52 ); 33 LPC32XX_DO_RESTART(addr); 53 34 } -
c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
r305234f7 rf437107 74 74 .end = (uint32_t) bsp_section_fast_data_end, 75 75 .flags = LPC32XX_MMU_READ_WRITE_DATA 76 #ifdef LPC32XX_SCRATCH_AREA_SIZE 77 }, { 78 .begin = (uint32_t) &lpc32xx_scratch_area [0], 79 .end = (uint32_t) &lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE], 80 .flags = LPC32XX_MMU_READ_ONLY_DATA 81 #endif 76 82 }, { 77 83 .begin = (uint32_t) bsp_section_start_begin, … … 225 231 { 226 232 #ifdef LPC32XX_STOP_GPDMA 227 if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { 228 if ((lpc32xx.dma.cfg & LPC_DMA_CFG_EN) != 0) { 229 int i = 0; 230 231 for (i = 0; i < 8; ++i) { 232 lpc32xx.dma.channels [i].cfg = 0; 233 } 234 235 lpc32xx.dma.cfg &= ~LPC_DMA_CFG_EN; 236 } 237 LPC32XX_DMACLK_CTRL = 0; 238 } 233 LPC32XX_DO_STOP_GPDMA; 239 234 #endif 240 235 241 236 #ifdef LPC32XX_STOP_ETHERNET 242 if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { 243 lpc32xx.eth.command = 0x38; 244 lpc32xx.eth.mac1 = 0xcf00; 245 lpc32xx.eth.mac1 = 0; 246 LPC32XX_MAC_CLK_CTRL = 0; 247 } 237 LPC32XX_DO_STOP_ETHERNET; 248 238 #endif 249 239 250 240 #ifdef LPC32XX_STOP_USB 251 if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { 252 LPC32XX_OTG_CLK_CTRL = 0; 253 LPC32XX_USB_CTRL = 0x80000; 254 } 241 LPC32XX_DO_STOP_USB; 255 242 #endif 256 243 } -
c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx
r305234f7 rf437107 38 38 RAM_INT : ORIGIN = 0x08000000, LENGTH = 256k 39 39 RAM_MMU : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */ 40 RAM_EXT : ORIGIN = 0x80004000, LENGTH = 32M - 16k /* SDRAM on DYCS0 */ 40 RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */ 41 RAM_EXT : ORIGIN = 0x80005000, LENGTH = 32M - 20k /* SDRAM on DYCS0 */ 41 42 NIRVANA : ORIGIN = 0, LENGTH = 0 42 43 } … … 58 59 REGION_ALIAS ("REGION_STACK", RAM_INT); 59 60 61 lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH); 62 60 63 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096; 61 64 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; 62 65 63 bsp_section_r obarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1M;66 bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; 64 67 65 68 INCLUDE linkcmds.lpc32xx -
c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_stage_1
r305234f7 rf437107 39 39 RAM_VEC : ORIGIN = 0x0803a000, LENGTH = 8k 40 40 RAM_MMU : ORIGIN = 0x0803c000, LENGTH = 16k 41 RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */ 41 42 NIRVANA : ORIGIN = 0, LENGTH = 0 42 43 } … … 58 59 REGION_ALIAS ("REGION_STACK", RAM_INT); 59 60 61 lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH); 62 60 63 bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 7296; 61 64 -
c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_stage_2
r305234f7 rf437107 36 36 37 37 MEMORY { 38 RAM_INT : ORIGIN = 0x08000000, LENGTH = 256k 39 RAM_MMU : ORIGIN = 0x81c00000, LENGTH = 16k /* SDRAM on DYCS0 */ 40 RAM_EXT : ORIGIN = 0x81c04000, LENGTH = 4M - 16k /* SDRAM on DYCS0 */ 38 RAM_INT : ORIGIN = 0x08000000, LENGTH = 240k 39 RAM_FAST : ORIGIN = 0x0803c000, LENGTH = 16k 40 RAM_MMU : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */ 41 RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */ 42 RAM_EXT : ORIGIN = 0x81c00000, LENGTH = 4M /* SDRAM on DYCS0 */ 41 43 NIRVANA : ORIGIN = 0, LENGTH = 0 42 44 } … … 50 52 REGION_ALIAS ("REGION_DATA", RAM_EXT); 51 53 REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); 52 REGION_ALIAS ("REGION_FAST_TEXT", RAM_ EXT);54 REGION_ALIAS ("REGION_FAST_TEXT", RAM_FAST); 53 55 REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); 54 REGION_ALIAS ("REGION_FAST_DATA", RAM_ EXT);56 REGION_ALIAS ("REGION_FAST_DATA", RAM_FAST); 55 57 REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); 56 58 REGION_ALIAS ("REGION_BSS", RAM_EXT); … … 58 60 REGION_ALIAS ("REGION_STACK", RAM_INT); 59 61 62 lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH); 63 60 64 bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 8192; 61 65 -
c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore
r305234f7 rf437107 63 63 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; 64 64 65 bsp_section_r obarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1M;65 bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; 66 66 67 67 INCLUDE linkcmds.lpc32xx
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