Changeset f41fb2b in rtems


Ignore:
Timestamp:
Dec 6, 2011, 2:01:55 PM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
7e0ef0f7
Parents:
6dbbe5b8
Message:

2011-12-06 Sebastian Huber <sebastian.huber@…>

  • misc/system-clocks.c: New file.
  • Makefile.am: Reflect change from above.
  • include/nand-mlc.h: Fixed lpc32xx_mlc_is_bad_page().
  • make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_stage_1.cfg: Flags for EABI tool chain.
  • configure.ac, include/bsp.h, include/lpc32xx.h, misc/emc.c, misc/i2c.c, rtc/rtc-config.c, startup/bspstarthooks.c: Avoid compile time ARM_CLK and HCLK.
Location:
c/src/lib/libbsp/arm/lpc32xx
Files:
1 added
12 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc32xx/ChangeLog

    r6dbbe5b8 rf41fb2b  
     12011-12-06      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * misc/system-clocks.c: New file.
     4        * Makefile.am: Reflect change from above.
     5        * include/nand-mlc.h: Fixed lpc32xx_mlc_is_bad_page().
     6        * make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_stage_1.cfg: Flags
     7        for EABI tool chain.
     8        * configure.ac, include/bsp.h, include/lpc32xx.h, misc/emc.c,
     9        misc/i2c.c, rtc/rtc-config.c, startup/bspstarthooks.c: Avoid compile
     10        time ARM_CLK and HCLK.
     11
    1122011-11-29      Joel Sherrill <joel.sherrilL@OARcorp.com>
    213
  • c/src/lib/libbsp/arm/lpc32xx/Makefile.am

    r6dbbe5b8 rf41fb2b  
    8383
    8484# Shared
    85 libbsp_a_SOURCES += ../../shared/bootcard.c \
    86         ../../shared/bspclean.c \
    87         ../../shared/bspgetworkarea.c \
    88         ../../shared/bsplibc.c \
    89         ../../shared/bsppost.c \
    90         ../../shared/bsppredriverhook.c \
    91         ../../shared/bsppretaskinghook.c \
    92         ../../shared/gnatinstallhandler.c \
    93         ../../shared/sbrk.c \
    94         ../../shared/src/stackalloc.c \
    95         ../../shared/src/uart-output-char.c \
    96         ../shared/abort/simple_abort.c
     85libbsp_a_SOURCES += ../../shared/bootcard.c
     86libbsp_a_SOURCES += ../../shared/bspclean.c
     87libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
     88libbsp_a_SOURCES += ../../shared/bsplibc.c
     89libbsp_a_SOURCES += ../../shared/bsppost.c
     90libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
     91libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
     92libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
     93libbsp_a_SOURCES += ../../shared/sbrk.c
     94libbsp_a_SOURCES += ../../shared/src/stackalloc.c
     95libbsp_a_SOURCES += ../../shared/src/uart-output-char.c
     96libbsp_a_SOURCES += ../shared/abort/simple_abort.c
    9797libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
    9898
    9999# Startup
    100 libbsp_a_SOURCES += startup/bspstart.c \
    101         startup/bspreset.c
     100libbsp_a_SOURCES += startup/bspreset.c
     101libbsp_a_SOURCES += startup/bspstart.c
    102102
    103103# IRQ
     
    127127
    128128# Misc
    129 libbsp_a_SOURCES += misc/timer.c \
    130         misc/nand-mlc.c \
    131         misc/nand-mlc-read-blocks.c \
    132         misc/nand-mlc-write-blocks.c \
    133         misc/nand-mlc-erase-block-safe.c \
    134         misc/restart.c \
    135         misc/boot.c \
    136         misc/emc.c \
    137         misc/mmu.c \
    138         misc/i2c.c
     129libbsp_a_SOURCES += misc/boot.c
     130libbsp_a_SOURCES += misc/emc.c
     131libbsp_a_SOURCES += misc/i2c.c
     132libbsp_a_SOURCES += misc/mmu.c
     133libbsp_a_SOURCES += misc/nand-mlc.c
     134libbsp_a_SOURCES += misc/nand-mlc-erase-block-safe.c
     135libbsp_a_SOURCES += misc/nand-mlc-read-blocks.c
     136libbsp_a_SOURCES += misc/nand-mlc-write-blocks.c
     137libbsp_a_SOURCES += misc/restart.c
     138libbsp_a_SOURCES += misc/system-clocks.c
     139libbsp_a_SOURCES += misc/timer.c
    139140
    140141# SSP
  • c/src/lib/libbsp/arm/lpc32xx/configure.ac

    r6dbbe5b8 rf41fb2b  
    3131RTEMS_BSPOPTS_SET([LPC32XX_OSCILLATOR_RTC],[*],[32768U])
    3232RTEMS_BSPOPTS_HELP([LPC32XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
    33 
    34 RTEMS_BSPOPTS_SET([LPC32XX_ARM_CLK],[*],[208000000U])
    35 RTEMS_BSPOPTS_HELP([LPC32XX_ARM_CLK],[ARM clock in Hz])
    36 
    37 RTEMS_BSPOPTS_SET([LPC32XX_HCLK],[*],[104000000U])
    38 RTEMS_BSPOPTS_HELP([LPC32XX_HCLK],[AHB bus clock in Hz])
    3933
    4034RTEMS_BSPOPTS_SET([LPC32XX_PERIPH_CLK],[*],[13000000U])
  • c/src/lib/libbsp/arm/lpc32xx/include/bsp.h

    r6dbbe5b8 rf41fb2b  
    88
    99/*
    10  * Copyright (c) 2009, 2010
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    110111  } while (elapsed < delay);
    111112}
     113
     114#if LPC32XX_OSCILLATOR_MAIN == 13000000U
     115  #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
     116    (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
     117  #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
     118    (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(1))
     119#else
     120  #error "unexpected main oscillator frequency"
     121#endif
     122
     123bool lpc32xx_start_pll_setup(
     124  uint32_t hclkpll_ctrl,
     125  uint32_t hclkdiv_ctrl,
     126  bool force
     127);
     128
     129uint32_t lpc32xx_sysclk(void);
     130
     131uint32_t lpc32xx_hclkpll_clk(void);
     132
     133uint32_t lpc32xx_periph_clk(void);
     134
     135uint32_t lpc32xx_hclk(void);
     136
     137uint32_t lpc32xx_arm_clk(void);
     138
     139uint32_t lpc32xx_dram_clk(void);
    112140
    113141void bsp_restart(void *addr);
  • c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

    r6dbbe5b8 rf41fb2b  
    202202#define HCLK_PLL_LOCK BSP_BIT32(0)
    203203#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
     204#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)
    204205#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
     206#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)
    205207#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
     208#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)
    206209#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
    207210#define HCLK_PLL_DIRECT BSP_BIT32(14)
     
    218221
    219222#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
     223#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)
    220224#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
     225#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)
    221226#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
     227#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)
    222228
    223229/** @} */
  • c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h

    r6dbbe5b8 rf41fb2b  
    393393);
    394394
     395/**
     396 * @brief Checks if the page spare area indicates to a bad page.
     397 *
     398 * If the first (byte offset 0) or sixth (byte offset 5) byte of the spare area
     399 * has a value other than 0xff, then it returns @true (the page is bad), else
     400 * it returns @a false (the page is not bad).
     401 *
     402 * Samsung uses the sixth byte to indicate a bad page.  Mircon uses the first
     403 * and sixth byte to indicate a bad page.
     404 *
     405 * This functions works only for small page flashes.
     406 */
    395407static inline bool lpc32xx_mlc_is_bad_page(const uint32_t *spare)
    396408{
    397   uint32_t valid_block_mask = 0xff00;
    398   return (spare [1] & valid_block_mask) != valid_block_mask;
     409  uint32_t first_byte_mask = 0x000000ff;
     410  uint32_t sixth_byte_mask = 0x0000ff00;
     411
     412  return (spare [0] & first_byte_mask) != first_byte_mask
     413    || (spare [1] & sixth_byte_mask) != sixth_byte_mask;
    399414}
    400415
  • c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc

    r6dbbe5b8 rf41fb2b  
    99RTEMS_CPU = arm
    1010
    11 CPU_CFLAGS = -mstructure-size-boundary=8 -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=soft -mthumb \
    12         -fno-schedule-insns2
     11CPU_CFLAGS = -mcpu=arm926ej-s -mthumb
    1312
    14 CFLAGS_OPTIMIZE_V = -O2 -g
     13CFLAGS_OPTIMIZE_V ?= -O2 -g
  • c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1.cfg

    r6dbbe5b8 rf41fb2b  
    55#
    66
     7CFLAGS_OPTIMIZE_V = -Os -g
     8
    79include $(RTEMS_ROOT)/make/custom/lpc32xx.inc
  • c/src/lib/libbsp/arm/lpc32xx/misc/emc.c

    r6dbbe5b8 rf41fb2b  
    9494void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg)
    9595{
    96   /* Enable clock */
    97   LPC32XX_HCLKDIV_CTRL |= HCLK_DIV_DDRAM_CLK(1);
    98 
    9996  /* Enable buffers in AHB ports */
    10097  emc_ahb [0].control = EMC_AHB_PORT_BUFF_EN;
  • c/src/lib/libbsp/arm/lpc32xx/misc/i2c.c

    r6dbbe5b8 rf41fb2b  
    88
    99/*
    10  * Copyright (c) 2010
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    5253}
    5354
    54 #if LPC32XX_HCLK != 104000000U
    55   #error "unexpected HCLK"
    56 #endif
    57 
    5855rtems_status_code lpc32xx_i2c_clock(
    5956  volatile lpc32xx_i2c *i2c,
     
    6158)
    6259{
     60  uint32_t clk_div = lpc32xx_hclk() / clock_in_hz;
    6361  uint32_t clk_lo = 0;
    6462  uint32_t clk_hi = 0;
     
    6664  switch (clock_in_hz) {
    6765    case 100000:
    68       clk_lo = 520;
    69       clk_hi = 520;
     66      clk_lo = clk_div / 2;
    7067      break;
    7168    case 400000:
    72       clk_lo = 166;
    73       clk_hi = 94;
     69      clk_lo = (64 * clk_div) / 100;
    7470      break;
    7571    default:
    7672      return RTEMS_INVALID_CLOCK;
    7773  }
     74
     75  clk_hi = clk_div - clk_lo;
    7876
    7977  i2c->clk_lo = clk_lo;
  • c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c

    r6dbbe5b8 rf41fb2b  
    88
    99/*
    10  * Copyright (c) 2009
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    4142static void lpc32xx_rtc_set(uint32_t val)
    4243{
    43   unsigned i = LPC32XX_ARM_CLK / LPC32XX_OSCILLATOR_RTC;
     44  unsigned i = lpc32xx_arm_clk() / LPC32XX_OSCILLATOR_RTC;
    4445
    4546  lpc32xx.rtc.ctrl |= LPC32XX_RTC_CTRL_STOP;
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c

    r6dbbe5b8 rf41fb2b  
    88
    99/*
    10  * Copyright (c) 2009
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    2021 */
    2122
    22 #include <stdbool.h>
    23 
    24 #include <bspopts.h>
     23#include <bsp.h>
    2524#include <bsp/start.h>
    2625#include <bsp/lpc32xx.h>
     
    4544LINKER_SYMBOL(lpc32xx_translation_table_base);
    4645
    47 static void BSP_START_TEXT_SECTION clear_bss(void)
     46static BSP_START_TEXT_SECTION void clear_bss(void)
    4847{
    4948  const int *end = (const int *) bsp_section_bss_end;
     
    135134  };
    136135
    137   static void BSP_START_TEXT_SECTION set_translation_table_entries(
     136  static BSP_START_TEXT_SECTION void set_translation_table_entries(
    138137    uint32_t *ttb,
    139138    const lpc32xx_mmu_config *config
     
    152151  }
    153152
    154   static void BSP_START_TEXT_SECTION
     153  static BSP_START_TEXT_SECTION void
    155154    setup_translation_table_and_enable_mmu(uint32_t ctrl)
    156155  {
     
    180179#endif
    181180
    182 static void BSP_START_TEXT_SECTION setup_mmu_and_cache(void)
     181static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void)
    183182{
    184183  uint32_t ctrl = 0;
     
    199198}
    200199
    201 #if LPC32XX_OSCILLATOR_MAIN != 13000000U
    202   #error "unexpected main oscillator frequency"
    203 #endif
    204 
    205 static void BSP_START_TEXT_SECTION setup_pll(void)
     200BSP_START_TEXT_SECTION bool lpc32xx_start_pll_setup(
     201  uint32_t hclkpll_ctrl,
     202  uint32_t hclkdiv_ctrl,
     203  bool force
     204)
    206205{
    207206  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
    208 
    209   if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0) {
    210     /* Enable HCLK PLL */
    211     LPC32XX_HCLKPLL_CTRL = HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1);
     207  bool settings_ok =
     208    ((LPC32XX_HCLKPLL_CTRL ^ hclkpll_ctrl) & BSP_MSK32(1, 16)) == 0
     209      && ((LPC32XX_HCLKDIV_CTRL ^ hclkdiv_ctrl) & BSP_MSK32(0, 8)) == 0;
     210
     211  if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0 || (!settings_ok && force)) {
     212    /* Disable HCLK PLL output */
     213    LPC32XX_PWR_CTRL = pwr_ctrl & ~PWR_NORMAL_RUN_MODE;
     214
     215    /* Configure HCLK PLL */
     216    LPC32XX_HCLKPLL_CTRL = hclkpll_ctrl;
    212217    while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) {
    213218      /* Wait */
     
    215220
    216221    /* Setup HCLK divider */
    217     LPC32XX_HCLKDIV_CTRL = HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1);
     222    LPC32XX_HCLKDIV_CTRL = hclkdiv_ctrl;
    218223
    219224    /* Enable HCLK PLL output */
    220225    LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE;
    221226  }
    222 }
    223 
    224 void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
     227
     228  return settings_ok;
     229}
     230
     231#if LPC32XX_OSCILLATOR_MAIN != 13000000U
     232  #error "unexpected main oscillator frequency"
     233#endif
     234
     235static BSP_START_TEXT_SECTION void setup_pll(void)
     236{
     237  uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL_INIT_VALUE;
     238  uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL_INIT_VALUE;
     239
     240  lpc32xx_start_pll_setup(hclkpll_ctrl, hclkdiv_ctrl, false);
     241}
     242
     243BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
    225244{
    226245  setup_pll();
     
    228247}
    229248
    230 static void BSP_START_TEXT_SECTION stop_dma_activities(void)
     249static BSP_START_TEXT_SECTION void stop_dma_activities(void)
    231250{
    232251  #ifdef LPC32XX_STOP_GPDMA
     
    243262}
    244263
    245 static void BSP_START_TEXT_SECTION setup_uarts(void)
     264static BSP_START_TEXT_SECTION void setup_uarts(void)
    246265{
    247266  uint32_t uartclk_ctrl = 0;
     
    278297}
    279298
    280 static void BSP_START_TEXT_SECTION setup_timer(void)
     299static BSP_START_TEXT_SECTION void setup_timer(void)
    281300{
    282301  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
     
    293312}
    294313
    295 void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
     314BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
    296315{
    297316  stop_dma_activities();
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