Changeset f3343c6e in rtems


Ignore:
Timestamp:
Sep 12, 2007, 3:15:32 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
bd51a63
Parents:
38feb6d5
Message:

2007-09-12 Joel Sherrill <joel.sherrill@…>

PR 1257/bsps

  • csb336/network/lan91c11x.c, csb337/startup/bspstart.c, edb7312/irq/irq.c, gba/irq/irq.c, gba/irq/irq_init.c, gp32/startup/bspstart.c, rtl22xx/startup/bspstart.c, shared/abort/abort.c, shared/abort/simple_abort.c, shared/irq/irq_init.c: Code outside of cpukit should use the public API for rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the public API and directly accessing _CPU_ISR_Disable and _CPU_ISR_Enable, they were bypassing the compiler memory barrier directive which could lead to problems. This patch also changes the type of the variable passed into these routines and addresses minor style issues.
Location:
c/src/lib/libbsp/arm
Files:
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/ChangeLog

    r38feb6d5 rf3343c6e  
     12007-09-12      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        PR 1257/bsps
     4        * csb336/network/lan91c11x.c, csb337/startup/bspstart.c,
     5        edb7312/irq/irq.c, gba/irq/irq.c, gba/irq/irq_init.c,
     6        gp32/startup/bspstart.c, rtl22xx/startup/bspstart.c,
     7        shared/abort/abort.c, shared/abort/simple_abort.c,
     8        shared/irq/irq_init.c: Code outside of cpukit should use the public
     9        API for rtems_interrupt_disable/rtems_interrupt_enable. By bypassing
     10        the public API and directly accessing _CPU_ISR_Disable and
     11        _CPU_ISR_Enable, they were bypassing the compiler memory barrier
     12        directive which could lead to problems. This patch also changes the
     13        type of the variable passed into these routines and addresses minor
     14        style issues.
     15
    1162007-09-08      Joel Sherrill <joel.sherrill@OARcorp.com>
    217
  • c/src/lib/libbsp/arm/csb336/network/lan91c11x.c

    r38feb6d5 rf3343c6e  
    1515#include "lan91c11x.h"
    1616
    17 static rtems_interrupt_level level;
    18 
    19 void lan91c11x_lock(void)
    20 {
    21     _CPU_ISR_Disable(level);
    22 }
    23 
    24 void lan91c11x_unlock(void)
    25 {
    26     _CPU_ISR_Enable(level);
    27 }
    28 
    2917uint16_t lan91c11x_read_reg(int reg)
    3018{
     
    3422    rtems_interrupt_level level;
    3523
    36     _CPU_ISR_Disable(level);
     24    rtems_interrupt_disable(level);
    3725
    3826    /* save the bank register */
     
    4735    ptr[7] = old_bank;
    4836
    49     _CPU_ISR_Enable(level);
     37    rtems_interrupt_enable(level);
    5038    return val;
    5139}
     
    5745    rtems_interrupt_level level;
    5846
    59     _CPU_ISR_Disable(level);
     47    rtems_interrupt_disable(level);
    6048
    6149    /* save the bank register */
     
    7058    ptr[7] = old_bank;
    7159
    72     _CPU_ISR_Enable(level);
     60    rtems_interrupt_enable(level);
    7361}
    7462
  • c/src/lib/libbsp/arm/csb337/startup/bspstart.c

    r38feb6d5 rf3343c6e  
    193193    rtems_interrupt_level level;
    194194
    195     _CPU_ISR_Disable(level);
     195    rtems_interrupt_disable(level);
    196196
    197197    /* Enable the watchdog timer, then wait for the world to end. */
  • c/src/lib/libbsp/arm/edb7312/irq/irq.c

    r38feb6d5 rf3343c6e  
    5252    }
    5353
    54     _CPU_ISR_Disable(level);
     54    rtems_interrupt_disable(level);
    5555
    5656    /*
     
    9191    }
    9292
    93     _CPU_ISR_Enable(level);
     93    rtems_interrupt_enable(level);
    9494
    9595    return 1;
     
    111111      return 0;
    112112    }
    113     _CPU_ISR_Disable(level);
     113    rtems_interrupt_disable(level);
    114114
    115115    /*
     
    148148    *(HdlTable + irq->name) = default_int_handler;
    149149
    150     _CPU_ISR_Enable(level);
     150    rtems_interrupt_enable(level);
    151151
    152152    return 1;
  • c/src/lib/libbsp/arm/gba/irq/irq.c

    r38feb6d5 rf3343c6e  
    6868    }
    6969
    70     _CPU_ISR_Disable(level);
     70    rtems_interrupt_disable(level);
    7171
    7272    /*
     
    9090    irq->on(irq);
    9191
    92     _CPU_ISR_Enable(level);
     92    rtems_interrupt_enable(level);
    9393
    9494    return 1;
     
    116116       return 0;
    117117    }
    118     _CPU_ISR_Disable(level);
     118    rtems_interrupt_disable(level);
    119119
    120120    /*
     
    133133    *(HdlTable + irq->name) = default_int_handler;
    134134
    135     _CPU_ISR_Enable(level);
     135    rtems_interrupt_enable(level);
    136136
    137137    return 1;
  • c/src/lib/libbsp/arm/gba/irq/irq_init.c

    r38feb6d5 rf3343c6e  
    5555    vectorTable = (uint32_t *)VECTOR_TABLE;
    5656
    57     _CPU_ISR_Disable(level);
     57    rtems_interrupt_disable(level);
    5858
    5959    /* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS */
  • c/src/lib/libbsp/arm/gp32/startup/bspstart.c

    r38feb6d5 rf3343c6e  
    197197{
    198198    rtems_interrupt_level level;
    199     _CPU_ISR_Disable(level);
     199    rtems_interrupt_disable(level);
    200200    printk("bsp_reset.....\n");
    201201        /* disable mmu, invalide i-cache and call swi #4 */
  • c/src/lib/libbsp/arm/rtl22xx/startup/bspstart.c

    r38feb6d5 rf3343c6e  
    258258    rtems_interrupt_level level;
    259259
    260     _CPU_ISR_Disable(level);
     260    rtems_interrupt_disable(level);
    261261
    262262    while(1);
  • c/src/lib/libbsp/arm/shared/abort/abort.c

    r38feb6d5 rf3343c6e  
    105105{
    106106    /* Clarify, which type is correct, CPU_Exception_frame or Context_Control */
    107 
    108     uint8_t    decode;
    109     uint8_t    insn_type;
    110 
    111     uint32_t    tmp;
     107    uint8_t               decode;
     108    uint8_t               insn_type;
     109    rtems_interrupt_level level;
    112110
    113111    g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
     
    153151
    154152    /* disable interrupts, wait forever */
    155     _CPU_ISR_Disable(tmp);
     153    rtems_interrupt_disable(level);
    156154    while(1) {
    157155        continue;
  • c/src/lib/libbsp/arm/shared/abort/simple_abort.c

    r38feb6d5 rf3343c6e  
    110110  /* Clarify, which type is correct, CPU_Exception_frame or Context_Control */
    111111
    112   uint8_t    decode;
    113   uint8_t    insn_type;
    114   uint32_t    tmp;
     112  uint8_t               decode;
     113  uint8_t               insn_type;
     114  rtems_interrupt_level level;
    115115
    116116  decode = ((insn >> 20) & 0xff);
     
    153153
    154154  /* disable interrupts, wait forever */
    155   _CPU_ISR_Disable(tmp);
     155  rtems_interrupt_disable(level);
    156156  while(1) {
    157157    continue;
  • c/src/lib/libbsp/arm/shared/irq/irq_init.c

    r38feb6d5 rf3343c6e  
    3232    rtems_interrupt_level       level;
    3333
    34     _CPU_ISR_Disable(level);
     34    rtems_interrupt_disable(level);
    3535
    3636    /* First, connect the ISR_Handler for IRQ and FIQ interrupts */
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