Changeset f2fed0c1 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 11:24:07 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
861d315
Parents:
13f1462f
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 11:24:07)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
Message:

bsps/arm: L2C 310 add compile time checks

Simplify initialization. Replace some assert() with fatal errors.

Location:
c/src/lib/libbsp
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h

    r13f1462f rf2fed0c1  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    4040#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
    4141
    42 #define BSP_ARM_L2C_310_BASE 0xFFFEF000U
     42#define BSP_ARM_L2C_310_BASE 0xfffef000
     43
     44#define BSP_ARM_L2C_310_ID 0x410000c9
    4345
    4446/* Forward declaration */
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r13f1462f rf2fed0c1  
    5959#include <assert.h>
    6060#include <bsp.h>
     61#include <bsp/fatal.h>
    6162#include <libcpu/arm-cp15.h>
    6263#include <rtems/rtems/intr.h>
     
    118119#define CACHE_L2C_310_L2CC_ID_PART_L210 ( 1 << 6 )
    119120#define CACHE_L2C_310_L2CC_ID_PART_L310 ( 3 << 6 )
     121#define CACHE_L2C_310_L2CC_ID_IMPL_MASK ( 0xff << 24 )
    120122  /** @brief Cache type */
    121123  uint32_t cache_type;
     
    11011103}
    11021104
    1103 static void cache_l2c_310_unlock( void )
    1104 {
    1105   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    1106 
    1107 
     1105static void cache_l2c_310_unlock( volatile L2CC *l2cc )
     1106{
    11081107  l2cc->d_lockdown_0 = 0;
    11091108  l2cc->i_lockdown_0 = 0;
     
    11241123}
    11251124
     1125static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc )
     1126{
     1127  while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1128
     1129  while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
     1130
     1131  while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1132}
     1133
     1134/* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */
     1135
     1136#if (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_PART_MASK) \
     1137  != CACHE_L2C_310_L2CC_ID_PART_L310
     1138#error "invalid L2-310 cache controller part number"
     1139#endif
     1140
     1141#if ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x8) \
     1142  && ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x9)
     1143#error "invalid L2-310 cache controller RTL revision"
     1144#endif
     1145
    11261146static inline void
    11271147cache_l2c_310_enable( void )
    11281148{
    11291149  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     1150  uint32_t cache_id = l2cc->cache_id;
    11301151  cache_l2c_310_rtl_release rtl_release =
    1131     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     1152    cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     1153  uint32_t id_mask =
     1154    CACHE_L2C_310_L2CC_ID_IMPL_MASK | CACHE_L2C_310_L2CC_ID_PART_MASK;
     1155
     1156  /*
     1157   * Do we actually have an L2C-310 cache controller?  Has BSP_ARM_L2C_310_BASE
     1158   * been configured correctly?
     1159   */
     1160  if (
     1161    (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask)
     1162      || rtl_release < (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK)
     1163  ) {
     1164    bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID );
     1165  }
     1166
     1167  l2c_310_cache_check_errata( rtl_release );
    11321168
    11331169  /* Only enable if L2CC is currently disabled */
    11341170  if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
    1135     uint32_t                     cache_id =
    1136       l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
    1137     int                          ways     = 0;
    1138 
    1139     /* Do we actually have an L2C-310 cache controller?
    1140     * Has BSP_ARM_L2C_310_BASE been configured correctly? */
    1141     switch ( cache_id ) {
    1142       case CACHE_L2C_310_L2CC_ID_PART_L310:
    1143       {
    1144         /* If this assertion fails, you have a release of the
    1145         * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ...
    1146         * methods are not yet implemented. This means you will get incorrect
    1147         * errata handling */
    1148         assert(    rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P3
    1149                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P2
    1150                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P1
    1151                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P0
    1152                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R2_P0
    1153                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R1_P0
    1154                 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    1155         if ( l2cc->aux_ctrl & ( 1 << 16 ) ) {
    1156           ways = 16;
    1157         } else {
    1158           ways = 8;
    1159         }
    1160 
    1161         assert( ways == CACHE_l2C_310_NUM_WAYS );
    1162       }
    1163       break;
    1164       case CACHE_L2C_310_L2CC_ID_PART_L210:
    1165 
    1166         /* Invalid case */
    1167 
    1168         /* Support for this type is not implemented in this driver.
    1169         * Either support needs to get added or a seperate driver needs to get
    1170         * implemented */
    1171         assert( cache_id != CACHE_L2C_310_L2CC_ID_PART_L210 );
    1172         break;
    1173       default:
    1174 
    1175         /* Unknown case */
    1176         assert( cache_id == CACHE_L2C_310_L2CC_ID_PART_L310 );
    1177         break;
     1171    uint32_t aux_ctrl;
     1172    int ways;
     1173
     1174    /* Make sure that I&D is not locked down when starting */
     1175    cache_l2c_310_unlock( l2cc );
     1176
     1177    cache_l2c_310_wait_for_background_ops( l2cc );
     1178
     1179    aux_ctrl = l2cc->aux_ctrl;
     1180
     1181    if ( (aux_ctrl & ( 1 << 16 )) != 0 ) {
     1182      ways = 16;
     1183    } else {
     1184      ways = 8;
    11781185    }
    11791186
    1180     if ( ways > 0 ) {
    1181       uint32_t              aux;
    1182 
    1183       /* Set up the way size */
    1184       aux  = l2cc->aux_ctrl;
    1185       aux &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
    1186       aux |= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK;
    1187 
    1188       /* Make sure that I&D is not locked down when starting */
    1189       cache_l2c_310_unlock();
    1190 
    1191       /* Level 2 configuration and control registers must not get written while
    1192       * background operations are pending */
    1193       while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
    1194 
    1195       while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
    1196 
    1197       while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
    1198 
    1199       l2cc->aux_ctrl = aux;
    1200 
    1201       /* Set up the latencies */
    1202       l2cc->tag_ram_ctrl  = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT;
    1203       l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK;
    1204 
    1205       cache_l2c_310_invalidate_entire();
    1206 
    1207       /* Clear the pending interrupts */
    1208       l2cc->int_clr = l2cc->int_raw_status;
    1209 
    1210       l2c_310_cache_check_errata( rtl_release );
    1211 
    1212       /* Enable the L2CC */
    1213       l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;
     1187    if ( ways != CACHE_l2C_310_NUM_WAYS ) {
     1188      bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS );
    12141189    }
     1190
     1191    /* Set up the way size */
     1192    aux_ctrl &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
     1193    aux_ctrl |= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK;
     1194
     1195    l2cc->aux_ctrl = aux_ctrl;
     1196
     1197    /* Set up the latencies */
     1198    l2cc->tag_ram_ctrl  = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT;
     1199    l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK;
     1200
     1201    cache_l2c_310_invalidate_entire();
     1202
     1203    /* Clear the pending interrupts */
     1204    l2cc->int_clr = l2cc->int_raw_status;
     1205
     1206    /* Enable the L2CC */
     1207    l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;
    12151208  }
    12161209}
     
    12271220    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    12281221
    1229     /* Level 2 configuration and control registers must not get written while
    1230      * background operations are pending */
    1231     while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
    1232 
    1233     while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
    1234 
    1235     while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1222    cache_l2c_310_wait_for_background_ops( l2cc );
    12361223
    12371224    /* Disable the L2 cache */
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    r13f1462f rf2fed0c1  
    5656#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
    5757
    58 #define BSP_ARM_L2C_310_BASE 0xF8F02000U
     58#define BSP_ARM_L2C_310_BASE 0xf8f02000
     59
     60#define BSP_ARM_L2C_310_ID 0x410000c8
    5961
    6062/**
  • c/src/lib/libbsp/shared/include/fatal.h

    r13f1462f rf2fed0c1  
    107107
    108108  /* Libchip fatal codes */
    109   DWMAC_FATAL_TOO_MANY_RBUFS_CONFIGURED = BSP_FATAL_CODE_BLOCK(8)
     109  DWMAC_FATAL_TOO_MANY_RBUFS_CONFIGURED = BSP_FATAL_CODE_BLOCK(8),
     110
     111  /* ARM fatal codes */
     112  ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9),
     113  ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS
    110114} bsp_fatal_code;
    111115
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