Changeset f2e6c3e in rtems


Ignore:
Timestamp:
Jan 13, 2015, 10:38:18 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
85dbf52
Parents:
3e2647a7
Message:

bsp/qoriq: Add T2080RDB and T4240RDB variants

Location:
c/src/lib/libbsp
Files:
4 added
20 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/qoriq/Makefile.am

    r3e2647a7 rf2e6c3e  
    2626        ../../shared/include/utility.h \
    2727        ../shared/include/u-boot-board-info.h \
     28        ../shared/include/u-boot-generic-board-info.h \
    2829        ../shared/include/start.h \
    2930        ../shared/include/tictac.h \
     
    4748        startup/linkcmds.qoriq_core_0 \
    4849        startup/linkcmds.qoriq_core_1 \
    49         startup/linkcmds.qoriq_p1020rdb
     50        startup/linkcmds.qoriq_p1020rdb \
     51        startup/linkcmds.qoriq_t2080rdb \
     52        startup/linkcmds.qoriq_t4240rdb
    5053
    5154noinst_LIBRARIES += libbsp.a
  • c/src/lib/libbsp/powerpc/qoriq/configure.ac

    r3e2647a7 rf2e6c3e  
    2929[only support Book E exception types])
    3030
     31RTEMS_BSPOPTS_SET([PPC_CACHE_ALIGNMENT],[qoriq_t*],[64])
     32RTEMS_BSPOPTS_SET([PPC_CACHE_ALIGNMENT],[*],[])
     33RTEMS_BSPOPTS_HELP([PPC_CACHE_ALIGNMENT],[the cache alignment])
     34
     35RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L1_SIZE],[*],[(32 * 1024)])
     36RTEMS_BSPOPTS_HELP([PPC_CACHE_DATA_L1_SIZE],[the L1 data cache size])
     37
     38RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L2_SIZE],[qoriq_t*],[(2048 * 1024)])
     39RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L2_SIZE],[*],[(256 * 1024)])
     40RTEMS_BSPOPTS_HELP([PPC_CACHE_DATA_L2_SIZE],[the L2 data cache size])
     41
     42RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L1_SIZE],[*],[(32 * 1024)])
     43RTEMS_BSPOPTS_HELP([PPC_CACHE_INSTRUCTION_L1_SIZE],[the L1 instruction cache size])
     44
     45RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L2_SIZE],[qoriq_t*],[(2048 * 1024)])
     46RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L2_SIZE],[*],[(256 * 1024)])
     47RTEMS_BSPOPTS_HELP([PPC_CACHE_INSTRUCTION_L2_SIZE],[the L2 instruction cache size])
     48
    3149RTEMS_BSPOPTS_SET([BSP_CONSOLE_BAUD],[*],[115200])
    3250RTEMS_BSPOPTS_HELP([BSP_CONSOLE_BAUD],[default baud for console and other serial devices])
     
    3755RTEMS_BSPOPTS_SET([HAS_UBOOT],[*],[1])
    3856RTEMS_BSPOPTS_HELP([HAS_UBOOT],[enables U-Boot support])
     57
     58RTEMS_BSPOPTS_SET([U_BOOT_64_BIT_PHYS_SIZE],[qoriq_t*],[1])
     59RTEMS_BSPOPTS_SET([U_BOOT_64_BIT_PHYS_SIZE],[*],[])
     60RTEMS_BSPOPTS_HELP([U_BOOT_64_BIT_PHYS_SIZE],[if defined, then use uint64_t for phys_size_t])
     61
     62RTEMS_BSPOPTS_SET([U_BOOT_GENERIC_BOARD_INFO],[qoriq_t*],[1])
     63RTEMS_BSPOPTS_SET([U_BOOT_GENERIC_BOARD_INFO],[*],[])
     64RTEMS_BSPOPTS_HELP([U_BOOT_GENERIC_BOARD_INFO],[if defined, then use the generic bd_t structure])
     65
     66RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_p2020*],[0x3fff0000])
     67RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_t2080*],[0x7fef4000])
     68RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_t4240*],[0x7ff33000])
     69RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[*],[0x1fff0000])
     70RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_BEGIN],[the begin address of the boot page set up by U-Boot])
     71
     72RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_p2020*],[0x3fffffff])
     73RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_t2080*],[0x7fef4fff])
     74RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_t4240*],[0x7ff33fff])
     75RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[*],[0x1fffffff])
     76RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_LAST],[the last address of the boot page set up by U-Boot])
     77
     78RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[qoriq_p2020*],[0xf240])
     79RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[qoriq_t*],[0x0200])
     80RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[*],[0xf2a0])
     81RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[the offset to the spin table in the boot page set up by U-Boot])
     82
     83RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[qoriq_t2080*],[8])
     84RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[qoriq_t4240*],[24])
     85RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[*],[2])
     86RTEMS_BSPOPTS_HELP([QORIQ_CPU_COUNT],[virtual processor count])
     87
     88RTEMS_BSPOPTS_SET([QORIQ_THREAD_COUNT],[qoriq_t*],[2])
     89RTEMS_BSPOPTS_SET([QORIQ_THREAD_COUNT],[*],[1])
     90RTEMS_BSPOPTS_HELP([QORIQ_THREAD_COUNT],[the number of threads per processor])
    3991
    4092RTEMS_BSPOPTS_SET([QORIQ_ETSEC_1_PHY_ADDR],[*],[-1])
     
    4799RTEMS_BSPOPTS_HELP([QORIQ_ETSEC_3_PHY_ADDR],[PHY address for eTSEC interface 3])
    48100
    49 RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_core_0],[1])
    50 RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_p1020rdb],[1])
    51 RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[*],[0])
     101RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_core_1],[0])
     102RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[*],[1])
    52103RTEMS_BSPOPTS_HELP([QORIQ_UART_0_ENABLE],[use 1 to enable UART 0, otherwise use 0])
    53104
    54 RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_core_0],[1])
    55 RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_p1020rdb],[1])
    56 RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[*],[0])
     105RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_core_1],[0])
     106RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[*],[1])
    57107RTEMS_BSPOPTS_HELP([QORIQ_UART_1_ENABLE],[use 1 to enable UART 1, otherwise use 0])
    58108
     
    85135RTEMS_BSPOPTS_HELP([QORIQ_INTERCOM_AREA_SIZE],[inter-processor communication area size])
    86136
     137RTEMS_BSPOPTS_SET([QORIQ_TLB1_ENTRY_COUNT],[qoriq_t*],[64])
     138RTEMS_BSPOPTS_SET([QORIQ_TLB1_ENTRY_COUNT],[*],[16])
     139RTEMS_BSPOPTS_HELP([QORIQ_TLB1_ENTRY_COUNT],[TLB1 entry count])
     140
     141RTEMS_BSPOPTS_SET([QORIQ_INITIAL_MSR],[qoriq_t*],[0x02002200])
    87142RTEMS_BSPOPTS_SET([QORIQ_INITIAL_MSR],[*],[0x02000200])
    88143RTEMS_BSPOPTS_HELP([QORIQ_INITIAL_MSR],[initial MSR value])
    89144
     145RTEMS_BSPOPTS_SET([QORIQ_INITIAL_SPEFSCR],[qoriq_t*],[])
    90146RTEMS_BSPOPTS_SET([QORIQ_INITIAL_SPEFSCR],[*],[0x00000000])
    91147RTEMS_BSPOPTS_HELP([QORIQ_INITIAL_SPEFSCR],[initial SPEFSCR value])
    92148
     149RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[qoriq_t*],[0xf])
    93150RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[*],[0x0])
    94151RTEMS_BSPOPTS_HELP([QORIQ_MMU_DEVICE_MAS7],[MAS7 value for device TLB1 entries])
     
    97154RTEMS_BSPOPTS_SET([QORIQ_CLOCK_TIMER],[*],[0])
    98155RTEMS_BSPOPTS_HELP([QORIQ_CLOCK_TIMER],[global timer used for system clock, 0..3 maps to A0..A3, and 4..7 maps to B0..B3])
     156
     157RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[qoriq_t2080*],[QORIQ_CHIP_T2080])
     158RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[qoriq_t4240*],[QORIQ_CHIP_T4240])
     159RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[*],[QORIQ_CHIP_P1020])
     160RTEMS_BSPOPTS_HELP([QORIQ_CHIP_VARIANT],[chip variant, use one of the defines QORIQ_CHIP_P1020, QORIQ_CHIP_T2080 or QORIQ_CHIP_T4240])
     161
     162RTEMS_BSPOPTS_SET([QORIQ_BUS_CLOCK_DIVIDER],[qoriq_t*],[2])
     163RTEMS_BSPOPTS_SET([QORIQ_BUS_CLOCK_DIVIDER],[*],[1])
     164RTEMS_BSPOPTS_HELP([QORIQ_BUS_CLOCK_DIVIDER],[divider of the platform clock to get the clock most on-chip peripherals])
    99165
    100166RTEMS_CHECK_NETWORKING
  • c/src/lib/libbsp/powerpc/qoriq/console/console-config.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    6767  .set_reg = set_register,
    6868  .port = (uintptr_t) &qoriq.uart_0,
    69   .irq = QORIQ_IRQ_DUART,
     69  .irq = QORIQ_IRQ_DUART_1,
    7070  .initial_baud = BSP_CONSOLE_BAUD
    7171};
     
    7878  .set_reg = set_register,
    7979  .port = (uintptr_t) &qoriq.uart_1,
    80   .irq = QORIQ_IRQ_DUART,
     80  .irq = QORIQ_IRQ_DUART_1,
    8181  .initial_baud = BSP_CONSOLE_BAUD
    8282};
  • c/src/lib/libbsp/powerpc/qoriq/console/uart-bridge-master.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2011-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
  • c/src/lib/libbsp/powerpc/qoriq/include/bsp.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    3737
    3838#define BSP_FEATURE_IRQ_EXTENSION
     39
     40#define QORIQ_CHIP(alpha, num) ((alpha) * 10000 + (num))
     41
     42#define QORIQ_CHIP_P1020 QORIQ_CHIP('P', 1020)
     43
     44#define QORIQ_CHIP_T2080 QORIQ_CHIP('T', 2080)
     45
     46#define QORIQ_CHIP_T4240 QORIQ_CHIP('T', 4240)
     47
     48#define QORIQ_CHIP_IS_T_VARIANT(variant) ((variant) / 10000 == 'T')
    3949
    4050extern unsigned BSP_bus_frequency;
  • c/src/lib/libbsp/powerpc/qoriq/include/irq.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2424#define LIBBSP_POWERPC_QORIQ_IRQ_H
    2525
    26 #include <rtems.h>
     26#include <bsp.h>
    2727#include <rtems/irq.h>
    2828#include <rtems/irq-extension.h>
     
    3232#endif /* __cplusplus */
    3333
     34#define QORIQ_IRQ_ERROR 0
     35
     36#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
     37
     38#define QORIQ_IRQ_PCI_EXPRESS_1 4
     39#define QORIQ_IRQ_PCI_EXPRESS_2 5
     40#define QORIQ_IRQ_PCI_EXPRESS_3 6
     41#define QORIQ_IRQ_PCI_EXPRESS_4 7
     42#define QORIQ_IRQ_PAMU 8
     43#define QORIQ_IRQ_IFC 9
     44#define QORIQ_IRQ_DMA_CHANNEL_1_1 12
     45#define QORIQ_IRQ_DMA_CHANNEL_1_2 13
     46#define QORIQ_IRQ_DMA_CHANNEL_1_3 14
     47#define QORIQ_IRQ_DMA_CHANNEL_1_4 15
     48#define QORIQ_IRQ_DMA_CHANNEL_2_1 16
     49#define QORIQ_IRQ_DMA_CHANNEL_2_2 17
     50#define QORIQ_IRQ_DMA_CHANNEL_2_3 18
     51#define QORIQ_IRQ_DMA_CHANNEL_2_4 19
     52#define QORIQ_IRQ_DUART_1 20
     53#define QORIQ_IRQ_DUART_2 21
     54#define QORIQ_IRQ_DUARL_I2C_1 22
     55#define QORIQ_IRQ_DUARL_I2C_2 23
     56#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24
     57#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25
     58#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26
     59#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27
     60#define QORIQ_IRQ_USB_1 28
     61#define QORIQ_IRQ_USB_2 29
     62#define QORIQ_IRQ_ESDHC 32
     63#define QORIQ_IRQ_PERF_MON 36
     64#define QORIQ_IRQ_ESPI 37
     65#define QORIQ_IRQ_GPIO_2 38
     66#define QORIQ_IRQ_GPIO_1 39
     67#define QORIQ_IRQ_SATA_1 52
     68#define QORIQ_IRQ_SATA_2 53
     69#define QORIQ_IRQ_DMA_CHANNEL_1_5 60
     70#define QORIQ_IRQ_DMA_CHANNEL_1_6 61
     71#define QORIQ_IRQ_DMA_CHANNEL_1_7 62
     72#define QORIQ_IRQ_DMA_CHANNEL_1_8 63
     73#define QORIQ_IRQ_DMA_CHANNEL_2_5 64
     74#define QORIQ_IRQ_DMA_CHANNEL_2_6 65
     75#define QORIQ_IRQ_DMA_CHANNEL_2_7 66
     76#define QORIQ_IRQ_DMA_CHANNEL_2_8 67
     77#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68
     78#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69
     79#define QORIQ_IRQ_GPIO_3 70
     80#define QORIQ_IRQ_GPIO_4 71
     81#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72
     82#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73
     83#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74
     84#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75
     85#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76
     86#define QORIQ_IRQ_SEC_MON 77
     87#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78
     88#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79
     89#define QORIQ_IRQ_FRAME_MGR 80
     90#define QORIQ_IRQ_MDIO_1 84
     91#define QORIQ_IRQ_MDIO_2 85
     92#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88
     93#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89
     94#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90
     95#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91
     96#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92
     97#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93
     98#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94
     99#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95
     100#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96
     101#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97
     102#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98
     103#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99
     104#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100
     105#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101
     106#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102
     107#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103
     108#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104
     109#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105
     110#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106
     111#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107
     112#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109
     113#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109
     114#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110
     115#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111
     116#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112
     117#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113
     118#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114
     119#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115
     120#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116
     121#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117
     122#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118
     123#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119
     124#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120
     125#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121
     126#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122
     127#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123
     128#define QORIQ_IRQ_DMA_CHANNEL_3_1 240
     129#define QORIQ_IRQ_DMA_CHANNEL_3_2 241
     130#define QORIQ_IRQ_DMA_CHANNEL_3_3 242
     131#define QORIQ_IRQ_DMA_CHANNEL_3_4 243
     132#define QORIQ_IRQ_DMA_CHANNEL_3_4 244
     133#define QORIQ_IRQ_DMA_CHANNEL_3_5 245
     134#define QORIQ_IRQ_DMA_CHANNEL_3_6 246
     135#define QORIQ_IRQ_DMA_CHANNEL_3_8 247
     136
     137#define QORIQ_IRQ_EXT_BASE 128
     138
     139#else /* QORIQ_CHIP_VARIANT */
     140
    34141/**
    35142 * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources
     
    42149 */
    43150
    44 #define QORIQ_IRQ_ERROR 0
    45151#define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1
    46152#define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2
     
    108214#define QORIQ_IRQ_ETSEC_RX_2 20
    109215#define QORIQ_IRQ_ETSEC_ER_2 24
    110 #define QORIQ_IRQ_DUART 26
     216#define QORIQ_IRQ_DUART_1 26
    111217#define QORIQ_IRQ_I2C 27
    112218#define QORIQ_IRQ_PERFORMANCE_MONITOR 28
     
    127233/** @} */
    128234
     235#define QORIQ_IRQ_EXT_BASE 64
     236
     237#endif /* QORIQ_CHIP_VARIANT */
     238
    129239/**
    130240 * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources
     
    137247 */
    138248
    139 #define QORIQ_IRQ_EXT_BASE 64
    140249#define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0)
    141250#define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1)
  • c/src/lib/libbsp/powerpc/qoriq/include/mmu.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2727#include <stdbool.h>
    2828
     29#include <bspopts.h>
     30
    2931#ifdef __cplusplus
    3032extern "C" {
     
    4143 */
    4244
    43 #define QORIQ_MMU_ENTRY_COUNT 32
    44 
    4545#define QORIQ_MMU_MIN_POWER 12
    46 #define QORIQ_MMU_MAX_POWER 32
     46#define QORIQ_MMU_MAX_POWER 30
    4747#define QORIQ_MMU_POWER_STEP 2
    4848
     
    5858typedef struct {
    5959        int count;
    60         qoriq_mmu_entry entries [QORIQ_MMU_ENTRY_COUNT];
     60        qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT];
    6161} qoriq_mmu_context;
    6262
  • c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2424#define LIBBSP_POWERPC_QORIQ_QORIQ_H
    2525
     26#include <bsp.h>
    2627#include <bsp/tsec.h>
    2728#include <bsp/utility.h>
     
    3334#define QORIQ_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
    3435#define QORIQ_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
    35 
    36 typedef struct {
    37         uint32_t ccsrbar;
    38         uint32_t reserved_0;
    39         uint32_t altcbar;
    40         uint32_t reserved_1;
    41         uint32_t altcar;
    42         uint32_t reserved_2 [3];
    43         uint32_t bptr;
    44 } qoriq_lcc;
    45 
    46 #define CCSRBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
    47 #define CCSRBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
    48 #define CCSRBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
    49 
    50 #define ALTCBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
    51 #define ALTCBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
    52 #define ALTCBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
    53 
    54 #define ALTCAR_EN BSP_BBIT32(0)
    55 #define ALTCAR_TRGT_ID(val) BSP_BFLD32(val, 8, 11)
    56 #define ALTCAR_TRGT_ID_GET(reg) BSP_BFLD32GET(reg, 8, 11)
    57 #define ALTCAR_TRGT_ID_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
    58 
    59 #define BPTR_EN BSP_BBIT32(0)
    60 #define BPTR_BOOT_PAGE(val) BSP_BFLD32(val, 8, 31)
    61 #define BPTR_BOOT_PAGE_GET(reg) BSP_BFLD32GET(reg, 8, 31)
    62 #define BPTR_BOOT_PAGE_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
    63 
    64 typedef struct {
    65         uint32_t bar;
    66         uint32_t reserved_0;
    67         uint32_t ar;
    68         uint32_t reserved_1 [5];
    69 } qoriq_law;
    70 
    71 #define LAWBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 31)
    72 #define LAWBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 31)
    73 #define LAWBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
    74 
    75 #define LAWAR_EN BSP_BBIT32(0)
    76 #define LAWAR_TRGT(val) BSP_BFLD32(val, 8, 11)
    77 #define LAWAR_TRGT_GET(reg) BSP_BFLD32GET(reg, 8, 11)
    78 #define LAWAR_TRGT_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
    79 #define LAWAR_SIZE(val) BSP_BFLD32(val, 26, 31)
    80 #define LAWAR_SIZE_GET(reg) BSP_BFLD32GET(reg, 26, 31)
    81 #define LAWAR_SIZE_SET(reg, val) BSP_BFLD32SET(reg, val, 26, 31)
    82 
    83 typedef struct {
    84 } qoriq_ecm;
    85 
    86 typedef struct {
    87 } qoriq_ddr_controller;
    88 
    89 typedef struct {
    90 } qoriq_i2c;
    91 
    92 typedef struct {
    93 } qoriq_uart;
    94 
    95 typedef struct {
    96 } qoriq_local_bus;
    97 
    98 typedef struct {
    99 } qoriq_spi;
    100 
    101 typedef struct {
    102 } qoriq_pci_express;
    103 
    104 typedef struct {
    105 } qoriq_gpio;
    106 
    107 typedef struct {
    108 } qoriq_tdm;
    109 
    110 typedef struct {
    111 } qoriq_l2_cache;
    112 
    113 typedef struct {
    114 } qoriq_dma;
    115 
    116 typedef struct {
    117   QORIQ_RESERVE(0x000, 0x100);
    118   uint16_t caplength;
    119   uint16_t hciversion;
    120   uint32_t hcsparams;
    121   uint32_t hccparams;
    122   QORIQ_RESERVE(0x10c, 0x120);
    123   uint32_t dciversion;
    124   uint32_t dccparams;
    125   QORIQ_RESERVE(0x128, 0x140);
    126   uint32_t usbcmd;
    127   uint32_t usbsts;
    128   uint32_t usbintr;
    129   uint32_t frindex;
    130   QORIQ_RESERVE(0x150, 0x154);
    131   union {
    132     uint32_t periodiclistbase;
    133     uint32_t deviceaddr;
    134   } perbase_devaddr;
    135   union {
    136     uint32_t asynclistaddr;
    137     uint32_t addr;
    138   } async_addr;
    139   QORIQ_RESERVE(0x15c, 0x160);
    140   uint32_t burstsize;
    141   uint32_t txfilltuning;
    142   QORIQ_RESERVE(0x168, 0x170);
    143   uint32_t viewport;
    144   QORIQ_RESERVE(0x174, 0x180);
    145   uint32_t configflag;
    146   uint32_t portsc1;
    147   QORIQ_RESERVE(0x188, 0x1a8);
    148   uint32_t usbmode;
    149   uint32_t endptsetupstat;
    150   uint32_t endpointprime;
    151   uint32_t endptflush;
    152   uint32_t endptstatus;
    153   uint32_t endptcomplete;
    154   uint32_t endptctrl[6];
    155   QORIQ_RESERVE(0x1d8, 0x400);
    156   uint32_t snoop1;
    157   uint32_t snoop2;
    158   uint32_t age_cnt_thresh;
    159   uint32_t pri_ctrl;
    160   uint32_t si_ctrl;
    161   QORIQ_RESERVE(0x414, 0x500);
    162   uint32_t control;
    163 } qoriq_usb;
    164 
    165 typedef struct {
    166 } qoriq_tdm_dma;
    167 
    168 typedef struct {
    169   uint32_t dsaddr;
    170   uint32_t blkattr;
    171   uint32_t cmdarg;
    172   uint32_t xfertyp;
    173   uint32_t cmdrsp0;
    174   uint32_t cmdrsp1;
    175   uint32_t cmdrsp2;
    176   uint32_t cmdrsp3;
    177   uint32_t datport;
    178   uint32_t prsstat;
    179   uint32_t proctl;
    180   uint32_t sysctl;
    181   uint32_t irqstat;
    182   uint32_t irqstaten;
    183   uint32_t irqsigen;
    184   uint32_t autoc12err;
    185   uint32_t hostcapblt;
    186   uint32_t wml;
    187   QORIQ_FILL(0x00044, 0x00050, uint32_t);
    188   uint32_t fevt;
    189   QORIQ_FILL(0x00050, 0x000fc, uint32_t);
    190   uint32_t hostver;
    191   QORIQ_FILL(0x000fc, 0x0040c, uint32_t);
    192   uint32_t dcr;
    193 } qoriq_esdhc;
    194 
    195 typedef struct {
    196 } qoriq_sec;
    19736
    19837typedef struct {
     
    329168#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31)
    330169#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31)
     170
     171typedef struct {
     172} qoriq_uart;
     173
     174#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
     175
     176typedef struct {
     177        uint32_t ccsrbarh;
     178        uint32_t ccsrbarl;
     179        uint32_t ccsrar;
     180        uint32_t altcbarh;
     181        uint32_t altcbarl;
     182        uint32_t altcar;
     183        uint32_t bstrh;
     184        uint32_t bstrl;
     185        uint32_t bstar;
     186} qoriq_lcc;
     187
     188#define LCC_BSTAR_EN BSP_BBIT32(0)
     189
     190typedef struct {
     191        uint32_t lawbarh;
     192        uint32_t lawbarl;
     193        uint32_t lawar;
     194        uint32_t reserved_0xc;
     195} qoriq_law;
     196
     197typedef struct {
     198  qoriq_lcc lcc;
     199  QORIQ_FILL(0x000000, 0x000c00, qoriq_lcc);
     200  qoriq_law law [32];
     201  QORIQ_FILL(0x000c00, 0x001000, qoriq_law [32]);
     202  QORIQ_RESERVE(0x001000, 0x040000);
     203  qoriq_pic pic;
     204  QORIQ_FILL(0x040000, 0x070000, qoriq_pic);
     205  QORIQ_RESERVE(0x070000, 0x11c500);
     206  qoriq_uart uart_0;
     207  QORIQ_FILL(0x11c500, 0x11c600, qoriq_uart);
     208  qoriq_uart uart_1;
     209  QORIQ_FILL(0x11c600, 0x11d500, qoriq_uart);
     210  qoriq_uart uart_2;
     211  QORIQ_FILL(0x11d500, 0x11d600, qoriq_uart);
     212  qoriq_uart uart_3;
     213  QORIQ_FILL(0x11d600, 0x11e000, qoriq_uart);
     214  QORIQ_RESERVE(0x11e000, 0x2000000);
     215} qoriq_ccsr;
     216
     217#else /* QORIQ_CHIP_VARIANT */
     218
     219typedef struct {
     220        uint32_t ccsrbar;
     221        uint32_t reserved_0;
     222        uint32_t altcbar;
     223        uint32_t reserved_1;
     224        uint32_t altcar;
     225        uint32_t reserved_2 [3];
     226        uint32_t bptr;
     227} qoriq_lcc;
     228
     229#define CCSRBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
     230#define CCSRBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
     231#define CCSRBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
     232
     233#define ALTCBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
     234#define ALTCBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
     235#define ALTCBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
     236
     237#define ALTCAR_EN BSP_BBIT32(0)
     238#define ALTCAR_TRGT_ID(val) BSP_BFLD32(val, 8, 11)
     239#define ALTCAR_TRGT_ID_GET(reg) BSP_BFLD32GET(reg, 8, 11)
     240#define ALTCAR_TRGT_ID_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
     241
     242#define BPTR_EN BSP_BBIT32(0)
     243#define BPTR_BOOT_PAGE(val) BSP_BFLD32(val, 8, 31)
     244#define BPTR_BOOT_PAGE_GET(reg) BSP_BFLD32GET(reg, 8, 31)
     245#define BPTR_BOOT_PAGE_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
     246
     247typedef struct {
     248        uint32_t bar;
     249        uint32_t reserved_0;
     250        uint32_t ar;
     251        uint32_t reserved_1 [5];
     252} qoriq_law;
     253
     254#define LAWBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 31)
     255#define LAWBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 31)
     256#define LAWBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
     257
     258#define LAWAR_EN BSP_BBIT32(0)
     259#define LAWAR_TRGT(val) BSP_BFLD32(val, 8, 11)
     260#define LAWAR_TRGT_GET(reg) BSP_BFLD32GET(reg, 8, 11)
     261#define LAWAR_TRGT_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
     262#define LAWAR_SIZE(val) BSP_BFLD32(val, 26, 31)
     263#define LAWAR_SIZE_GET(reg) BSP_BFLD32GET(reg, 26, 31)
     264#define LAWAR_SIZE_SET(reg, val) BSP_BFLD32SET(reg, val, 26, 31)
     265
     266typedef struct {
     267} qoriq_ecm;
     268
     269typedef struct {
     270} qoriq_ddr_controller;
     271
     272typedef struct {
     273} qoriq_i2c;
     274
     275typedef struct {
     276} qoriq_local_bus;
     277
     278typedef struct {
     279} qoriq_spi;
     280
     281typedef struct {
     282} qoriq_pci_express;
     283
     284typedef struct {
     285} qoriq_gpio;
     286
     287typedef struct {
     288} qoriq_tdm;
     289
     290typedef struct {
     291} qoriq_l2_cache;
     292
     293typedef struct {
     294} qoriq_dma;
     295
     296typedef struct {
     297  QORIQ_RESERVE(0x000, 0x100);
     298  uint16_t caplength;
     299  uint16_t hciversion;
     300  uint32_t hcsparams;
     301  uint32_t hccparams;
     302  QORIQ_RESERVE(0x10c, 0x120);
     303  uint32_t dciversion;
     304  uint32_t dccparams;
     305  QORIQ_RESERVE(0x128, 0x140);
     306  uint32_t usbcmd;
     307  uint32_t usbsts;
     308  uint32_t usbintr;
     309  uint32_t frindex;
     310  QORIQ_RESERVE(0x150, 0x154);
     311  union {
     312    uint32_t periodiclistbase;
     313    uint32_t deviceaddr;
     314  } perbase_devaddr;
     315  union {
     316    uint32_t asynclistaddr;
     317    uint32_t addr;
     318  } async_addr;
     319  QORIQ_RESERVE(0x15c, 0x160);
     320  uint32_t burstsize;
     321  uint32_t txfilltuning;
     322  QORIQ_RESERVE(0x168, 0x170);
     323  uint32_t viewport;
     324  QORIQ_RESERVE(0x174, 0x180);
     325  uint32_t configflag;
     326  uint32_t portsc1;
     327  QORIQ_RESERVE(0x188, 0x1a8);
     328  uint32_t usbmode;
     329  uint32_t endptsetupstat;
     330  uint32_t endpointprime;
     331  uint32_t endptflush;
     332  uint32_t endptstatus;
     333  uint32_t endptcomplete;
     334  uint32_t endptctrl[6];
     335  QORIQ_RESERVE(0x1d8, 0x400);
     336  uint32_t snoop1;
     337  uint32_t snoop2;
     338  uint32_t age_cnt_thresh;
     339  uint32_t pri_ctrl;
     340  uint32_t si_ctrl;
     341  QORIQ_RESERVE(0x414, 0x500);
     342  uint32_t control;
     343} qoriq_usb;
     344
     345typedef struct {
     346} qoriq_tdm_dma;
     347
     348typedef struct {
     349  uint32_t dsaddr;
     350  uint32_t blkattr;
     351  uint32_t cmdarg;
     352  uint32_t xfertyp;
     353  uint32_t cmdrsp0;
     354  uint32_t cmdrsp1;
     355  uint32_t cmdrsp2;
     356  uint32_t cmdrsp3;
     357  uint32_t datport;
     358  uint32_t prsstat;
     359  uint32_t proctl;
     360  uint32_t sysctl;
     361  uint32_t irqstat;
     362  uint32_t irqstaten;
     363  uint32_t irqsigen;
     364  uint32_t autoc12err;
     365  uint32_t hostcapblt;
     366  uint32_t wml;
     367  QORIQ_FILL(0x00044, 0x00050, uint32_t);
     368  uint32_t fevt;
     369  QORIQ_FILL(0x00050, 0x000fc, uint32_t);
     370  uint32_t hostver;
     371  QORIQ_FILL(0x000fc, 0x0040c, uint32_t);
     372  uint32_t dcr;
     373} qoriq_esdhc;
     374
     375typedef struct {
     376} qoriq_sec;
    331377
    332378typedef struct {
     
    442488} qoriq_ccsr;
    443489
     490#endif /* QORIQ_CHIP_VARIANT */
     491
    444492extern volatile qoriq_ccsr qoriq;
    445493
  • c/src/lib/libbsp/powerpc/qoriq/include/tm27.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
  • c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h

    r3e2647a7 rf2e6c3e  
    11/*
    2  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
    5  *  Obere Lagerstr. 30
     5 *  Dornierstr. 4
    66 *  82178 Puchheim
    77 *  Germany
     
    1616#define LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H
    1717
     18#include <bspopts.h>
     19
     20#define U_BOOT_BOARD_INFO_TEXT_SECTION __attribute__((section(".bsp_start_text")))
     21
     22#define U_BOOT_BOARD_INFO_DATA_SECTION __attribute__((section(".bsp_start_data")))
     23
    1824#define CONFIG_E500
    1925#define CONFIG_HAS_ETH1
  • c/src/lib/libbsp/powerpc/qoriq/include/uart-bridge.h

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2011-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
  • c/src/lib/libbsp/powerpc/qoriq/irq/irq.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
  • c/src/lib/libbsp/powerpc/qoriq/network/network.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    3636#include <bsp/u-boot.h>
    3737#include <bsp/qoriq.h>
     38
     39#if QORIQ_CHIP_VARIANT == QORIQ_CHIP_P1020
    3840
    3941int BSP_tsec_attach(
     
    132134  return tsec_driver_attach_detach(config, attaching);
    133135}
     136
     137#endif /* QORIQ_CHIP_VARIANT */
  • c/src/lib/libbsp/powerpc/qoriq/preinstall.am

    r3e2647a7 rf2e6c3e  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot-board-info.h
    8383
     84$(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h: ../shared/include/u-boot-generic-board-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     85        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h
     86PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h
     87
    8488$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8589        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
     
    146150PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_p1020rdb
    147151
     152$(PROJECT_LIB)/linkcmds.qoriq_t2080rdb: startup/linkcmds.qoriq_t2080rdb $(PROJECT_LIB)/$(dirstamp)
     153        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.qoriq_t2080rdb
     154PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_t2080rdb
     155
     156$(PROJECT_LIB)/linkcmds.qoriq_t4240rdb: startup/linkcmds.qoriq_t4240rdb $(PROJECT_LIB)/$(dirstamp)
     157        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.qoriq_t4240rdb
     158PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_t4240rdb
     159
  • c/src/lib/libbsp/powerpc/qoriq/start/start.S

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    2121 */
    2222
    23 #include <rtems/asm.h>
     23#include <rtems/score/percpu.h>
    2424
    2525#include <bspopts.h>
     
    3030
    3131#define FIRST_TLB 0
    32 #define SCRATCH_TLB 15
     32#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
    3333#define INITIAL_MSR r14
    34 #define UBOOT_BOARD_INFO r15
    3534
    3635        .globl _start
    3736#ifdef RTEMS_SMP
    38         .globl _start_core_1
     37#if QORIQ_THREAD_COUNT > 1
     38        .globl _start_thread
     39#endif
     40        .globl _start_secondary_processor
    3941#endif
    4042        .globl bsp_exc_vector_base
     
    4345
    4446_start:
    45         /* Reset time base */
    46         li      r0, 0
    47         mtspr   TBWU, r0
    48         mtspr   TBWL, r0
     47        bl      .Linit
    4948
    5049#ifdef HAS_UBOOT
    51         mr      UBOOT_BOARD_INFO, r3
     50        bl      bsp_uboot_copy_board_info
    5251#endif /* HAS_UBOOT */
    5352
     
    6867        mtmsr   r0
    6968
    70         /* SPEFSCR initialization */
    71         LWI     r0, QORIQ_INITIAL_SPEFSCR
    72         mtspr   FSL_EIS_SPEFSCR, r0
    73 
    7469        /* Initialize start stack */
    75         LWI     r1, start_stack_end
    76         subi    r1, r1, 16
     70        LWI     r1, start_stack_end - PPC_MINIMUM_STACK_FRAME_SIZE
     71        clrrwi  r1, r1, PPC_STACK_ALIGN_POWER
    7772        li      r0, 0
    7873        stw     r0, 0(r1)
     
    8277        LWI     r4, bsp_section_fast_text_load_begin
    8378        LWI     r5, bsp_section_fast_text_size
    84         bl      copy
     79        bl      .Lcopy
    8580
    8681        /* Copy read-only data */
     
    8883        LWI     r4, bsp_section_rodata_load_begin
    8984        LWI     r5, bsp_section_rodata_size
    90         bl      copy
     85        bl      .Lcopy
    9186
    9287        /* Copy fast data */
     
    9489        LWI     r4, bsp_section_fast_data_load_begin
    9590        LWI     r5, bsp_section_fast_data_size
    96         bl      copy
     91        bl      .Lcopy
    9792
    9893        /* Copy data */
     
    10095        LWI     r4, bsp_section_data_load_begin
    10196        LWI     r5, bsp_section_data_size
    102         bl      copy
     97        bl      .Lcopy
    10398
    10499        /* NULL pointer access protection (only core 0 has to do this) */
    105100        mfspr   r3, BOOKE_PIR
    106101        cmpwi   r3, 0
    107         bne     null_area_setup_done
     102        bne     .Lnull_area_setup_done
    108103        LWI     r3, bsp_section_start_begin
    109104        srawi   r3, r3, 2
     
    111106        li      r3, -4
    112107        LWI     r4, 0x44000002
    113 null_area_setup_loop:
     108.Lnull_area_setup_loop:
    114109        stwu    r4, 4(r3)
    115         bdnz    null_area_setup_loop
    116 null_area_setup_done:
     110        bdnz    .Lnull_area_setup_loop
     111.Lnull_area_setup_done:
    117112
    118113        /* Configure MMU */
     
    134129        bl      bsp_start_zero
    135130
    136 #ifdef HAS_UBOOT
    137         li      r3, SCRATCH_TLB
    138         li      r4, 0
    139         li      r5, 0
    140         li      r6, FSL_EIS_MAS3_SR
    141         li      r7, 0
    142         mr      r8, UBOOT_BOARD_INFO
    143         li      r9, 1
    144         bl      qoriq_tlb1_write
    145         mr      r3, UBOOT_BOARD_INFO
    146         bl      bsp_uboot_copy_board_info
    147         li      r3, SCRATCH_TLB
    148         bl      qoriq_tlb1_invalidate
    149 #endif /* HAS_UBOOT */
    150 
    151131        /* Set up EABI and SYSV environment */
    152132        bl      __eabi
     
    157137        bl      boot_card
    158138
    159 twiddle:
    160         b       twiddle
    161 
    162 copy:
     139.Lcopy:
    163140        cmpw    r3, r4
    164141        beqlr
    165142        b       memcpy
    166143
    167 #ifdef RTEMS_SMP
    168 _start_core_1:
    169 
     144        /* Do not use r3 here, since this could be the U-Boot board info */
     145.Linit:
    170146        /* Reset time base */
    171147        li      r0, 0
     
    173149        mtspr   TBWL, r0
    174150
     151        /* Disable decrementer */
     152        mfspr   r0, BOOKE_TCR
     153        LWI     r4, BOOKE_TCR_DIE
     154        andc    r0, r0, r4
     155        mtspr   BOOKE_TCR, r0
     156
     157#ifdef QORIQ_INITIAL_SPEFSCR
     158        /* SPEFSCR initialization */
     159        LWI     r0, QORIQ_INITIAL_SPEFSCR
     160        mtspr   FSL_EIS_SPEFSCR, r0
     161#endif
     162
     163        /* Set small-data anchors */
     164        LA      r2, _SDA2_BASE_
     165        LA      r13, _SDA_BASE_
     166
     167        blr
     168
     169#ifdef RTEMS_SMP
     170#if QORIQ_THREAD_COUNT > 1
     171_start_thread:
     172        /* Adjust PIR */
     173        mfspr   r0, BOOKE_PIR
     174        srawi   r0, r0, 2
     175        ori     r0, r0, 1
     176        mtspr   BOOKE_PIR, r0
     177
     178        bl      .Linit
     179
     180        /* Initialize start stack */
     181        GET_SELF_CPU_CONTROL    r3
     182        lwz     r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
     183        subi    r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
     184        clrrwi  r1, r1, PPC_STACK_ALIGN_POWER
     185        li      r0, 0
     186        stw     r0, 0(r1)
     187
     188        b       qoriq_start_thread
     189#endif
     190_start_secondary_processor:
     191
     192        bl      .Linit
     193
    175194        /* Get start stack */
    176         subi    r1, r3, 16
     195        mr      r1, r3
    177196
    178197        /* Initial MMU setup */
     
    192211        mtmsr   r0
    193212
    194         /* SPEFSCR initialization */
    195         LWI     r0, QORIQ_INITIAL_SPEFSCR
    196         mtspr   FSL_EIS_SPEFSCR, r0
    197 
    198213        /* Initialize start stack */
     214        subi    r1, r1, PPC_MINIMUM_STACK_FRAME_SIZE
     215        clrrwi  r1, r1, PPC_STACK_ALIGN_POWER
    199216        li      r0, 0
    200217        stw     r0, 0(r1)
     
    208225        bl      qoriq_tlb1_invalidate
    209226
    210         /* Set small-data anchors */
    211         LA      r2, _SDA2_BASE_
    212         LA      r13, _SDA_BASE_
    213 
    214227        b       bsp_start_on_secondary_processor
    215 
    216         b       twiddle
    217228#endif /* RTEMS_SMP */
    218229
  • c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c

    r3e2647a7 rf2e6c3e  
    11/*
    2  * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2015 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    1313 */
    1414
    15 #include <assert.h>
    16 
    1715#include <rtems/score/smpimpl.h>
    1816
     
    2119#include <bsp.h>
    2220#include <bsp/mmu.h>
     21#include <bsp/fatal.h>
    2322#include <bsp/qoriq.h>
    2423#include <bsp/vectors.h>
     
    2928LINKER_SYMBOL(bsp_exc_vector_base);
    3029
    31 void _start_core_1(void);
    32 
    33 #define CORE_COUNT 2
    34 
    35 #define ONE_CORE(core) (1 << (core))
    36 
    37 #define ALL_CORES ((1 << CORE_COUNT) - 1)
     30#if QORIQ_THREAD_COUNT > 1
     31void _start_thread(void);
     32#endif
     33
     34void _start_secondary_processor(void);
    3835
    3936#define IPI_INDEX 0
    4037
    41 #define TLB_BEGIN 8
    42 
    43 #define TLB_END 16
     38#define TLB_BEGIN (3 * QORIQ_TLB1_ENTRY_COUNT / 4)
     39
     40#define TLB_END QORIQ_TLB1_ENTRY_COUNT
    4441
    4542#define TLB_COUNT (TLB_END - TLB_BEGIN)
     
    4946 * U-Boot sources (arch/powerpc/cpu/mpc85xx/release.S).
    5047 */
    51 #if 1
    52   #define BOOT_BEGIN 0x1fff0000
    53   #define BOOT_LAST  0x1fffffff
    54   #define SPIN_TABLE (BOOT_BEGIN + 0xf2a0)
    55 #else
    56   #define BOOT_BEGIN 0x3fff0000
    57   #define BOOT_LAST  0x3fffffff
    58   #define SPIN_TABLE (BOOT_BEGIN + 0xf240)
    59 #endif
    60 
    61 #define TLB_BEGIN 8
    62 
    63 #define TLB_END 16
    64 
    65 #define TLB_COUNT (TLB_END - TLB_BEGIN)
     48#define BOOT_BEGIN U_BOOT_BOOT_PAGE_BEGIN
     49#define BOOT_LAST U_BOOT_BOOT_PAGE_LAST
     50#define SPIN_TABLE (BOOT_BEGIN + U_BOOT_BOOT_PAGE_SPIN_OFFSET)
    6651
    6752typedef struct {
     
    7055  uint32_t r3_upper;
    7156  uint32_t r3_lower;
    72   uint32_t reserved;
     57  uint32_t reserved_0;
    7358  uint32_t pir;
    7459  uint32_t r6_upper;
    7560  uint32_t r6_lower;
     61  uint32_t reserved_1[8];
    7662} uboot_spin_table;
    7763
    78 static uint32_t initial_core_1_stack[4096 / sizeof(uint32_t)];
    79 
    80 static void mmu_config_undo(void)
    81 {
    82   int i = 0;
    83 
    84   for (i = TLB_BEGIN; i < TLB_END; ++i) {
    85     qoriq_tlb1_invalidate(i);
    86   }
    87 }
    88 
    89 static void release_core_1(void)
    90 {
    91   const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1);
    92   uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE;
    93   qoriq_mmu_context mmu_context;
    94 
    95   qoriq_mmu_context_init(&mmu_context);
    96   qoriq_mmu_add(
    97     &mmu_context,
    98     BOOT_BEGIN,
    99     BOOT_LAST,
    100     0,
    101     0,
    102     FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW,
    103     0
     64#if QORIQ_THREAD_COUNT > 1
     65static bool is_started_by_u_boot(uint32_t cpu_index)
     66{
     67  return cpu_index % QORIQ_THREAD_COUNT == 0;
     68}
     69
     70void qoriq_start_thread(void)
     71{
     72  const Per_CPU_Control *cpu_self = _Per_CPU_Get();
     73
     74  ppc_exc_initialize_interrupt_stack(
     75    (uintptr_t) cpu_self->interrupt_stack_low,
     76    rtems_configuration_get_interrupt_stack_size()
    10477  );
    105   qoriq_mmu_partition(&mmu_context, TLB_COUNT);
    106   qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN);
    107 
    108   spin_table->pir = 1;
    109   spin_table->r3_lower = (uint32_t) second_cpu->interrupt_stack_high;
    110   spin_table->addr_upper = 0;
    111   rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
    112   ppc_synchronize_data();
    113   spin_table->addr_lower = (uint32_t) _start_core_1;
    114   rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
    115 
    116   mmu_config_undo();
     78
     79  bsp_interrupt_facility_initialize();
     80
     81  _SMP_Start_multitasking_on_secondary_processor();
     82}
     83#endif
     84
     85static void start_thread_if_necessary(uint32_t cpu_index_self)
     86{
     87#if QORIQ_THREAD_COUNT > 1
     88  uint32_t i;
     89
     90  for (i = 1; i < QORIQ_THREAD_COUNT; ++i) {
     91    uint32_t cpu_index_next = cpu_index_self + i;
     92
     93    if (
     94      is_started_by_u_boot(cpu_index_self)
     95        && cpu_index_next < rtems_configuration_get_maximum_processors()
     96        && _SMP_Should_start_processor(cpu_index_next)
     97    ) {
     98      /* Thread Initial Next Instruction Address (INIA) */
     99      PPC_SET_THREAD_MGMT_REGISTER(321, (uint32_t) _start_thread);
     100
     101      /* Thread Initial Machine State (IMSR) */
     102      PPC_SET_THREAD_MGMT_REGISTER(289, QORIQ_INITIAL_MSR);
     103
     104      /* Thread Enable Set (TENS) */
     105      PPC_SET_SPECIAL_PURPOSE_REGISTER(438, 1U << i);
     106    }
     107  }
     108#endif
    117109}
    118110
    119111void bsp_start_on_secondary_processor(void)
    120112{
    121   const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1);
    122 
    123   /* Disable decrementer */
    124   PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
    125 
    126   /* Initialize exception handler */
     113  uint32_t cpu_index_self = _SMP_Get_current_processor();
     114  const Per_CPU_Control *cpu_self = _Per_CPU_Get_by_index(cpu_index_self);
     115
    127116  ppc_exc_initialize_with_vector_base(
    128     (uintptr_t) second_cpu->interrupt_stack_low,
     117    (uintptr_t) cpu_self->interrupt_stack_low,
    129118    rtems_configuration_get_interrupt_stack_size(),
    130119    bsp_exc_vector_base
     
    138127  );
    139128
    140   /* Initialize interrupt support */
    141129  bsp_interrupt_facility_initialize();
    142130
    143   bsp_interrupt_vector_enable(QORIQ_IRQ_IPI_0);
     131  start_thread_if_necessary(cpu_index_self);
    144132
    145133  _SMP_Start_multitasking_on_secondary_processor();
     
    153141uint32_t _CPU_SMP_Initialize(void)
    154142{
    155   return CORE_COUNT;
     143  if (rtems_configuration_get_maximum_processors() > 0) {
     144    qoriq_mmu_context mmu_context;
     145
     146    qoriq_mmu_context_init(&mmu_context);
     147    qoriq_mmu_add(
     148      &mmu_context,
     149      BOOT_BEGIN,
     150      BOOT_LAST,
     151      0,
     152      0,
     153      FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW,
     154      0
     155    );
     156    qoriq_mmu_partition(&mmu_context, TLB_COUNT);
     157    qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN);
     158  }
     159
     160  start_thread_if_necessary(0);
     161
     162  return QORIQ_CPU_COUNT;
     163}
     164
     165static void release_processor(uboot_spin_table *spin_table, uint32_t cpu_index)
     166{
     167  const Per_CPU_Control *cpu = _Per_CPU_Get_by_index(cpu_index);
     168
     169  spin_table->pir = cpu_index;
     170  spin_table->r3_lower = (uint32_t) cpu->interrupt_stack_high;
     171  spin_table->addr_upper = 0;
     172  rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
     173  ppc_synchronize_data();
     174  spin_table->addr_lower = (uint32_t) _start_secondary_processor;
     175  rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
    156176}
    157177
    158178bool _CPU_SMP_Start_processor(uint32_t cpu_index)
    159179{
    160   (void) cpu_index;
    161 
    162   release_core_1();
     180#if QORIQ_THREAD_COUNT > 1
     181  if (is_started_by_u_boot(cpu_index)) {
     182    uboot_spin_table *spin_table =
     183      &((uboot_spin_table *) SPIN_TABLE)[cpu_index / 2 - 1];
     184
     185    release_processor(spin_table, cpu_index);
     186
     187    return true;
     188  } else {
     189    return _SMP_Should_start_processor(cpu_index - 1);
     190  }
     191#else
     192  uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE;
     193
     194  release_processor(spin_table, cpu_index);
    163195
    164196  return true;
     197#endif
     198}
     199
     200static void mmu_config_undo(void)
     201{
     202  int i;
     203
     204  for (i = TLB_BEGIN; i < TLB_END; ++i) {
     205    qoriq_tlb1_invalidate(i);
     206  }
    165207}
    166208
    167209void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
    168210{
     211  if (rtems_configuration_get_maximum_processors() > 0) {
     212    mmu_config_undo();
     213  }
     214
    169215  if (cpu_count > 1) {
    170216    rtems_status_code sc;
     
    177223      NULL
    178224    );
    179     assert(sc == RTEMS_SUCCESSFUL);
     225    if (sc != RTEMS_SUCCESSFUL) {
     226      bsp_fatal(QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL);
     227    }
    180228  }
    181229}
     
    183231void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
    184232{
    185   uint32_t self = ppc_processor_id();
    186   qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg =
    187     ONE_CORE(target_processor_index);
    188 }
     233  qoriq.pic.ipidr [IPI_INDEX].reg = 1U << target_processor_index;
     234}
  • c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c

    r3e2647a7 rf2e6c3e  
    8888  /* Initialize some device driver parameters */
    8989  #ifdef HAS_UBOOT
    90     BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
    91     bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000;
     90    BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq
     91      / QORIQ_BUS_CLOCK_DIVIDER;
     92    bsp_clicks_per_usec = BSP_bus_frequency / 8000000;
    9293    rtems_counter_initialize_converter(bsp_uboot_board_info.bi_intfreq);
    9394  #endif /* HAS_UBOOT */
     
    109110
    110111      #ifdef HAS_UBOOT
    111         ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
     112        #ifdef U_BOOT_GENERIC_BOARD_INFO
     113          ctx->initial_baud = 115200;
     114        #else
     115          ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
     116        #endif
    112117      #endif
    113118    }
    114119  }
    115 
    116   /* Disable decrementer */
    117   PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
    118120
    119121  /* Initialize exception handler */
     
    135137
    136138  /* Disable boot page translation */
     139#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
     140  qoriq.lcc.bstar &= ~LCC_BSTAR_EN;
     141#else
    137142  qoriq.lcc.bptr &= ~BPTR_EN;
     143#endif
    138144}
  • c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2011-2013 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    106106        qoriq_mmu_context_init(&context);
    107107
    108         for (i = 0; i < 16; ++i) {
     108        for (i = 0; i < QORIQ_TLB1_ENTRY_COUNT; ++i) {
    109109                if (i != scratch_tlb) {
    110110                        qoriq_tlb1_invalidate(i);
     
    127127        }
    128128
    129         qoriq_mmu_partition(&context, 8);
     129        qoriq_mmu_partition(&context, (3 * QORIQ_TLB1_ENTRY_COUNT) / 4);
    130130        qoriq_mmu_write_to_tlb1(&context, first_tlb);
    131131}
  • c/src/lib/libbsp/powerpc/qoriq/startup/mmu.c

    r3e2647a7 rf2e6c3e  
    88
    99/*
    10  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    3737                test_power += QORIQ_MMU_POWER_STEP;
    3838        }
     39
     40        return power;
     41}
     42
     43static uint32_t TEXT max_power_of_two(uint32_t val)
     44{
     45        uint32_t test_power = QORIQ_MMU_MIN_POWER;
     46        uint32_t power = test_power;
     47        uint32_t max = 1U << test_power;
     48
     49        do {
     50                power = test_power;
     51                max <<= QORIQ_MMU_POWER_STEP;
     52                test_power += QORIQ_MMU_POWER_STEP;
     53        } while (test_power <= QORIQ_MMU_MAX_POWER && max <= val);
    3954
    4055        return power;
     
    151166static bool TEXT is_full(qoriq_mmu_context *self)
    152167{
    153         return self->count >= QORIQ_MMU_ENTRY_COUNT;
     168        return self->count >= QORIQ_TLB1_ENTRY_COUNT;
    154169}
    155170
     
    209224        uint32_t size = end - begin;
    210225        uint32_t begin_power = power_of_two(begin);
    211         uint32_t end_power = power_of_two(end);
    212         uint32_t size_power = power_of_two(size);
    213         uint32_t power = min(begin_power, min(end_power, size_power));
     226        uint32_t size_power = max_power_of_two(size);
     227        uint32_t power = min(begin_power, size_power);
    214228        uint32_t split_size = power < 32 ? (1U << power) : 0;
    215229        uint32_t split_pos = begin + split_size;
  • c/src/lib/libbsp/shared/include/fatal.h

    r3e2647a7 rf2e6c3e  
    11/*
    2  * Copyright (c) 2012-2014 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2012-2015 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    112112  ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9),
    113113  ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS,
    114   ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG
     114  ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG,
     115
     116  /* QorIQ fatal codes */
     117  QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL = BSP_FATAL_CODE_BLOCK(10)
    115118} bsp_fatal_code;
    116119
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