Changeset f278329 in rtems


Ignore:
Timestamp:
Dec 1, 2007, 9:59:20 PM (12 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
a3ae5896
Parents:
34fb3635
Message:

2007-12-01 Till Straumann <strauman@…>

  • shared/irq/openpic_i8259_irq.c:
  • conditionally define 'irq_mask_or_tbl' only if BSP_PCI_ISA_BRIDGE_IRQ is defined.
  • use _ISR_Get_level() / _ISR_Set_level() for re-enabling interrupts rather than messing with MSR directly; these macros:

o implement compiler memory barrier

o will handle multiple levels (e500 'critical' interrupts)

if they are ever supported.

  • decrementer irqs are also shareable - added list traversal.
Location:
c/src/lib/libbsp/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    r34fb3635 rf278329  
     12007-12-01      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * shared/irq/openpic_i8259_irq.c:
     4        - conditionally define 'irq_mask_or_tbl' only if
     5          BSP_PCI_ISA_BRIDGE_IRQ is defined.
     6        - use _ISR_Get_level() / _ISR_Set_level() for re-enabling
     7          interrupts rather than messing with MSR directly;
     8          these macros:
     9            o implement compiler memory barrier
     10                o will handle multiple levels (e500 'critical' interrupts)
     11                  if they are ever supported.
     12        - decrementer irqs are also shareable - added list traversal.
     13
    1142007-12-01      Till Straumann <strauman@slac.stanford.edu>
    215
  • c/src/lib/libbsp/powerpc/shared/irq/openpic_i8259_irq.c

    r34fb3635 rf278329  
    2727#define RAVEN_INTR_ACK_REG 0xfeff0030
    2828
     29#ifdef BSP_PCI_ISA_BRIDGE_IRQ
    2930/*
    3031 * pointer to the mask representing the additionnal irq vectors
     
    3637 */
    3738rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
     39#endif
    3840
    3941/*
     
    207209
    208210unsigned BSP_spuriousIntr = 0;
    209 /*
    210  * High level IRQ handler called from shared_raw_irq_code_entry
    211  */
    212 void C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
    213 {
    214   register unsigned int irq;
    215 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
    216   register unsigned isaIntr;                  /* boolean */
    217   register unsigned oldMask = 0;              /* old isa pic masks */
    218   register unsigned newMask;                  /* new isa pic masks */
    219 #endif
    220   register unsigned msr;
    221   register unsigned new_msr;
    222 
    223   if (excNum == ASM_DEC_VECTOR) {
    224     _CPU_MSR_GET(msr);
    225     new_msr = msr | MSR_EE;
    226     _CPU_MSR_SET(new_msr);
    227 
    228     rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
    229 
    230     _CPU_MSR_SET(msr);
    231     return;
    232 
    233   }
    234   irq = openpic_irq(0);
    235   if (irq == OPENPIC_VEC_SPURIOUS) {
    236     ++BSP_spuriousIntr;
    237     return;
    238   }
    239 
    240   /* some BSPs might want to use a different numbering... */
    241   irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
    242 
    243 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
    244   isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
    245   if (isaIntr)  {
    246     /*
    247      * Acknowledge and read 8259 vector
    248      */
    249     irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
    250     /*
    251      * store current PIC mask
    252      */
    253     oldMask = i8259s_cache;
    254     newMask = oldMask | irq_mask_or_tbl [irq];
    255     i8259s_cache = newMask;
    256     outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
    257     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    258     BSP_irq_ack_at_i8259s (irq);
    259     openpic_eoi(0);
    260   }
    261 #endif
    262   _CPU_MSR_GET(msr);
    263   new_msr = msr | MSR_EE;
    264   _CPU_MSR_SET(new_msr);
     211
     212static inline void
     213dispatch_list(unsigned int irq)
     214{
     215register uint32_t       l_orig;
     216
     217        l_orig = _ISR_Get_level();
     218
     219        /* Enable all interrupts */
     220        _ISR_Set_level(0);
    265221
    266222  /* rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); */
     
    275231  }
    276232
    277   _CPU_MSR_SET(msr);
     233  /* Restore original level */
     234  _ISR_Set_level(l_orig);
     235}
     236/*
     237 * High level IRQ handler called from shared_raw_irq_code_entry
     238 */
     239void C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
     240{
     241  register unsigned int irq;
     242#ifdef BSP_PCI_ISA_BRIDGE_IRQ
     243  register unsigned isaIntr;                  /* boolean */
     244  register unsigned oldMask = 0;              /* old isa pic masks */
     245  register unsigned newMask;                  /* new isa pic masks */
     246#endif
     247
     248  if (excNum == ASM_DEC_VECTOR) {
     249
     250        dispatch_list(BSP_DECREMENTER);
     251
     252    return;
     253
     254  }
     255  irq = openpic_irq(0);
     256  if (irq == OPENPIC_VEC_SPURIOUS) {
     257    ++BSP_spuriousIntr;
     258    return;
     259  }
     260
     261  /* some BSPs might want to use a different numbering... */
     262  irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
     263
     264#ifdef BSP_PCI_ISA_BRIDGE_IRQ
     265  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
     266  if (isaIntr)  {
     267    /*
     268     * Acknowledge and read 8259 vector
     269     */
     270    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
     271    /*
     272     * store current PIC mask
     273     */
     274    oldMask = i8259s_cache;
     275    newMask = oldMask | irq_mask_or_tbl [irq];
     276    i8259s_cache = newMask;
     277    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
     278    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
     279    BSP_irq_ack_at_i8259s (irq);
     280    openpic_eoi(0);
     281  }
     282#endif
     283
     284  /* dispatch handlers */
     285  dispatch_list(irq);
    278286
    279287#ifdef BSP_PCI_ISA_BRIDGE_IRQ
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