Changeset f22bba3 in rtems for c/src/lib/libbsp/arm/lm3s69xx
- Timestamp:
- 04/26/13 09:03:59 (11 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 024a572
- Parents:
- b7cf1ff7
- git-author:
- Eugeniy Meshcheryakov <eugen@…> (04/26/13 09:03:59)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (04/26/13 09:03:59)
- Location:
- c/src/lib/libbsp/arm/lm3s69xx
- Files:
-
- 10 added
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/lm3s69xx/Makefile.am
rb7cf1ff7 rf22bba3 19 19 project_lib_DATA += startup/linkcmds 20 20 21 EXTRA_DIST = startup/linkcmds.lm3s6965 21 EXTRA_DIST = startup/linkcmds.lm3s6965 startup/linkcmds.lm3s6965_qemu startup/linkcmds.lm3s3749 22 22 23 23 ############################################################################### … … 46 46 include_bsp_HEADERS += include/irq.h 47 47 include_bsp_HEADERS += include/uart.h 48 include_bsp_HEADERS += include/io.h 49 include_bsp_HEADERS += include/syscon.h 50 include_bsp_HEADERS += include/ssi.h 48 51 include_bsp_HEADERS += include/lm3s69xx.h 49 52 … … 76 79 libbsp_a_SOURCES += startup/bspstarthook.c 77 80 libbsp_a_SOURCES += startup/bspreset.c 81 libbsp_a_SOURCES += startup/io.c 82 libbsp_a_SOURCES += startup/syscon.c 78 83 79 84 # IRQ … … 108 113 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include 109 114 115 # SSI 116 libbsp_a_SOURCES += ssi/ssi.c 117 110 118 ############################################################################### 111 119 # Special Rules # -
c/src/lib/libbsp/arm/lm3s69xx/configure.ac
rb7cf1ff7 rf22bba3 22 22 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") 23 23 24 RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[]) 24 RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*_qemu],[]) 25 RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[1]) 25 26 RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands]) 26 27 27 RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[*],[50000000 ])28 RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[*],[50000000U]) 28 29 RTEMS_BSPOPTS_HELP([LM3S69XX_SYSTEM_CLOCK],[system clock in Hz]) 29 30 30 RTEMS_BSPOPTS_SET([LM3S69XX_UART_BAUD],[*],[115200]) 31 RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s6965*],[0xE]) dnl 8MHz XTAL 32 RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s3749*],[0x10]) dnl 10MHz XTAL 33 RTEMS_BSPOPTS_HELP([LM3S69XX_XTAL_CONFIG],[crystal configuration for RCC register]) 34 35 RTEMS_BSPOPTS_SET([LM3S69XX_SSI_CLOCK],[*],[1000000U]) 36 RTEMS_BSPOPTS_HELP([LM3S69XX_SSI_CLOCK],[SSI clock in Hz]) 37 38 RTEMS_BSPOPTS_SET([LM3S69XX_UART_BAUD],[*],[115200U]) 31 39 RTEMS_BSPOPTS_HELP([LM3S69XX_UART_BAUD],[baud for UARTs]) 32 40 … … 40 48 RTEMS_BSPOPTS_HELP([LM3S69XX_ENABLE_UART_2],[enable UART 2]) 41 49 50 RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s3749*],[8]) 51 RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s6965*],[7]) 52 RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_GPIO_BLOCKS],[number of GPIO blocks supported by MCU]) 53 54 RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s3749*],[2]) 55 RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s6965*],[1]) 56 RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_SSI_BLOCKS],[number of SSI blocks supported by MCU]) 57 58 RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[lm3s3749*],[1]) 59 RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[*],[0]) 60 RTEMS_BSPOPTS_HELP([LM3S69XX_HAS_UDMA],[defined if MCU supports UDMA]) 61 62 RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[lm3s3749*],[1]) 63 RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[*],[0]) 64 RTEMS_BSPOPTS_HELP([LM3S69XX_USE_AHB_FOR_GPIO],[use AHB apperture to access GPIO registers]) 65 66 RTEMS_BSPOPTS_SET([LM3S69XX_MCU_LM3S3749],[lm3s3749*],[1]) 67 RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM3S3749],[board has LM3S3749 MCU]) 68 69 RTEMS_BSPOPTS_SET([LM3S69XX_MCU_LM3S6965],[lm3s6965*],[1]) 70 RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM3S6965],[board has LM3S6965 MCU]) 71 42 72 RTEMS_BSP_CLEANUP_OPTIONS(0, 0) 43 73 RTEMS_BSP_LINKCMDS -
c/src/lib/libbsp/arm/lm3s69xx/console/console-config.c
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 3 * 2 4 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 5 * … … 30 32 .ulCtrlPort1 = LM3S69XX_UART_0_BASE, 31 33 .ulClock = LM3S69XX_UART_BAUD, 32 .ulIntVector = LM3S69XX_IRQ_UART_0 34 .ulIntVector = LM3S69XX_IRQ_UART_0, 35 .pDeviceParams = (void *)0 33 36 }, 34 37 #endif … … 40 43 .ulCtrlPort1 = LM3S69XX_UART_1_BASE, 41 44 .ulClock = LM3S69XX_UART_BAUD, 42 .ulIntVector = LM3S69XX_IRQ_UART_1 45 .ulIntVector = LM3S69XX_IRQ_UART_1, 46 .pDeviceParams = (void *)1 43 47 } 44 48 #endif … … 50 54 .ulCtrlPort1 = LM3S69XX_UART_2_BASE, 51 55 .ulClock = LM3S69XX_UART_BAUD, 52 .ulIntVector = LM3S69XX_IRQ_UART_2 56 .ulIntVector = LM3S69XX_IRQ_UART_2, 57 .pDeviceParams = (void *)2 53 58 } 54 59 #endif … … 65 70 const console_fns *con = 66 71 Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; 67 72 68 73 if (c == '\n') { 69 74 con->deviceWritePolled((int) Console_Port_Minor, '\r'); -
c/src/lib/libbsp/arm/lm3s69xx/console/uart.c
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 3 * 2 4 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 5 * … … 16 18 #include <bsp/uart.h> 17 19 #include <libchip/sersupp.h> 20 #include <bsp/syscon.h> 21 #include <bsp/lm3s69xx.h> 18 22 19 23 static volatile lm3s69xx_uart *get_uart_regs(int minor) … … 24 28 } 25 29 30 static unsigned int get_uart_number(int minor) 31 { 32 console_tbl *ct = Console_Port_Tbl [minor]; 33 34 return (unsigned int)ct->pDeviceParams; 35 } 36 37 /* 38 * Returns both integer and fractional parts as one number. 39 */ 40 static uint32_t get_baud_div(uint32_t baud) 41 { 42 uint32_t clock4 = LM3S69XX_SYSTEM_CLOCK * 4; 43 return (clock4 + baud - 1) / baud; 44 } 45 26 46 static void initialize(int minor) 27 47 { 28 48 volatile lm3s69xx_uart *uart = get_uart_regs(minor); 49 unsigned int num = get_uart_number(minor); 50 51 lm3s69xx_syscon_enable_uart_clock(num, true); 29 52 30 53 uart->ctl = 0; 54 55 uint32_t brd = get_baud_div(LM3S69XX_UART_BAUD); 56 uart->ibrd = brd / 64; 57 uart->fbrd = brd % 64; 58 31 59 uart->lcrh = UARTLCRH_WLEN(0x3) | UARTLCRH_FEN; 32 60 uart->ctl = UARTCTL_RXE | UARTCTL_TXE | UARTCTL_UARTEN; -
c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h
rb7cf1ff7 rf22bba3 24 24 #define BSP_ARMV7M_SYSTICK_PRIORITY (6 << 5) 25 25 26 #define BSP_ARMV7M_SYSTICK_FREQUENCY LM3S69XX_SYSTEM_CLOCK 27 26 28 #ifndef ASM 27 29 … … 32 34 #include <rtems/clockdrv.h> 33 35 34 #ifdef __cplusplus35 extern "C" {36 #endif /* __cplusplus */37 38 #ifdef __cplusplus39 }40 #endif /* __cplusplus */41 42 36 #endif /* ASM */ 43 37 -
c/src/lib/libbsp/arm/lm3s69xx/include/irq.h
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 3 * 2 4 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 5 * … … 21 23 #include <rtems/irq.h> 22 24 #include <rtems/irq-extension.h> 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 #ifdef __cplusplus 29 } 30 #endif /* __cplusplus */ 25 #include <bspopts.h> 31 26 32 27 #endif /* ASM */ 33 28 34 #define LM3S69XX_IRQ_GPIO_PORT_A 16 35 #define LM3S69XX_IRQ_GPIO_PORT_B 17 36 #define LM3S69XX_IRQ_GPIO_PORT_C 18 37 #define LM3S69XX_IRQ_GPIO_PORT_D 19 38 #define LM3S69XX_IRQ_GPIO_PORT_E 20 39 #define LM3S69XX_IRQ_UART_0 21 40 #define LM3S69XX_IRQ_UART_1 22 41 #define LM3S69XX_IRQ_SSI_0 23 42 #define LM3S69XX_IRQ_I2C_0 24 43 #define LM3S69XX_IRQ_PWM_GENERATOR_0 26 44 #define LM3S69XX_IRQ_PWM_GENERATOR_1 27 45 #define LM3S69XX_IRQ_PWM_GENERATOR_2 28 46 #define LM3S69XX_IRQ_QEI_0 29 47 #define LM3S69XX_IRQ_ADC0_SEQUENCE_0 30 48 #define LM3S69XX_IRQ_ADC0_SEQUENCE_1 31 49 #define LM3S69XX_IRQ_ADC0_SEQUENCE_2 32 50 #define LM3S69XX_IRQ_ADC0_SEQUENCE_3 33 51 #define LM3S69XX_IRQ_WATCHDOG_TIMER_0 34 52 #define LM3S69XX_IRQ_TIMER_0_A 35 53 #define LM3S69XX_IRQ_TIMER_0_B 36 54 #define LM3S69XX_IRQ_TIMER_1_A 37 55 #define LM3S69XX_IRQ_TIMER_1_B 38 56 #define LM3S69XX_IRQ_TIMER_2_A 39 57 #define LM3S69XX_IRQ_TIMER_2_B 40 58 #define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 41 59 #define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 42 60 #define LM3S69XX_IRQ_SYSTEM_CONTROL 44 61 #define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 45 62 #define LM3S69XX_IRQ_GPIO_PORT_F 46 63 #define LM3S69XX_IRQ_GPIO PORT_G 47 64 #define LM3S69XX_IRQ_UART_2 49 65 #define LM3S69XX_IRQ_TIMER_3_A 51 66 #define LM3S69XX_IRQ_TIMER_3_B 52 67 #define LM3S69XX_IRQ_I2C_1 53 68 #define LM3S69XX_IRQ_QEI_1 54 69 #define LM3S69XX_IRQ_ETHERNET_CONTROLLER 58 70 #define LM3S69XX_IRQ_HIBERNATION_MODULE 59 29 #define LM3S69XX_IRQ_GPIO_PORT_A 0 30 #define LM3S69XX_IRQ_GPIO_PORT_B 1 31 #define LM3S69XX_IRQ_GPIO_PORT_C 2 32 #define LM3S69XX_IRQ_GPIO_PORT_D 3 33 #define LM3S69XX_IRQ_GPIO_PORT_E 4 34 #define LM3S69XX_IRQ_UART_0 5 35 #define LM3S69XX_IRQ_UART_1 6 36 #define LM3S69XX_IRQ_SSI_0 7 37 #define LM3S69XX_IRQ_I2C_0 8 38 #define LM3S69XX_IRQ_PWM_FAULT 9 39 #define LM3S69XX_IRQ_PWM_GENERATOR_0 10 40 #define LM3S69XX_IRQ_PWM_GENERATOR_1 11 41 #define LM3S69XX_IRQ_PWM_GENERATOR_2 12 42 #define LM3S69XX_IRQ_QEI_0 13 43 #define LM3S69XX_IRQ_ADC0_SEQUENCE_0 14 44 #define LM3S69XX_IRQ_ADC0_SEQUENCE_1 15 45 #define LM3S69XX_IRQ_ADC0_SEQUENCE_2 16 46 #define LM3S69XX_IRQ_ADC0_SEQUENCE_3 17 47 #define LM3S69XX_IRQ_WATCHDOG_TIMER_0 18 48 #define LM3S69XX_IRQ_TIMER_0_A 19 49 #define LM3S69XX_IRQ_TIMER_0_B 20 50 #define LM3S69XX_IRQ_TIMER_1_A 21 51 #define LM3S69XX_IRQ_TIMER_1_B 22 52 #define LM3S69XX_IRQ_TIMER_2_A 23 53 #define LM3S69XX_IRQ_TIMER_2_B 24 54 #define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 25 55 #define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 26 56 #define LM3S69XX_IRQ_SYSTEM_CONTROL 28 57 #define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 29 58 #define LM3S69XX_IRQ_GPIO_PORT_F 30 59 #define LM3S69XX_IRQ_GPIO PORT_G 31 60 /* NOTE: lm3s3749 */ 61 #define LM3S69XX_IRQ_GPIO PORT_H 32 62 #define LM3S69XX_IRQ_UART_2 33 63 /* NOTE: lm3s3749 */ 64 #define LM3S69XX_IRQ_SSI_1 34 65 #define LM3S69XX_IRQ_TIMER_3_A 35 66 #define LM3S69XX_IRQ_TIMER_3_B 36 67 #define LM3S69XX_IRQ_I2C_1 37 68 69 /* NOTE: lm3s6965 */ 70 #define LM3S69XX_IRQ_QEI_1 38 71 #define LM3S69XX_IRQ_ETHERNET_CONTROLLER 42 72 73 #define LM3S69XX_IRQ_HIBERNATION_MODULE 43 74 75 /* NOTE: lm3s3749 */ 76 #define LM3S69XX_IRQ_USB 44 77 #define LM3S69XX_IRQ_PWM_GENERATOR_3 45 78 #define LM3S69XX_IRQ_UDMA_SOFTWARE 46 79 #define LM3S69XX_IRQ_UDMA_ERROR 47 71 80 72 81 #define LM3S69XX_IRQ_PRIORITY_VALUE_MIN 0 … … 77 86 78 87 #define BSP_INTERRUPT_VECTOR_MIN 0 79 #define BSP_INTERRUPT_VECTOR_MAX 59 88 /* NOTE: for lm3s6965 - 43 */ 89 #define BSP_INTERRUPT_VECTOR_MAX 47 80 90 81 91 #endif /* LIBBSP_ARM_LM3S69XX_IRQ_H */ -
c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 3 * 2 4 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 5 * … … 15 17 #ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H 16 18 #define LIBBSP_ARM_LM3S69XX_LM3S69XX_H 17 18 #i fdef __cplusplus19 extern "C" { 20 # endif /* __cplusplus */19 #include <bspopts.h> 20 #include <bsp/utility.h> 21 22 #define LM3S69XX_SYSCON_BASE 0x400fe000 21 23 22 24 #define LM3S69XX_UART_0_BASE 0x4000c000 … … 24 26 #define LM3S69XX_UART_2_BASE 0x4000e000 25 27 26 #ifdef __cplusplus 27 } 28 #endif /* __cplusplus */ 28 #ifdef LM3S69XX_USE_AHB_FOR_GPIO 29 #define LM3S69XX_GPIO_A_BASE 0x40058000 30 #define LM3S69XX_GPIO_B_BASE 0x40059000 31 #define LM3S69XX_GPIO_C_BASE 0x4005a000 32 #define LM3S69XX_GPIO_D_BASE 0x4005b000 33 #define LM3S69XX_GPIO_E_BASE 0x4005c000 34 #define LM3S69XX_GPIO_F_BASE 0x4005d000 35 #define LM3S69XX_GPIO_G_BASE 0x4005e000 36 #if LM3S69XX_NUM_GPIO_BLOCKS > 7 37 #define LM3S69XX_GPIO_H_BASE 0x4005f000 38 #endif 39 40 #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) 41 #else /* LM3S69XX_USE_AHB_FOR_GPIO */ 42 #define LM3S69XX_GPIO_A_BASE 0x40004000 43 #define LM3S69XX_GPIO_B_BASE 0x40005000 44 #define LM3S69XX_GPIO_C_BASE 0x40006000 45 #define LM3S69XX_GPIO_D_BASE 0x40007000 46 #define LM3S69XX_GPIO_E_BASE 0x40024000 47 #define LM3S69XX_GPIO_F_BASE 0x40025000 48 #define LM3S69XX_GPIO_G_BASE 0x40026000 49 #if LM3S69XX_NUM_GPIO_BLOCKS > 7 50 #define LM3S69XX_GPIO_H_BASE 0x40027000 51 #endif 52 53 #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ 54 (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ 55 (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) 56 #endif /* LM3S69XX_USE_AHB_FOR_GPIO */ 57 58 #define LM3S69XX_SSI_0_BASE 0x40008000 59 #if LM3S69XX_NUM_SSI_BLOCKS > 1 60 #define LM3S69XX_SSI_1_BASE 0x40009000 61 #endif 62 63 #define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) 64 65 #define LM3S69XX_PLL_FREQUENCY 400000000U 66 67 typedef struct { 68 uint32_t data[256]; /* Masked data registers are included here. */ 69 uint32_t dir; 70 uint32_t is; 71 uint32_t ibe; 72 uint32_t iev; 73 uint32_t im; 74 uint32_t ris; 75 uint32_t mis; 76 uint32_t icr; 77 uint32_t afsel; 78 79 uint32_t reserved_0[55]; 80 81 uint32_t dr2r; 82 uint32_t dr4r; 83 uint32_t dr8r; 84 uint32_t odr; 85 uint32_t pur; 86 uint32_t pdr; 87 uint32_t slr; 88 uint32_t den; 89 uint32_t lock; 90 uint32_t cr; 91 uint32_t amsel; 92 } lm3s69xx_gpio; 93 94 typedef struct { 95 uint32_t did0; 96 uint32_t did1; 97 98 uint32_t dc0; 99 uint32_t reserved_0; 100 uint32_t dc1; 101 uint32_t dc2; 102 uint32_t dc3; 103 uint32_t dc4; 104 uint32_t dc5; 105 uint32_t dc6; 106 uint32_t dc7; 107 108 uint32_t reserved_1; 109 110 #define SYSCONPBORCTL_BORIOR BSP_BIT32(1) 111 uint32_t pborctl; 112 113 #define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) 114 #define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) 115 uint32_t ldopctl; 116 117 uint32_t reserved_2[2]; 118 119 uint32_t srcr0; 120 uint32_t srcr1; 121 uint32_t srcr2; 122 123 uint32_t reserved_3; 124 125 #define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) 126 #define SYSCONRIS_USBPLLRIS BSP_BIT32(7) 127 #define SYSCONRIS_PLLLRIS BSP_BIT32(6) 128 #define SYSCONRIS_BORRIS BSP_BIT32(1) 129 uint32_t ris; 130 131 #define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) 132 #define SYSCONIMC_USBPLLLIM BSP_BIT32(7) 133 #define SYSCONIMC_PLLLIM BSP_BIT32(6) 134 #define SYSCONIMC_BORIM BSP_BIT32(1) 135 uint32_t imc; 136 137 #define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) 138 #define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) 139 #define SYSCONMISC_PLLLMIS BSP_BIT32(6) 140 #define SYSCONMISC_BORMIS BSP_BIT32(1) 141 uint32_t misc; 142 143 #define SYSCONRESC_MOSCFAIL BSP_BIT32(16) 144 #define SYSCONRESC_SW BSP_BIT32(4) 145 #define SYSCONRESC_WDT BSP_BIT32(3) 146 #define SYSCONRESC_BOR BSP_BIT32(2) 147 #define SYSCONRESC_POR BSP_BIT32(1) 148 #define SYSCONRESC_EXT BSP_BIT32(0) 149 uint32_t resc; 150 151 #define SYSCONRCC_AGC BSP_BIT32(27) 152 #define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) 153 #define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) 154 #define SYSCONRCC_USESYSDIV BSP_BIT32(22) 155 #define SYSCONRCC_USEPWMDIV BSP_BIT32(20) 156 #define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) 157 #define SYSCONRCC_PWMDIV_DIV2_VAL 0 158 #define SYSCONRCC_PWMDIV_DIV4_VAL 1 159 #define SYSCONRCC_PWMDIV_DIV8_VAL 2 160 #define SYSCONRCC_PWMDIV_DIV16_VAL 3 161 #define SYSCONRCC_PWMDIV_DIV32_VAL 4 162 #define SYSCONRCC_PWMDIV_DIV64_VAL 5 163 #define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) 164 #define SYSCONRCC_PWRDN BSP_BIT32(13) 165 #define SYSCONRCC_BYPASS BSP_BIT32(11) 166 #define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) 167 #define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) 168 #define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) 169 #define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) 170 #define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) 171 #define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) 172 #define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) 173 #define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) 174 #define SYSCONRCC_IOSCDIS BSP_BIT32(1) 175 #define SYSCONRCC_MOSCDIS BSP_BIT32(0) 176 uint32_t rcc; 177 178 #define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) 179 #define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) 180 #define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) 181 #define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) 182 uint32_t pllcfg; 183 184 uint32_t reserved_4; 185 186 #define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) 187 #define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) 188 #define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) 189 #define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) 190 #define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) 191 #define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) 192 #define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) 193 #define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) 194 uint32_t gpiohbctl; 195 196 #define SYSCONRCC2_USERCC2 BSP_BIT32(31) 197 #define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) 198 #define SYSCONRCC2_SYSDIV2_MSK(val) BSP_MSK32(23, 28) 199 #define SYSCONRCC2_USBPWRDN BSP_BIT32(14) 200 #define SYSCONRCC2_PWRDN2 BSP_BIT32(13) 201 #define SYSCONRCC2_BYPASS2 BSP_BIT32(11) 202 #define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) 203 #define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) 204 uint32_t rcc2; 205 206 uint32_t reserved_5[2]; 207 208 #define SYSCONMOSCCTL_CVAL BSP_BIT32(0) 209 uint32_t moscctl; 210 211 uint32_t reserved_6[32]; 212 213 #define SYSCONRCGC0_PWM BSP_BIT32(20) 214 #define SYSCONRCGC0_ADC BSP_BIT32(16) 215 #define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) 216 #define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) 217 #define SYSCONRCGC0_HIB BSP_BIT32(6) 218 #define SYSCONRCGC0_WDT BSP_BIT32(3) 219 uint32_t rcgc0; 220 221 #define SYSCONRCGC1_COMP1 BSP_BIT32(25) 222 #define SYSCONRCGC1_COMP0 BSP_BIT32(24) 223 #define SYSCONRCGC1_TIMER3 BSP_BIT32(19) 224 #define SYSCONRCGC1_TIMER2 BSP_BIT32(18) 225 #define SYSCONRCGC1_TIMER1 BSP_BIT32(17) 226 #define SYSCONRCGC1_TIMER0 BSP_BIT32(16) 227 #define SYSCONRCGC1_I2C1 BSP_BIT32(14) 228 #define SYSCONRCGC1_I2C0 BSP_BIT32(12) 229 #define SYSCONRCGC1_QEI0 BSP_BIT32(8) 230 #if LM3S69XX_NUM_SSI_BLOCKS > 1 231 #define SYSCONRCGC1_SSI1 BSP_BIT32(5) 232 #endif 233 #define SYSCONRCGC1_SSI0 BSP_BIT32(4) 234 #define SYSCONRCGC1_UART2 BSP_BIT32(2) 235 #define SYSCONRCGC1_UART1 BSP_BIT32(1) 236 #define SYSCONRCGC1_UART0 BSP_BIT32(0) 237 uint32_t rcgc1; 238 239 #define SYSCONRCGC2_USB0 BSP_BIT32(16) 240 #define SYSCONRCGC2_UDMA BSP_BIT32(13) 241 #if LM3S69XX_NUM_GPIO_BLOCKS > 7 242 #define SYSCONRCGC2_GPIOH BSP_BIT32(7) 243 #endif 244 #define SYSCONRCGC2_GPIOG BSP_BIT32(6) 245 #define SYSCONRCGC2_GPIOF BSP_BIT32(5) 246 #define SYSCONRCGC2_GPIOE BSP_BIT32(4) 247 #define SYSCONRCGC2_GPIOD BSP_BIT32(3) 248 #define SYSCONRCGC2_GPIOC BSP_BIT32(2) 249 #define SYSCONRCGC2_GPIOB BSP_BIT32(1) 250 #define SYSCONRCGC2_GPIOA BSP_BIT32(0) 251 uint32_t rcgc2; 252 253 uint32_t reserved_7; 254 255 uint32_t scgc0; 256 uint32_t scgc1; 257 uint32_t scgc2; 258 259 uint32_t reserved_8; 260 261 uint32_t dcgc0; 262 uint32_t dcgc1; 263 uint32_t dcgc2; 264 265 uint32_t reserved_9[6]; 266 267 #define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) 268 #define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) 269 #define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) 270 #define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) 271 uint32_t dslpclkcfg; 272 } lm3s69xx_syscon; 273 274 typedef struct { 275 #define UARTDR_OE BSP_BIT32(11) 276 #define UARTDR_BE BSP_BIT32(10) 277 #define UARTDR_PE BSP_BIT32(9) 278 #define UARTDR_FE BSP_BIT32(8) 279 #define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) 280 uint32_t dr; 281 282 uint32_t rsr_ecr; 283 uint32_t reserved_0[4]; 284 285 #define UARTFR_TXFE BSP_BIT32(7) 286 #define UARTFR_RXFF BSP_BIT32(6) 287 #define UARTFR_TXFF BSP_BIT32(5) 288 #define UARTFR_RXFE BSP_BIT32(4) 289 #define UARTFR_BUSY BSP_BIT32(3) 290 uint32_t fr; 291 292 uint32_t reserved_1; 293 294 uint32_t ilpr; 295 uint32_t ibrd; 296 uint32_t fbrd; 297 298 #define UARTLCRH_SPS BSP_BIT32(7) 299 #define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) 300 #define UARTLCRH_FEN BSP_BIT32(4) 301 #define UARTLCRH_STP2 BSP_BIT32(3) 302 #define UARTLCRH_EPS BSP_BIT32(2) 303 #define UARTLCRH_PEN BSP_BIT32(1) 304 #define UARTLCRH_BRK BSP_BIT32(0) 305 uint32_t lcrh; 306 307 #define UARTCTL_RXE BSP_BIT32(9) 308 #define UARTCTL_TXE BSP_BIT32(8) 309 #define UARTCTL_LBE BSP_BIT32(7) 310 #define UARTCTL_SIRLP BSP_BIT32(2) 311 #define UARTCTL_SIREN BSP_BIT32(1) 312 #define UARTCTL_UARTEN BSP_BIT32(0) 313 uint32_t ctl; 314 315 #define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) 316 #define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) 317 uint32_t ifls; 318 319 #define UARTI_OE BSP_BIT32(10) 320 #define UARTI_BE BSP_BIT32(9) 321 #define UARTI_PE BSP_BIT32(8) 322 #define UARTI_FE BSP_BIT32(7) 323 #define UARTI_RT BSP_BIT32(6) 324 #define UARTI_TX BSP_BIT32(5) 325 #define UARTI_RX BSP_BIT32(4) 326 uint32_t im; 327 uint32_t ris; 328 uint32_t mis; 329 uint32_t icr; 330 #if LM3S69XX_HAS_UDMA 331 uint32_t dmactl; 332 #endif 333 } lm3s69xx_uart; 334 335 typedef struct { 336 #define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) 337 #define SSICR0_SPH BSP_BIT32(7) 338 #define SSICR0_SPO BSP_BIT32(6) 339 #define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) 340 #define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) 341 uint32_t cr0; 342 343 #define SSICR1_SOD BSP_BIT32(3) 344 #define SSICR1_MS BSP_BIT32(2) 345 #define SSICR1_SSE BSP_BIT32(1) 346 #define SSICR1_LBM BSP_BIT32(0) 347 uint32_t cr1; 348 uint32_t dr; 349 350 #define SSISR_BSY BSP_BIT32(4) 351 #define SSISR_RFF BSP_BIT32(3) 352 #define SSISR_RNE BSP_BIT32(2) 353 #define SSISR_TNF BSP_BIT32(1) 354 #define SSISR_TFE BSP_BIT32(0) 355 uint32_t sr; 356 357 #define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) 358 uint32_t cpsr; 359 360 #define SSII_TX BSP_BIT32(3) 361 #define SSII_RX BSP_BIT32(2) 362 #define SSII_RT BSP_BIT32(1) 363 #define SSII_ROR BSP_BIT32(0) 364 uint32_t im; 365 uint32_t ris; 366 uint32_t mis; 367 uint32_t icr; 368 369 #if LM3S69XX_HAS_UDMA 370 #define SSIDMACTL_TXDMAE BSP_BIT32(1) 371 #define SSIDMACTL_RXDMAE BSP_BIT32(0) 372 uint32_t dmactl; 373 #endif /* LM3S69XX_HAS_UDMA */ 374 } lm3s69xx_ssi; 29 375 30 376 #endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ -
c/src/lib/libbsp/arm/lm3s69xx/include/uart.h
rb7cf1ff7 rf22bba3 17 17 18 18 #include <libchip/serial.h> 19 #include <bsp/utility.h>20 19 21 20 #ifdef __cplusplus 22 21 extern "C" { 23 22 #endif /* __cplusplus */ 24 25 typedef struct {26 #define UARTDR_OE BSP_BIT32(11)27 #define UARTDR_BE BSP_BIT32(10)28 #define UARTDR_PE BSP_BIT32(9)29 #define UARTDR_FE BSP_BIT32(8)30 #define UARTDR_DATA(val) BSP_FLD32(val, 0, 7)31 uint32_t dr;32 33 uint32_t rsr_ecr;34 uint32_t reserved [4];35 36 #define UARTFR_TXFE BSP_BIT32(7)37 #define UARTFR_RXFF BSP_BIT32(6)38 #define UARTFR_TXFF BSP_BIT32(5)39 #define UARTFR_RXFE BSP_BIT32(4)40 #define UARTFR_BUSY BSP_BIT32(3)41 uint32_t fr;42 uint32_t ilpr;43 uint32_t ibrd;44 uint32_t fbrd;45 46 #define UARTLCRH_SPS BSP_BIT32(7)47 #define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6)48 #define UARTLCRH_FEN BSP_BIT32(4)49 #define UARTLCRH_STP2 BSP_BIT32(3)50 #define UARTLCRH_EPS BSP_BIT32(2)51 #define UARTLCRH_PEN BSP_BIT32(1)52 #define UARTLCRH_BRK BSP_BIT32(0)53 uint32_t lcrh;54 55 #define UARTCTL_RXE BSP_BIT32(9)56 #define UARTCTL_TXE BSP_BIT32(8)57 #define UARTCTL_LBE BSP_BIT32(7)58 #define UARTCTL_SIRLP BSP_BIT32(2)59 #define UARTCTL_SIREN BSP_BIT32(1)60 #define UARTCTL_UARTEN BSP_BIT32(0)61 uint32_t ctl;62 63 #define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)64 #define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)65 uint32_t ifls;66 67 #define UARTI_OE BSP_BIT32(10)68 #define UARTI_BE BSP_BIT32(9)69 #define UARTI_PE BSP_BIT32(8)70 #define UARTI_FE BSP_BIT32(7)71 #define UARTI_RT BSP_BIT32(6)72 #define UARTI_TX BSP_BIT32(5)73 #define UARTI_RX BSP_BIT32(4)74 uint32_t im;75 uint32_t ris;76 uint32_t mis;77 uint32_t icr;78 } lm3s69xx_uart;79 23 80 24 extern const console_fns lm3s69xx_uart_fns; -
c/src/lib/libbsp/arm/lm3s69xx/preinstall.am
rb7cf1ff7 rf22bba3 102 102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h 103 103 104 $(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) 105 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h 106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h 107 108 $(PROJECT_INCLUDE)/bsp/syscon.h: include/syscon.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) 109 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/syscon.h 110 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/syscon.h 111 112 $(PROJECT_INCLUDE)/bsp/ssi.h: include/ssi.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) 113 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssi.h 114 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssi.h 115 104 116 $(PROJECT_INCLUDE)/bsp/lm3s69xx.h: include/lm3s69xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) 105 117 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lm3s69xx.h -
c/src/lib/libbsp/arm/lm3s69xx/startup/bspreset.c
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 3 * 2 4 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 5 * … … 25 27 rtems_interrupt_disable(level); 26 28 27 _ARMV7M_NVIC->reserved_5 [0] = 0; 29 _ARMV7M_SCB->aircr = ARMV7M_SCB_AIRCR_VECTKEY 30 | ARMV7M_SCB_AIRCR_SYSRESETREQ; 31 32 while (true) 33 /* Do nothing */; 28 34 } -
c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c
rb7cf1ff7 rf22bba3 1 1 /* 2 * Copyright (c) 2011 Sebastian Huber. All rights reserved. 3 * 4 * embedded brains GmbH 5 * Obere Lagerstr. 30 6 * 82178 Puchheim 7 * Germany 8 * <rtems@embedded-brains.de> 2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> 9 3 * 10 4 * The license and distribution terms for this file may be … … 14 8 15 9 #include <bsp.h> 16 #include <bsp /bootcard.h>10 #include <bspopts.h> 17 11 #include <bsp/irq-generic.h> 18 #include <bsp/irq.h> 19 #include <bsp/linker-symbols.h> 12 #include <bsp/lm3s69xx.h> 13 #include <bsp/io.h> 14 #include <bsp/syscon.h> 15 #include <assert.h> 16 17 static void init_main_osc(void) 18 { 19 volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; 20 21 uint32_t sysdiv_val = LM3S69XX_PLL_FREQUENCY / LM3S69XX_SYSTEM_CLOCK; 22 assert(sysdiv_val * LM3S69XX_SYSTEM_CLOCK == LM3S69XX_PLL_FREQUENCY); 23 assert((sysdiv_val >= 4) && (sysdiv_val <= 16)); 24 25 uint32_t rcc = syscon->rcc; 26 27 rcc = (rcc & ~SYSCONRCC_USESYSDIV) | SYSCONRCC_BYPASS; 28 syscon->rcc = rcc; 29 30 rcc = (rcc & ~(SYSCONRCC_PWRDN | SYSCONRCC_XTAL_MSK | SYSCONRCC_OSCSRC_MSK)) 31 | SYSCONRCC_XTAL(LM3S69XX_XTAL_CONFIG) | SYSCONRCC_OSCSRC_MOSC; 32 syscon->rcc = rcc; 33 34 rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_SYSDIV(sysdiv_val / 2 - 1) 35 | SYSCONRCC_USESYSDIV; 36 syscon->rcc = rcc; 37 38 while ((syscon->ris & SYSCONRIS_PLLLRIS) == 0) 39 /* Wait for PLL lock */; 40 41 rcc &= ~SYSCONRCC_BYPASS; 42 syscon->rcc = rcc; 43 } 44 45 static const lm3s69xx_gpio_config start_config_gpio[] = { 46 #ifdef LM3S69XX_ENABLE_UART_0 47 #if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) 48 LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_A, 0), 49 LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_A, 1), 50 #else 51 #error No GPIO pin configuration for UART 0 52 #endif 53 #endif /* LM3S69XX_ENABLE_UART_0 */ 54 55 #ifdef LM3S69XX_ENABLE_UART_1 56 #if defined(LM3S69XX_MCU_LM3S3749) 57 LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_B, 0), 58 LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_B, 1), 59 #elif defined(LM3S69XX_MCU_LM3S6965) 60 LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_D, 2); 61 LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_D, 3); 62 #else 63 #error No GPIO pin configuration for UART 1 64 #endif 65 #endif /* LM3S69XX_ENABLE_UART_1 */ 66 67 #ifdef LM3S69XX_ENABLE_UART_2 68 #if defined(LM3S69XX_MCU_LM3S3749) 69 LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_D, 0), 70 LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_D, 1), 71 #elif defined(LM3S69XX_MCU_LM3S6965) 72 LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_G, 0), 73 LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_G, 1), 74 #else 75 #error No GPIO pin configuration for UART 2 76 #endif 77 #endif /* LM3S69XX_ENABLE_UART_2 */ 78 }; 79 80 static void init_gpio(void) 81 { 82 #if LM3S69XX_USE_AHB_FOR_GPIO 83 volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; 84 85 syscon->gpiohbctl |= SYSCONGPIOHBCTL_PORTA | SYSCONGPIOHBCTL_PORTB 86 | SYSCONGPIOHBCTL_PORTC | SYSCONGPIOHBCTL_PORTD 87 | SYSCONGPIOHBCTL_PORTE | SYSCONGPIOHBCTL_PORTF 88 | SYSCONGPIOHBCTL_PORTG 89 #if LM3S69XX_NUM_GPIO_BLOCKS > 7 90 | SYSCONGPIOHBCTL_PORTH 91 #endif 92 ; 93 94 #endif /* LM3S69XX_USE_AHB_FOR_GPIO */ 95 96 lm3s69xx_gpio_set_config_array(start_config_gpio, 97 sizeof(start_config_gpio) / sizeof(start_config_gpio[0])); 98 } 20 99 21 100 void bsp_start(void) 22 101 { 102 init_main_osc(); 103 init_gpio(); 23 104 bsp_interrupt_initialize(); 24 105 } -
c/src/lib/libbsp/arm/lm3s69xx/startup/linkcmds.lm3s6965
rb7cf1ff7 rf22bba3 6 6 7 7 MEMORY { 8 RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 16M9 ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 64M8 RAM_INT (AIW) : ORIGIN = 0x20000000, LENGTH = 64K 9 ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 256K 10 10 } 11 11
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