Changeset f1f42b4 in rtems for c/src

Modifications from Jiri Gaisler <jgais@…> to
fix some problems encountered when reusing this driver on
a SPARC ERC32 based Tharsys board. He eliminted the need
for TX interrupts and added code that can optionally ensure that
the IP address is 32-bit aligned. He also fixed a handful of
problems that only occured because the 8 Mhz ERC32 was
enough slower than the 100 Mhz PPC603e that timing
issues in this driver were magnified.