Changeset f0ad529 in rtems
- Timestamp:
- 03/07/06 20:47:53 (18 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d3490f27
- Parents:
- a03debd5
- Location:
- cpukit
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/ChangeLog
ra03debd5 rf0ad529 1 2006-03-07 Joel Sherrill <joel@OARcorp.com> 2 3 PR 866/rtems 4 * score/include/rtems/system.h, score/include/rtems/score/isr.h, 5 score/inline/rtems/score/thread.inl, 6 score/macros/rtems/score/thread.inl: Added memory barriers to enter 7 and exit of dispatching and interrupt critical sections so GCC will 8 not optimize and reorder code out of a critical section. 9 1 10 2006-02-08 Thomas Rauscher <trauscher@loytec.com> 2 11 -
cpukit/score/include/rtems/score/isr.h
ra03debd5 rf0ad529 105 105 */ 106 106 #define _ISR_Disable( _level ) \ 107 _CPU_ISR_Disable( _level ) 107 do { \ 108 _CPU_ISR_Disable( _level ); \ 109 RTEMS_COMPILER_MEMORY_BARRIER(); \ 110 } while (0) 108 111 109 112 /** … … 113 116 */ 114 117 #define _ISR_Enable( _level ) \ 115 _CPU_ISR_Enable( _level ) 118 do { \ 119 RTEMS_COMPILER_MEMORY_BARRIER(); \ 120 _CPU_ISR_Enable( _level ); \ 121 } while (0) 116 122 117 123 /** … … 128 134 */ 129 135 #define _ISR_Flash( _level ) \ 130 _CPU_ISR_Flash( _level ) 136 do { \ 137 RTEMS_COMPILER_MEMORY_BARRIER(); \ 138 _CPU_ISR_Flash( _level ); \ 139 RTEMS_COMPILER_MEMORY_BARRIER(); \ 140 } while (0) 131 141 132 142 /** -
cpukit/score/include/rtems/system.h
ra03debd5 rf0ad529 136 136 #endif 137 137 138 /** 139 * The following macro is a compiler specific way to ensure that memory 140 * writes are not reordered around certian points. This specifically can 141 * impact interrupt disable and thread dispatching critical sections. 142 */ 143 #ifdef __GNUC__ 144 #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory") 145 #else 146 #define RTEMS_COMPILER_MEMORY_BARRIER() 147 #endif 148 138 149 #ifdef RTEMS_POSIX_API 139 150 /** The following is used by the POSIX implementation to catch bad paths. */ -
cpukit/score/inline/rtems/score/thread.inl
ra03debd5 rf0ad529 143 143 { 144 144 _Thread_Dispatch_disable_level += 1; 145 RTEMS_COMPILER_MEMORY_BARRIER(); 145 146 } 146 147 … … 155 156 RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch() 156 157 { 158 RTEMS_COMPILER_MEMORY_BARRIER(); 157 159 if ( (--_Thread_Dispatch_disable_level) == 0 ) 158 160 _Thread_Dispatch(); … … 172 174 RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch( void ) 173 175 { 176 RTEMS_COMPILER_MEMORY_BARRIER(); 174 177 _Thread_Dispatch_disable_level -= 1; 175 178 } -
cpukit/score/macros/rtems/score/thread.inl
ra03debd5 rf0ad529 127 127 128 128 #define _Thread_Disable_dispatch() \ 129 _Thread_Dispatch_disable_level += 1 129 do { \ 130 _Thread_Dispatch_disable_level += 1; \ 131 RTEMS_COMPILER_MEMORY_BARRIER(); \ 132 } while (0) 130 133 131 134 /*PAGE … … 137 140 #if ( CPU_INLINE_ENABLE_DISPATCH == TRUE ) 138 141 #define _Thread_Enable_dispatch() \ 139 { if ( (--_Thread_Dispatch_disable_level) == 0 ) \ 140 _Thread_Dispatch(); \ 141 } 142 do { \ 143 RTEMS_COMPILER_MEMORY_BARRIER(); \ 144 if ( (--_Thread_Dispatch_disable_level) == 0 ) \ 145 _Thread_Dispatch(); \ 146 } while (0) 142 147 #endif 143 148 … … 153 158 154 159 #define _Thread_Unnest_dispatch() \ 155 _Thread_Dispatch_disable_level -= 1 160 do { \ 161 RTEMS_COMPILER_MEMORY_BARRIER(); \ 162 _Thread_Dispatch_disable_level -= 1; \ 163 } while (0) 156 164 157 165 /*PAGE
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