Changeset f0ad529 in rtems


Ignore:
Timestamp:
03/07/06 20:47:53 (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
d3490f27
Parents:
a03debd5
Message:

2006-03-07 Joel Sherrill <joel@…>

PR 866/rtems

  • score/include/rtems/system.h, score/include/rtems/score/isr.h, score/inline/rtems/score/thread.inl, score/macros/rtems/score/thread.inl: Added memory barriers to enter and exit of dispatching and interrupt critical sections so GCC will not optimize and reorder code out of a critical section.
Location:
cpukit
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/ChangeLog

    ra03debd5 rf0ad529  
     12006-03-07      Joel Sherrill <joel@OARcorp.com>
     2
     3        PR 866/rtems
     4        * score/include/rtems/system.h, score/include/rtems/score/isr.h,
     5        score/inline/rtems/score/thread.inl,
     6        score/macros/rtems/score/thread.inl: Added memory barriers to enter
     7        and exit of dispatching and interrupt critical sections so GCC will
     8        not optimize and reorder code out of a critical section.
     9
    1102006-02-08      Thomas Rauscher  <trauscher@loytec.com>
    211
  • cpukit/score/include/rtems/score/isr.h

    ra03debd5 rf0ad529  
    105105 */
    106106#define _ISR_Disable( _level ) \
    107         _CPU_ISR_Disable( _level )
     107  do { \
     108    _CPU_ISR_Disable( _level ); \
     109    RTEMS_COMPILER_MEMORY_BARRIER(); \
     110  } while (0)
    108111
    109112/**
     
    113116 */
    114117#define _ISR_Enable( _level ) \
    115         _CPU_ISR_Enable( _level )
     118  do { \
     119    RTEMS_COMPILER_MEMORY_BARRIER(); \
     120    _CPU_ISR_Enable( _level ); \
     121  } while (0)
    116122
    117123/**
     
    128134 */
    129135#define _ISR_Flash( _level ) \
    130         _CPU_ISR_Flash( _level )
     136  do { \
     137    RTEMS_COMPILER_MEMORY_BARRIER(); \
     138    _CPU_ISR_Flash( _level ); \
     139    RTEMS_COMPILER_MEMORY_BARRIER(); \
     140  } while (0)
    131141
    132142/**
  • cpukit/score/include/rtems/system.h

    ra03debd5 rf0ad529  
    136136#endif
    137137
     138/**
     139 *  The following macro is a compiler specific way to ensure that memory
     140 *  writes are not reordered around certian points.  This specifically can
     141 *  impact interrupt disable and thread dispatching critical sections.
     142 */
     143#ifdef __GNUC__
     144  #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory")
     145#else
     146  #define RTEMS_COMPILER_MEMORY_BARRIER()
     147#endif
     148
    138149#ifdef RTEMS_POSIX_API
    139150/** The following is used by the POSIX implementation to catch bad paths.  */
  • cpukit/score/inline/rtems/score/thread.inl

    ra03debd5 rf0ad529  
    143143{
    144144  _Thread_Dispatch_disable_level += 1;
     145  RTEMS_COMPILER_MEMORY_BARRIER();
    145146}
    146147
     
    155156RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch()
    156157{
     158  RTEMS_COMPILER_MEMORY_BARRIER();
    157159  if ( (--_Thread_Dispatch_disable_level) == 0 )
    158160    _Thread_Dispatch();
     
    172174RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch( void )
    173175{
     176  RTEMS_COMPILER_MEMORY_BARRIER();
    174177  _Thread_Dispatch_disable_level -= 1;
    175178}
  • cpukit/score/macros/rtems/score/thread.inl

    ra03debd5 rf0ad529  
    127127
    128128#define _Thread_Disable_dispatch() \
    129   _Thread_Dispatch_disable_level += 1
     129  do { \
     130    _Thread_Dispatch_disable_level += 1; \
     131    RTEMS_COMPILER_MEMORY_BARRIER(); \
     132  } while (0)
    130133
    131134/*PAGE
     
    137140#if ( CPU_INLINE_ENABLE_DISPATCH == TRUE )
    138141#define _Thread_Enable_dispatch()  \
    139       { if ( (--_Thread_Dispatch_disable_level) == 0 ) \
    140              _Thread_Dispatch();  \
    141       }
     142  do { \
     143    RTEMS_COMPILER_MEMORY_BARRIER(); \
     144    if ( (--_Thread_Dispatch_disable_level) == 0 ) \
     145       _Thread_Dispatch(); \
     146  } while (0)
    142147#endif
    143148
     
    153158
    154159#define _Thread_Unnest_dispatch()  \
    155   _Thread_Dispatch_disable_level -= 1
     160  do { \
     161    RTEMS_COMPILER_MEMORY_BARRIER(); \
     162    _Thread_Dispatch_disable_level -= 1; \
     163  } while (0)
    156164
    157165/*PAGE
Note: See TracChangeset for help on using the changeset viewer.