Changeset f098bf1 in rtems


Ignore:
Timestamp:
Nov 26, 2007, 7:56:21 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
a3ff693
Parents:
a4ebf1f4
Message:

2007-11-26 Ray Xu <rayx.cn@…>

  • thumb_isr.c: Remove extra debug information, Change function definition.
Location:
cpukit/score/cpu/arm/thumb
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/thumb/ChangeLog

    ra4ebf1f4 rf098bf1  
     12007-11-26      Ray Xu <rayx.cn@gmail.com>
     2
     3        * thumb_isr.c: Remove extra debug information, Change function
     4        definition.
     5
    162007-11-06      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
  • cpukit/score/cpu/arm/thumb/thumb_isr.c

    ra4ebf1f4 rf098bf1  
    1818 */
    1919uint32_t        _CPU_ISR_Get_level_Thumb(void)       __attribute__ ((naked));
    20 unsigned int    _CPU_ISR_Disable_Thumb(void )        __attribute__ ((naked));
    21 void __inline__ _CPU_ISR_Enable_Thumb(int  _level )  __attribute__ ((naked));
    22 void __inline__ _CPU_ISR_Flash_Thumb(int _level )    __attribute__ ((naked));
    23 void __inline__ _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
     20uint32_t    _CPU_ISR_Disable_Thumb(void )        __attribute__ ((naked));
     21void   _CPU_ISR_Enable_Thumb(int  _level )  __attribute__ ((naked));
     22void   _CPU_ISR_Flash_Thumb(int _level )    __attribute__ ((naked));
     23void   _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
    2424
    2525/*
     
    3434
    3535
    36 
    37 /*
    38  *  Fix me: use mutex to visit isr_flag
    39  */
    40 
    4136#define str(x) #x
    4237#define xstr(x) str(x)
    4338#define L(x) #x "_" xstr(__LINE__)
    44 
    45 #define U0THR           (*((volatile unsigned char *) 0xE000C000))
    46 #define U0LSR           (*((volatile unsigned char *) 0xE000C014))
    47 
    48 void __inline__  UART0_Send_Byte(char data)
    49 {
    50     U0THR = data;
    51 
    52     while( (U0LSR&0x40)==0 );
    53 }
    5439
    5540/*
     
    7964 */
    8065
    81 unsigned int __inline__ _CPU_ISR_Disable_Thumb(void )
     66uint32_t _CPU_ISR_Disable_Thumb(void )
    8267  {
    8368    int reg=0;
     
    10186 */
    10287
    103 void __inline__ _CPU_ISR_Enable_Thumb(int  _level )
     88void _CPU_ISR_Enable_Thumb(int  _level )
    10489  {
    10590        int reg=0;
     
    121106 * modified.
    122107 */
    123 void __inline__ _CPU_ISR_Flash_Thumb(int _level )
     108void _CPU_ISR_Flash_Thumb(int _level )
    124109  {
    125110    int reg=0;
    126     UART0_Send_Byte(70);
    127     //asm volatile("NOP");
    128     //(*((volatile unsigned char *) 0xE000C000))='\r';
    129111    TO_ARM_MODE(flash);
    130112    asm volatile ( \
     
    156138 */
    157139
    158 void __inline__ _CPU_ISR_Set_level_Thumb(int  new_level )
     140void _CPU_ISR_Set_level_Thumb(int  new_level )
    159141  {
    160142   int reg = 0; /* to avoid warning */          \
     
    172154 }
    173155
    174 uint32_t __inline__ _CPU_ISR_Get_level_Thumb( void )
     156uint32_t _CPU_ISR_Get_level_Thumb( void )
    175157{
    176158    uint32_t   reg = 0; /* to avoid warning */
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