Changeset f018b1a in rtems


Ignore:
Timestamp:
Aug 25, 2000, 5:25:27 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
8e57762
Parents:
00ff4cd
Message:

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

  • mpc8xx/console-generic/console-generic.c: Add support for configuration parameters in NVRAM
Location:
c/src/lib/libcpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r00ff4cd rf018b1a  
     12000-08-11  Charles-Antoine Gauthier  <charles.gauthier@nrc.ca>
     2
     3        * mpc8xx/console-generic/console-generic.c:
     4        Add support for configuration parameters in NVRAM
     5
    162000-08-25      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
  • c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c

    r00ff4cd rf018b1a  
    5555#include <unistd.h>
    5656#include <termios.h>
     57#include <bsp.h>
    5758
    5859extern rtems_cpu_table Cpu_table;
     
    704705  sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
    705706  sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
     707#if NVRAM_CONFIGURE == 1
     708  if ( (nvram->console_mode & 0x06) == 0x02 )
     709    sccparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
     710  else
     711    sccparms->mrblr = 1;            /* Maximum Rx buffer size */
     712#else
    706713#if UARTS_IO_MODE == 1
    707714  sccparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
     
    709716  sccparms->mrblr = 1;              /* Maximum Rx buffer size */
    710717#endif
    711 
     718#endif
    712719  sccparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
    713720  sccparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
     
    775782#endif
    776783  }
     784#if NVRAM_CONFIGURE == 1
     785  if ( (nvram->console_mode & 0x06) == 0x02 ) {
     786    switch (minor) {
     787      case SCC2_MINOR:
     788        rtems_interrupt_catch (m8xx_scc2_interrupt_handler,
     789                               PPC_IRQ_CPM_SCC2,
     790                               &old_handler[minor]);
     791
     792        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
     793        m8xx.cimr |= 1UL <<  29;      /* Enable SCC2 interrupts */
     794        break;
     795
     796#ifdef mpc860
     797      case SCC3_MINOR:
     798        rtems_interrupt_catch (m8xx_scc3_interrupt_handler,
     799                               PPC_IRQ_CPM_SCC3,
     800                               &old_handler[minor]);
     801
     802        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
     803        m8xx.cimr |= 1UL <<  28;      /* Enable SCC2 interrupts */
     804        break;
     805     
     806      case SCC4_MINOR:
     807        rtems_interrupt_catch (m8xx_scc4_interrupt_handler,
     808                               PPC_IRQ_CPM_SCC4,
     809                               &old_handler[minor]);
     810
     811        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
     812        m8xx.cimr |= 1UL <<  27;      /* Enable SCC2 interrupts */
     813        break;
     814#endif /* mpc860 */
     815    }
     816  }
     817 
     818#else /* NVRAM_CONFIGURE != 1 */
     819
    777820#if UARTS_IO_MODE == 1
    778821  switch (minor) {
     
    807850  }
    808851#endif /* UARTS_IO_MODE */
     852
     853#endif /* NVRAM_CONFIGURE */
    809854}
    810855
     
    875920  smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
    876921  smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
     922#if NVRAM_CONFIGURE == 1
     923  if ( (nvram->console_mode & 0x06) == 0x02 )
     924    smcparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
     925  else
     926    smcparms->mrblr = 1;            /* Maximum Rx buffer size */
     927#else
    877928#if UARTS_IO_MODE == 1
    878929  smcparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
     
    880931  smcparms->mrblr = 1;              /* Maximum Rx buffer size */
    881932#endif
     933#endif
    882934
    883935  /*
     
    924976   */
    925977  smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
     978#if NVRAM_CONFIGURE == 1
     979  if ( (nvram->console_mode & 0x06) == 0x02 ) {
     980    switch (minor) {
     981      case SMC1_MINOR:
     982        rtems_interrupt_catch (m8xx_smc1_interrupt_handler,
     983                                    PPC_IRQ_CPM_SMC1,
     984                                    &old_handler[minor]);
     985
     986        smcregs->smcm = 3;            /* Enable SMC1 Rx & Tx interrupts */
     987        m8xx.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
     988        break;
     989     
     990      case SMC2_MINOR:
     991        rtems_interrupt_catch (m8xx_smc2_interrupt_handler,
     992                                    PPC_IRQ_CPM_SMC2,
     993                                    &old_handler[minor]);
     994
     995        smcregs->smcm = 3;            /* Enable SMC2 Rx & Tx interrupts */
     996        m8xx.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
     997        break;
     998    }
     999  }
     1000#else
    9261001#if UARTS_IO_MODE == 1
    9271002  switch (minor) {
     
    9441019      break;
    9451020  }
     1021#endif
     1022
    9461023#endif
    9471024}
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