Changeset f018b1a in rtems

Timestamp:

08/25/00 17:25:27 (23 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

8e57762

Parents:

00ff4cd

Message:

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

• mpc8xx/console-generic/console-generic.c: Add support for configuration parameters in NVRAM

Location:

c/src/lib/libcpu/powerpc

Files:

• ChangeLog (modified) (1 diff)
• mpc8xx/console-generic/console-generic.c (modified) (9 diffs)

c/src/lib/libcpu/powerpc/ChangeLog

@@ +1 @@
+2000-08-11  Charles-Antoine Gauthier  <charles.gauthier@nrc.ca>
+
+        * mpc8xx/console-generic/console-generic.c:
+        Add support for configuration parameters in NVRAM
+
 2000-08-25      Joel Sherrill <joel.sherrill@OARcorp.com>
 

c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c

@@ -55 +55 @@
 #include <unistd.h>
 #include <termios.h>
+#include <bsp.h>
 
 extern rtems_cpu_table Cpu_table;
@@ -704 +705 @@
   sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
   sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
+#if NVRAM_CONFIGURE == 1
+  if ( (nvram->console_mode & 0x06) == 0x02 )
+    sccparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
+  else
+    sccparms->mrblr = 1;            /* Maximum Rx buffer size */
+#else
 #if UARTS_IO_MODE == 1
   sccparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
@@ -709 +716 @@
   sccparms->mrblr = 1;              /* Maximum Rx buffer size */
 #endif
-
+#endif
   sccparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
   sccparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
@@ -775 +782 @@
 #endif
   }
+#if NVRAM_CONFIGURE == 1
+  if ( (nvram->console_mode & 0x06) == 0x02 ) {
+    switch (minor) {
+      case SCC2_MINOR:
+        rtems_interrupt_catch (m8xx_scc2_interrupt_handler,
+                               PPC_IRQ_CPM_SCC2,
+                               &old_handler[minor]);
+
+        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+        m8xx.cimr |= 1UL <<  29;      /* Enable SCC2 interrupts */
+        break;
+
+#ifdef mpc860
+      case SCC3_MINOR:
+        rtems_interrupt_catch (m8xx_scc3_interrupt_handler,
+                               PPC_IRQ_CPM_SCC3,
+                               &old_handler[minor]);
+
+        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+        m8xx.cimr |= 1UL <<  28;      /* Enable SCC2 interrupts */
+        break;
+      
+      case SCC4_MINOR:
+        rtems_interrupt_catch (m8xx_scc4_interrupt_handler,
+                               PPC_IRQ_CPM_SCC4,
+                               &old_handler[minor]);
+
+        sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+        m8xx.cimr |= 1UL <<  27;      /* Enable SCC2 interrupts */
+        break;
+#endif /* mpc860 */
+    }
+  }
+  
+#else /* NVRAM_CONFIGURE != 1 */
+
 #if UARTS_IO_MODE == 1
   switch (minor) {
@@ -807 +850 @@
   }
 #endif /* UARTS_IO_MODE */
+
+#endif /* NVRAM_CONFIGURE */
 }
 
@@ -875 +920 @@
   smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
   smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
+#if NVRAM_CONFIGURE == 1
+  if ( (nvram->console_mode & 0x06) == 0x02 )
+    smcparms->mrblr = RXBUFSIZE;    /* Maximum Rx buffer size */
+  else
+    smcparms->mrblr = 1;            /* Maximum Rx buffer size */
+#else
 #if UARTS_IO_MODE == 1
   smcparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
@@ -880 +931 @@
   smcparms->mrblr = 1;              /* Maximum Rx buffer size */
 #endif
+#endif
 
   /*
@@ -924 +976 @@
    */
   smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
+#if NVRAM_CONFIGURE == 1
+  if ( (nvram->console_mode & 0x06) == 0x02 ) {
+    switch (minor) {
+      case SMC1_MINOR:
+        rtems_interrupt_catch (m8xx_smc1_interrupt_handler,
+                                    PPC_IRQ_CPM_SMC1,
+                                    &old_handler[minor]);
+
+        smcregs->smcm = 3;            /* Enable SMC1 Rx & Tx interrupts */
+        m8xx.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
+        break;
+      
+      case SMC2_MINOR:
+        rtems_interrupt_catch (m8xx_smc2_interrupt_handler,
+                                    PPC_IRQ_CPM_SMC2,
+                                    &old_handler[minor]);
+
+        smcregs->smcm = 3;            /* Enable SMC2 Rx & Tx interrupts */
+        m8xx.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
+        break;
+    }
+  }
+#else
 #if UARTS_IO_MODE == 1
   switch (minor) {
@@ -944 +1019 @@
       break;
   }
+#endif
+
 #endif
 }