Changeset efdfd48 in rtems


Ignore:
Timestamp:
Nov 29, 2009, 3:27:07 PM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
44b06ca
Parents:
d4b4664b
Message:

Whitespace removal.

Location:
c/src/lib/libbsp
Files:
57 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/csb350/clock/clockdrv.c

    rd4b4664b refdfd48  
    66 *  Copyright (c) 2005 by Cogent Computer Systems
    77 *  Written by Jay Monkman <jtm@lopingdog.com>
    8  *     
     8 *
    99 *  The license and distribution terms for this file may be
    1010 *  found in found in the file LICENSE in this distribution or at
     
    4747{
    4848    uint32_t wakemask;
    49     /* Clear the trim register */ 
    50     AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0; 
    51    
    52     /* Clear the TOY counter */ 
    53     while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); 
    54     AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0; 
    55     while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); 
    56    
    57     wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR); 
     49    /* Clear the trim register */
     50    AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
     51
     52    /* Clear the TOY counter */
     53    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
     54    AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0;
     55    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
     56
     57    wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR);
    5858    wakemask |= AU1X00_SYS_WAKEMSK_M20;
    59     AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask; 
     59    AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask;
    6060    AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
    61    
    62     tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick(); 
    63     tick_interval = tick_interval / 1000000; 
    64     printk("tick_interval = %d\n", tick_interval); 
    65    
    66     last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); 
    67     AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval); 
     61
     62    tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick();
     63    tick_interval = tick_interval / 1000000;
     64    printk("tick_interval = %d\n", tick_interval);
     65
     66    last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR);
     67    AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval);
    6868    AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
    69     while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); 
     69    while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0);
    7070}
    7171
     
    7575  } while(0)
    7676
    77                  
     77
    7878
    7979#define Clock_driver_support_shutdown_hardware()
  • c/src/lib/libbsp/mips/csb350/console/console-io.c

    rd4b4664b refdfd48  
    4848        continue;
    4949    }
    50    
     50
    5151    uart0->txdata = ch;
    5252    au_sync();
     
    5454
    5555/*
    56  *  console_inbyte_nonblocking 
     56 *  console_inbyte_nonblocking
    5757 *
    5858 *  This routine polls for a character.
     
    7575#include <rtems/bspIo.h>
    7676
    77 void csb250_output_char(char c) 
    78 { 
    79     console_outbyte_polled( 0, c ); 
     77void csb250_output_char(char c)
     78{
     79    console_outbyte_polled( 0, c );
    8080    if (c == '\n') {
    81         console_outbyte_polled( 0, '\r' ); 
     81        console_outbyte_polled( 0, '\r' );
    8282    }
    8383}
  • c/src/lib/libbsp/mips/csb350/include/bsp.h

    rd4b4664b refdfd48  
    3535extern struct rtems_bsdnet_ifconfig *config;
    3636
    37 int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config, 
     37int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config,
    3838                             int attaching);
    3939#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
  • c/src/lib/libbsp/mips/csb350/network/network.c

    rd4b4664b refdfd48  
    44 *  Copyright (c) 2005 by Cogent Computer Systems
    55 *  Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in found in the file LICENSE in this distribution or at
     
    6262     */
    6363    struct arpcom                    arpcom;
    64    
     64
    6565    /*
    6666     * Interrupt vector
    6767     */
    6868    rtems_vector_number             vector;
    69    
     69
    7070    /*
    7171     *  Indicates configuration
    7272     */
    7373    int                             acceptBroadcast;
    74    
     74
    7575    /*
    7676     * Tasks waiting for interrupts
     
    7878    rtems_id                        rx_daemon_tid;
    7979    rtems_id                        tx_daemon_tid;
    80    
     80
    8181    /*
    8282     * Buffers
     
    126126    unsigned long                   rx_pkts;
    127127    unsigned long                   rx_dropped;
    128    
     128
    129129    unsigned long                   tx_deferred;
    130130    unsigned long                   tx_underrun;
     
    137137
    138138/* function prototypes */
    139 int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config, 
     139int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config,
    140140                              int attaching);
    141141void au1x00_emac_init(void *arg);
     
    161161    /* write to address 0 - we only support address 0 */
    162162    AU1X00_MAC_MIIDATA(sc->ctrl_regs) = val;
    163     AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) | 
     163    AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) |
    164164                                         AU1X00_MAC_MIICTRL_MW);
    165165    au_sync();
    166    
     166
    167167    /* wait for it to complete */
    168168    while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
     
    181181    AU1X00_MAC_MIICTRL(sc->ctrl_regs) = ((reg & 0x1f) << 6);
    182182    au_sync();
    183    
     183
    184184    /* wait for it to complete */
    185185    while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
     
    215215    char *unitname;
    216216    static au1x00_emac_softc_t *sc;
    217    
     217
    218218    /*
    219219     * Parse driver name
     
    221221    if ((unitnumber = rtems_bsdnet_parse_driver_name (config, &unitname)) < 0)
    222222        return 0;
    223    
     223
    224224    /*
    225225     * Is driver free?
     
    241241     *  zero out the control structure
    242242     */
    243    
     243
    244244    memset((void *)sc, 0, sizeof(*sc));
    245    
     245
    246246    sc->unitnumber = unitnumber;
    247247    sc->int_ctrlr = AU1X00_IC0_ADDR;
     
    261261    /* If the ethernet controller is already set up, read the MAC address */
    262262    if ((*sc->en_reg & 0x33) == 0x33) {
    263         sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) & 
     263        sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) &
    264264                                   0xff);
    265265        sc->arpcom.ac_enaddr[4] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 0) &
     
    269269        sc->arpcom.ac_enaddr[2] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 16) &
    270270                                   0xff);
    271         sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) & 
     271        sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) &
    272272                                   0xff);
    273         sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) & 
     273        sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) &
    274274                                   0xff);
    275275    } else {
     
    282282        sc->arpcom.ac_enaddr[0] = 0x00;
    283283    }
    284    
     284
    285285
    286286    if (config->mtu) {
     
    291291
    292292    sc->acceptBroadcast = !config->ignore_broadcast;
    293    
     293
    294294    /*
    295295     * Set up network interface values
     
    318318void au1x00_emac_init(void *arg)
    319319{
    320     au1x00_emac_softc_t     *sc = arg;     
     320    au1x00_emac_softc_t     *sc = arg;
    321321    struct ifnet *ifp = &sc->arpcom.ac_if;
    322322
    323     /* 
    324      *This is for stuff that only gets done once (au1x00_emac_init() 
    325      * gets called multiple times 
     323    /*
     324     *This is for stuff that only gets done once (au1x00_emac_init()
     325     * gets called multiple times
    326326     */
    327327    if (sc->tx_daemon_tid == 0)
     
    329329        /* Set up EMAC hardware */
    330330        au1x00_emac_init_hw(sc);
    331        
    332        
     331
     332
    333333        /* install the interrupt handler */
    334334        if (sc->unitnumber == 0) {
     
    339339        AU1X00_IC_MASKCLR(sc->int_ctrlr) = sc->int_mask;
    340340        au_sync();
    341            
     341
    342342        /* set src bit */
    343343        AU1X00_IC_SRCSET(sc->int_ctrlr) = sc->int_mask;
    344        
     344
    345345        /* high level */
    346346        AU1X00_IC_CFG0SET(sc->int_ctrlr) = sc->int_mask;
    347347        AU1X00_IC_CFG1CLR(sc->int_ctrlr) = sc->int_mask;
    348348        AU1X00_IC_CFG2SET(sc->int_ctrlr) = sc->int_mask;
    349            
     349
    350350        /* assign to request 0 - negative logic */
    351351        AU1X00_IC_ASSIGNSET(sc->int_ctrlr) = sc->int_mask;
     
    353353
    354354        /* Start driver tasks */
    355         sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx", 
    356                                                  4096, 
    357                                                  au1x00_emac_tx_daemon, 
     355        sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx",
     356                                                 4096,
     357                                                 au1x00_emac_tx_daemon,
    358358                                                 sc);
    359    
    360         sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx", 
    361                                                  4096, 
    362                                                  au1x00_emac_rx_daemon, 
     359
     360        sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx",
     361                                                 4096,
     362                                                 au1x00_emac_rx_daemon,
    363363                                                 sc);
    364    
     364
    365365
    366366    }
     
    368368    if (ifp->if_flags & IFF_PROMISC)
    369369        printf ("Warning - AU1X00 EMAC doesn't support Promiscuous Mode!\n");
    370    
     370
    371371    /*
    372372     * Tell the world that we're running.
    373373     */
    374374    ifp->if_flags |= IFF_RUNNING;
    375    
    376     /*
    377      * start tx, rx 
    378      */
    379     AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE | 
     375
     376    /*
     377     * start tx, rx
     378     */
     379    AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE |
    380380                                             AU1X00_MAC_CTRL_RE);
    381381    au_sync();
    382    
     382
    383383
    384384} /* au1x00_emac_init() */
     
    391391
    392392    /* reset the MAC */
    393     *sc->en_reg = 0x40; 
     393    *sc->en_reg = 0x40;
    394394    au_sync();
    395395    for (i = 0; i < 10000; i++) {
     
    405405
    406406/*
    407     *sc->en_reg = (AU1X00_MAC_EN_CE | 
    408                    AU1X00_MAC_EN_E2 | 
    409                    AU1X00_MAC_EN_E1 | 
     407    *sc->en_reg = (AU1X00_MAC_EN_CE |
     408                   AU1X00_MAC_EN_E2 |
     409                   AU1X00_MAC_EN_E1 |
    410410                   AU1X00_MAC_EN_E0);
    411411*/
     
    446446    printk("mac_control was set to 0x%x\n", AU1X00_MAC_CONTROL(sc->ctrl_regs));
    447447    printk("mac_control addr is 0x%x\n", &AU1X00_MAC_CONTROL(sc->ctrl_regs));
    448    
     448
    449449    /* initialize our receive buffer descriptors */
    450450    for (i = 0; i < NUM_RX_DMA_BUFS; i++) {
     
    457457        /*
    458458         * The receive buffer must be aligned with a cache line
    459          * boundary. 
     459         * boundary.
    460460         */
    461461        if (mtod(m, uint32_t) & 0x1f) {
     
    492492{
    493493    au1x00_emac_softc_t *sc = ifp->if_softc;
    494    
     494
    495495    rtems_event_send(sc->tx_daemon_tid, START_TX_EVENT);
    496496    ifp->if_flags |= IFF_OACTIVE;
     
    500500{
    501501    struct ifnet *ifp = &sc->arpcom.ac_if;
    502    
     502
    503503    ifp->if_flags &= ~IFF_RUNNING;
    504    
     504
    505505    /*
    506506     * Stop the transmitter and receiver.
     
    508508
    509509    /* Disable TX/RX  */
    510     AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE | 
     510    AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE |
    511511                                      AU1X00_MAC_CTRL_RE);
    512512    au_sync();
     
    578578        /* while there are packets to receive */
    579579
    580         while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN | 
     580        while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN |
    581581                                                AU1X00_MAC_DMA_RXADDR_EN))) {
    582582            status = sc->rx_dma[sc->rx_head].stat;
     
    622622
    623623            /* If no errrors, accept packet */
    624             if ((status & (AU1X00_MAC_DMA_RXSTAT_CR | 
    625                            AU1X00_MAC_DMA_RXSTAT_DB | 
     624            if ((status & (AU1X00_MAC_DMA_RXSTAT_CR |
     625                           AU1X00_MAC_DMA_RXSTAT_DB |
    626626                           AU1X00_MAC_DMA_RXSTAT_RF)) == 0) {
    627627
     
    630630                /* find the start of the mbuf */
    631631                m = sc->rx_mbuf[sc->rx_head];
    632                
     632
    633633                /* set the length of the mbuf */
    634634                m->m_len = AU1X00_MAC_DMA_RXSTAT_LEN(sc->rx_dma[sc->rx_head].stat);
    635635                m->m_len -= 4; /* remove ethernet CRC */
    636                
     636
    637637                m->m_pkthdr.len = m->m_len;
    638                
     638
    639639                /* strip off the ethernet header from the mbuf */
    640640                /* but save the pointer to it */
    641641                eh = mtod (m, struct ether_header *);
    642642                m->m_data += sizeof(struct ether_header);
    643                
     643
    644644                /* give the received packet to the stack */
    645645                ether_input(ifp, eh, m);
     
    647647                MGETHDR(m, M_WAIT, MT_DATA);
    648648                MCLGET(m, M_WAIT);
    649                
     649
    650650                m->m_pkthdr.rcvif = ifp;
    651651                m->m_nextpkt = 0;
    652                
     652
    653653                /*
    654654                 * The receive buffer must be aligned with a cache line
    655                  * boundary. 
     655                 * boundary.
    656656                 */
    657657                {
     
    659659                  *p = (mtod(m, uint32_t) + 0x1f) & ~0x1f;
    660660                }
    661            
     661
    662662            } else {
    663663                sc->rx_dropped++;
     
    666666                m = sc->rx_mbuf[sc->rx_head];
    667667            }
    668            
     668
    669669            /* set up the receive dma to use the mbuf's cluster */
    670670            sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000);
     
    674674            sc->rx_dma[sc->rx_head].addr |= AU1X00_MAC_DMA_RXADDR_EN;
    675675            au_sync();
    676            
     676
    677677
    678678            /* increment the buffer index */
     
    698698        continue;
    699699    }
    700    
     700
    701701    /* copy the mbuf chain into the transmit buffer */
    702702    l = m;
     
    705705    while (l != NULL)
    706706    {
    707        
     707
    708708        memcpy(((char *)txbuf + pkt_offset), /* offset into pkt for mbuf */
    709                (char *)mtod(l, void *),      /* cast to void */ 
     709               (char *)mtod(l, void *),      /* cast to void */
    710710               l->m_len);                    /* length of this mbuf */
    711        
     711
    712712        pkt_offset += l->m_len;              /* update offset */
    713         l = l->m_next;                       /* get next mbuf, if any */     
     713        l = l->m_next;                       /* get next mbuf, if any */
    714714    }
    715715
     
    723723    sc->tx_dma[sc->tx_head].stat = 0;
    724724    sc->tx_dma[sc->tx_head].len = pkt_offset;
    725     sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) | 
     725    sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) |
    726726                                    AU1X00_MAC_DMA_TXADDR_EN);
    727727    au_sync();
    728728
    729729
    730     /* 
     730    /*
    731731     *Without this delay, some outgoing packets never
    732732     * make it out the device. Nothing in the documentation
     
    748748
    749749
    750        
     750
    751751/* Show interface statistics */
    752752void au1x00_emac_stats (au1x00_emac_softc_t *sc)
     
    770770    printf("       RX watchdog:%-8lu", sc->rx_watchdog);
    771771    printf("   RX dropped:%-8lu\n", sc->rx_dropped);
    772    
     772
    773773    printf("TX Packets:%-8lu", sc->tx_pkts);
    774774    printf("    TX Deferred:%-8lu", sc->tx_deferred);
     
    785785    au1x00_emac_softc_t *sc = ifp->if_softc;
    786786    int error = 0;
    787    
     787
    788788    switch (command) {
    789789    case SIOCGIFADDR:
     
    791791        ether_ioctl (ifp, command, data);
    792792        break;
    793        
     793
    794794    case SIOCSIFFLAGS:
    795795        switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
     
    798798            au1x00_emac_stop (sc);
    799799            break;
    800            
     800
    801801        case IFF_UP:
    802802            au1x00_emac_init (sc);
    803803            break;
    804            
     804
    805805        case IFF_UP | IFF_RUNNING:
    806806            au1x00_emac_stop (sc);
    807807            au1x00_emac_init (sc);
    808808            break;
    809            
     809
    810810        default:
    811811            break;
    812812        } /* switch (if_flags) */
    813813        break;
    814        
     814
    815815    case SIO_RTEMS_SHOW_STATS:
    816816        au1x00_emac_stats (sc);
    817817        break;
    818        
     818
    819819        /*
    820820         * FIXME: All sorts of multicast commands need to be added here!
     
    842842
    843843    /*
    844      * Since there's no easy way to find out the source of the 
     844     * Since there's no easy way to find out the source of the
    845845     * interrupt, we have to look at the tx and rx dma buffers
    846846     */
     
    851851        sc->rx_dma[sc->rx_tail].addr &= ~AU1X00_MAC_DMA_RXADDR_DN;
    852852        au_sync();
    853        
     853
    854854        sc->rx_tail++;
    855855        if (sc->rx_tail >= NUM_RX_DMA_BUFS) {
     
    866866        tx_flag = 1;
    867867        sc->tx_interrupts++;
    868        
     868
    869869        status = sc->tx_dma[sc->tx_tail].stat;
    870870        if (status & AU1X00_MAC_DMA_TXSTAT_DF) {
     
    877877            sc->tx_aborted++;
    878878        }
    879        
     879
    880880        sc->tx_dma[sc->tx_tail].addr = 0;
    881881        au_sync();
  • c/src/lib/libbsp/mips/csb350/start/start.S

    rd4b4664b refdfd48  
    44 *  Copyright (c) 2005 by Cogent Computer Systems
    55 *  Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in found in the file LICENSE in this distribution or at
     
    3030        .set    noreorder
    3131
    32         /* Get the address of start into $5 in a position independent 
     32        /* Get the address of start into $5 in a position independent
    3333         * fashion. This lets us know whether we have been relocated or not.
    3434         */
     
    4848        mtc0    v0, C0_SR
    49492:
    50 /* Fix high bits, if any, of the PC so that exception handling 
     50/* Fix high bits, if any, of the PC so that exception handling
    5151   doesn't get confused.  */
    5252        la v0, 3f
     
    7676           supposed to allocate stack space for parameters in registers in
    7777           the old MIPS ABIs.  We must do this even though we aren't passing
    78            arguments, because main might be declared to have them. 
     78           arguments, because main might be declared to have them.
    7979
    8080           Some ports need a larger alignment for the stack, so we subtract
     
    9999        move    a0,v0                   /* pass through the exit code */
    100100        .end    init
    101        
     101
    102102/*
    103103 * _sys_exit -- Exit from the application. Normally we cause a user trap
     
    122122        nop
    123123        .end _sys_exit
    124        
     124
    125125/* EOF crt0.S */
  • c/src/lib/libbsp/mips/csb350/startup/bspreset.c

    rd4b4664b refdfd48  
    1515{
    1616  void (*reset_func)(void);
    17  
     17
    1818  reset_func = (void *)0xbfc00000;
    1919
  • c/src/lib/libbsp/mips/csb350/startup/bspstart.c

    rd4b4664b refdfd48  
    3131void bsp_start( void )
    3232{
    33   unsigned int compare = 0; 
     33  unsigned int compare = 0;
    3434
    3535  mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
  • c/src/lib/libbsp/mips/csb350/timer/timer.c

    rd4b4664b refdfd48  
    1 /* 
     1/*
    22 *  This file implements a benchmark timer using the count/compare
    33 *  CP0 registers.
     
    55 *  Copyright (c) 2005 by Cogent Computer Systems
    66 *  Written by Jay Monkman <jtm@lopingdog.com>
    7  *     
     7 *
    88 *  The license and distribution terms for this file may be
    99 *  found in found in the file LICENSE in this distribution or at
  • c/src/lib/libbsp/mips/hurricane/clock/ckinit.c

    rd4b4664b refdfd48  
    9191 * These are set by clock driver during its init
    9292 */
    93  
     93
    9494rtems_device_major_number rtems_clock_major = ~0;
    9595rtems_device_minor_number rtems_clock_minor;
     
    164164  *  Hardware specific initialize goes here
    165165  */
    166  
     166
    167167  /* Set up USC heartbeat timer to generate interrupts */
    168168  disable_hbi();      /* Disable heartbeat interrupt in USC */
    169  
     169
    170170              /* Install interrupt handler */
    171171  Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
    172  
     172
    173173  init_hbt();        /* Initialize heartbeat timer */
    174  
     174
    175175  reset_wdt();      /* Reset watchdog timer */
    176  
     176
    177177  enable_wdi();      /* Enable watchdog interrupt in USC */
    178  
     178
    179179  enable_hbi();      /* Enable heartbeat interrupt in USC */
    180  
     180
    181181              /* Enable USC interrupt in MIPS processor */
    182182  mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
    183  
     183
    184184  /*
    185185  *  Schedule the clock cleanup routine to execute if the application exits.
     
    212212{
    213213  Install_clock( Clock_isr );
    214  
     214
    215215  /*
    216216   * make major/minor avail to others such as shared memory driver
    217217   */
    218  
     218
    219219  rtems_clock_major = major;
    220220  rtems_clock_minor = minor;
    221  
     221
    222222  return RTEMS_SUCCESSFUL;
    223223}
  • c/src/lib/libbsp/mips/hurricane/clock/clock.S

    rd4b4664b refdfd48  
    1 /*  clock.s 
     1/*  clock.s
    22 *
    33 *  This file contains the assembly code for the Hurricane BSP clock driver.
  • c/src/lib/libbsp/mips/hurricane/console/console.c

    rd4b4664b refdfd48  
    5555{
    5656  rtems_status_code status;
    57  
     57
    5858  status = rtems_io_register_name(
    5959    "/dev/console",
     
    6161    (rtems_device_minor_number) 0
    6262  );
    63  
     63
    6464  if (status != RTEMS_SUCCESSFUL)
    6565    rtems_fatal_error_occurred(status);
    66  
     66
    6767  return RTEMS_SUCCESSFUL;
    6868}
     
    158158  return RTEMS_SUCCESSFUL;
    159159}
    160  
     160
    161161/*
    162162 *  Close entry point
     
    190190  int maximum;
    191191  int count = 0;
    192  
     192
    193193  rw_args = (rtems_libio_rw_args_t *) arg;
    194194
     
    209209
    210210/*
    211  * write bytes to the serial port. Stdout and stderr are the same. 
     211 * write bytes to the serial port. Stdout and stderr are the same.
    212212 */
    213213
  • c/src/lib/libbsp/mips/hurricane/include/bsp.h

    rd4b4664b refdfd48  
    3636 *  This is very dependent on the clock speed of the target.
    3737 *
    38  *  NOTE: This macro generates a warning like "integer constant out 
     38 *  NOTE: This macro generates a warning like "integer constant out
    3939 *        of range" which is safe to ignore.  In 64 bit mode, unsigned32
    4040 *        types are actually 64 bits long so that comparisons between
  • c/src/lib/libbsp/mips/hurricane/start/start.S

    rd4b4664b refdfd48  
    2020COPYRIGHT IDT CORPORATION 1996
    2121LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
    22 */ 
     22*/
    2323
    2424/*************************************************************************
     
    3838
    3939
    40 #if 0   
     40#if 0
    4141        .extern _fdata,4                /* this is defined by the linker */
    4242        .extern _edata,4                /* this is defined by the linker */
     
    5454#define HARD_CODED_MEM_SIZE 0x1000000
    5555
    56 #define TMP_STKSIZE  1024 
    57 
    58 /*
    59 ** P_STACKSIZE is the size of the Prom Stack. 
    60 ** the prom stack grows downward 
     56#define TMP_STKSIZE  1024
     57
     58/*
     59** P_STACKSIZE is the size of the Prom Stack.
     60** the prom stack grows downward
    6161*/
    6262#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
     
    7373**              d) Set kernel/disabled mode
    7474**      2)  Initialize Cause Register
    75 **              a)  clear software interrupt bits       
     75**              a)  clear software interrupt bits
    7676**      3)  Determine FPU installed or not
    7777**              if not, clear CoProcessor 1 usable bit
     
    8585**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
    8686**      11)  Execute initialization code if the IDT/c library is to be used
    87 ** 
     87**
    8888**      12)  Jump to user's "main()" (boot_card() for RTEMS)
    8989**      13)  Jump to promexit
    9090**
    91 **      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
     91**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
    9292**      This is used to mark code specific to R3xxx or R4xxx processors.
    93 **      IDT/C 6.x defines __mips to be the ISA level for which we're 
    94 **      generating code. This is used to make sure the stack etc. is 
    95 **      double word aligned, when using -mips3 (default) or -mips2, 
     93**      IDT/C 6.x defines __mips to be the ISA level for which we're
     94**      generating code. This is used to make sure the stack etc. is
     95**      double word aligned, when using -mips3 (default) or -mips2,
    9696**      when compiling with IDT/C6.x
    9797**
     
    111111        mtc0    zero,C0_CAUSE           /* clear software interrupts */
    112112        nop
    113        
     113
    114114        la      t0,0xBE200000           /* on Hurricane board, enable interrupt output signal from UART ch. B */
    115115        li      t1,0x8                  /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
     
    120120
    121121/*
    122 **      check to see if an fpu is really plugged in 
     122**      check to see if an fpu is really plugged in
    123123*/
    124124        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
    125         mtc1    t3,fp0                  /* try to write them into fp0   */     
     125        mtc1    t3,fp0                  /* try to write them into fp0   */
    126126        mtc1    zero,fp1                /* try to write zero in fp      */
    127127        mfc1    t0,fp0
     
    141141        mtc0    v0, C0_SR               /* reset status register */
    1421422:
    143         la      gp, _gp                 
     143        la      gp, _gp
    144144
    145145#if 0
     
    1611614:      sw      zero,0(v0)
    162162        bltu    v0,v1,4b
    163         add     v0,4 
     163        add     v0,4
    164164
    165165
     
    174174*************************************************************************/
    175175        /* For MIPS 3, we need to be sure that the stack is aligned on a
    176          * double word boundary. 
     176         * double word boundary.
    177177         */
    178178        andi    t0, v0, 0x7
     
    186186        sub     v1, v1, (4*4)           /* overhead */
    187187        move    sp, v1                  /* set sp to top of stack */
    188 4:      sw      zero, 0(v0) 
     1884:      sw      zero, 0(v0)
    189189        bltu    v0, v1, 4b              /* clear out temp stack */
    190         add     v0, 4 
    191        
    192 /*      jal     init_exc_vecs */                /* install exception handlers */ 
     190        add     v0, 4
     191
     192/*      jal     init_exc_vecs */                /* install exception handlers */
    193193/*      nop */                          /* MUST do before memory probes */
    194194
     
    217217
    218218        /* For MIPS 3, we need to be sure that the stack (and hence v0
    219          * here) is aligned on a double word boundary. 
     219         * here) is aligned on a double word boundary.
    220220         */
    221221        andi    t0, v0, 0x7
     
    229229/**************************************************************************
    230230**
    231 **  Permanent Stack - now know top of memory, put permanent stack there 
    232 **
    233 ***************************************************************************/ 
     231**  Permanent Stack - now know top of memory, put permanent stack there
     232**
     233***************************************************************************/
    234234
    235235        la      t2, _fbss               /* cache mode as linked */
     
    245245        subu    v1, P_STACKSIZE         /* clear requested stack size */
    246246
    247 7:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */ 
     2477:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
    248248        bltu    v1,v0,7b
    249         add     v1, 4 
     249        add     v1, 4
    250250        .set    reorder
    251251
     
    259259**      If this chip supports a Translation Lookaside Buffer, clear it
    260260**
    261 ***************************************************************************/ 
     261***************************************************************************/
    262262
    263263        .set    noreorder
     
    280280/************************************************************************
    281281**
    282 **  Initialization required if using IDT/c or libc.a, standard C Lib 
     282**  Initialization required if using IDT/c or libc.a, standard C Lib
    283283**
    284284**  can SKIP if not necessary for application
     
    310310        beq     zero,zero,1b
    311311        nop
    312        
     312
    313313ENDFRAME(start)
    314314
     
    328328        b       13b                             # but loop back just in-case
    329329        nop
    330        
     330
    331331ENDFRAME(_sys_exit)
    332332
  • c/src/lib/libbsp/mips/hurricane/startup/bspstart.c

    rd4b4664b refdfd48  
    2020
    2121uint32_t bsp_clicks_per_microsecond;
    22  
     22
    2323/*
    2424 *  bsp_start
  • c/src/lib/libbsp/mips/hurricane/startup/exception.S

    rd4b4664b refdfd48  
    185185        ADDIU    sp,sp,-EXCP_STACK_SIZE
    186186
    187         STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
     187        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
    188188        STREG v0, R_V0*R_SZ(sp)
    189189        STREG v1, R_V1*R_SZ(sp)
     
    202202        mflo  t0
    203203        STREG t8, R_T8*R_SZ(sp)
    204         STREG t0, R_MDLO*R_SZ(sp) 
     204        STREG t0, R_MDLO*R_SZ(sp)
    205205        STREG t9, R_T9*R_SZ(sp)
    206206        mfhi  t0
    207207        STREG gp, R_GP*R_SZ(sp)
    208         STREG t0, R_MDHI*R_SZ(sp) 
     208        STREG t0, R_MDHI*R_SZ(sp)
    209209        STREG fp, R_FP*R_SZ(sp)
    210        
     210
    211211        .set noat
    212212        STREG AT, R_AT*R_SZ(sp)
     
    278278   *    restore stack
    279279   *  #endif
    280    * 
     280   *
    281281   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    282282   *    goto the label "exit interrupt (simple case)"
     
    312312        la      t0,__exceptionStackFrame
    313313        STREG   sp,(t0)
    314                                        
     314
    315315        jal     _Thread_Dispatch
    316316        NOP
     
    322322        NOP
    323323
    324 /* 
     324/*
    325325** turn interrupts back off while we restore context so
    326326** a badly timed interrupt won't accidentally mess things up
     
    336336#elif __mips == 1
    337337        /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
    338         li      t1,SR_IEC | SR_KUP | SR_KUC     
     338        li      t1,SR_IEC | SR_KUP | SR_KUC
    339339        not     t1
    340340        and     t0, t1
     
    348348        ** make sure previous int enable is on  because we're returning from an interrupt
    349349        ** which means interrupts have to be enabled
    350        
     350
    351351        li      t1,SR_IEP
    352352        or      t0,t1
     
    355355        mtc0    t0, C0_SR
    356356        NOP
    357        
     357
    358358  /*
    359359   *  prepare to get out of interrupt
     
    371371        LDREG t0, R_T0*R_SZ(sp)
    372372        mtlo  t8
    373         LDREG t8, R_MDHI*R_SZ(sp)           
     373        LDREG t8, R_MDHI*R_SZ(sp)
    374374        LDREG t1, R_T1*R_SZ(sp)
    375375        mthi  t8
     
    391391        LDREG v1, R_V1*R_SZ(sp)
    392392        LDREG v0, R_V0*R_SZ(sp)
    393        
     393
    394394        LDREG k1, R_EPC*R_SZ(sp)
    395395        mtc0  k1,C0_EPC
    396        
     396
    397397        .set noat
    398398        LDREG     AT, R_AT*R_SZ(sp)
     
    408408        /* Interrupts from USC320 are serviced here */
    409409        .global USC_isr
    410         .extern Clock_isr       
     410        .extern Clock_isr
    411411USC_isr:
    412412        /* check if it's a USC320 heartbeat interrupt */
     
    415415        nop                     /* reading from external device */
    416416        sll     k0,(31-21)      /* test bit 21 (HBI) */
    417        
     417
    418418        bgez    k0,USC_isr2     /* branch if not a heartbeat interrupt */
    419419        NOP
     
    435435USC_isr2:
    436436        j       ra              /* no serviceable interrupt, return without doing anything */
    437         nop             
     437        nop
    438438
    439439       .set    reorder
     
    451451        la      k0,INT_CFG3
    452452        sw      k1,(k0)
    453        
     453
    454454        la  k0,_brk_esr_link    /* Jump to next exception handler in PMON exception chain */
    455455        lw  k0,(k0)
     
    479479
    480480        .extern mon_onintr
    481        
     481
    482482/* Install interrupt handler in PMON exception handling chain */
    483483
     
    518518        li      t1,0xA5
    519519        sb      t1,(t0)
    520        
     520
    521521        la      t0,WD_HBI       # Initialize heatbeat and watchdog timers
    522522
    523                                 # (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds 
     523                                # (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
    524524                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
    525525                                # Watchdog period = 4000 * 5 = 20000 microseconds
    526526        li      t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
    527527
    528                                 # (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds 
     528                                # (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
    529529                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
    530530                                # Watchdog period = 1000 * 20 = 20000 microseconds
    531531        li      t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
    532532
    533                                 # (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds 
     533                                # (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
    534534                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
    535535                                # Watchdog period = 10000 * 20 = 200000 microseconds
     
    537537
    538538        sw      t1,(t0)
    539        
     539
    540540        la      t0,SYSTEM       # Lock USC registers
    541541        li      t1,0x60
    542542        sb      t1,(t0)
    543        
     543
    544544        .set reorder
    545545        j       ra
     
    556556
    557557        la      t0,WD_HBI+2     # Load address watchdog timer reset byte
    558         li      t1,WD_INIT     
     558        li      t1,WD_INIT
    559559        sb      t1,(t0)
    560        
     560
    561561        .set reorder
    562562        j       ra
     
    576576        and     t1,t1,t2
    577577        sw      t1,(t0)
    578        
     578
    579579        .set reorder
    580580        j       ra
     
    589589FRAME(enable_hbi,sp,0,ra)
    590590        .set noreorder
    591        
     591
    592592        la      t0,INT_CFG3     # Enable heartbeat interrupt in USC320
    593593        lw      t1,(t0)
     
    595595        or      t1,t1,t2
    596596        sw      t1,(t0)
    597        
     597
    598598        .set reorder
    599599        j       ra
     
    613613        and     t1,t1,t2
    614614        sw      t1,(t0)
    615        
     615
    616616        .set reorder
    617617        j       ra
     
    627627FRAME(enable_wdi,sp,0,ra)
    628628        .set noreorder
    629        
     629
    630630        la      t0,INT_CFG1     # Enable watchdog interrupt in USC320
    631631        lw      t1,(t0)
     
    633633        or      t1,t1,t2
    634634        sw      t1,(t0)
    635        
     635
    636636        .set reorder
    637637        j       ra
     
    646646FRAME(disable_wdi,sp,0,ra)
    647647        .set noreorder
    648        
     648
    649649        la      t0,INT_CFG1     # Disable watchdog interrupt in USC320
    650650        lw      t1,(t0)
     
    652652        and     t1,t1,t2
    653653        sw      t1,(t0)
    654        
     654
    655655        la      t0,INT_STAT     # Clear watchdog interrupt status bit
    656656        li      t1,WDI_MASK
    657657        sw      t1,(t0)
    658        
     658
    659659        .set reorder
    660660        j       ra
     
    667667
    668668k1tmp:  .word   0       /* Temporary strage for K1 during interrupt service */
    669        
     669
    670670/*************************************************************
    671671*
     
    677677        .word   0
    678678        .word   hurricane_ISR_Handler
    679        
     679
    680680        /* Break exception service routine link */
    681681        .global _brk_esr_link
     
    685685
    686686
    687        
    688 
     687
     688
  • c/src/lib/libbsp/mips/hurricane/startup/idttlb.S

    rd4b4664b refdfd48  
    183183#if __mips == 1
    184184        .set    noreorder
    185         mfc0    v0,C0_TLBHI             # fetch tlb high 
     185        mfc0    v0,C0_TLBHI             # fetch tlb high
    186186        nop
    187187        and     v0,TLBHI_PIDMASK        # isolate and position
     
    216216        and     a0,TLBHI_VPNMASK        /* isolate just the vpn */
    217217        and     t0,~SR_PE               /* don't inadvertantly clear pe */
    218         mtc0    zero,C0_SR 
    219         mfc0    t1,C0_TLBHI     
     218        mtc0    zero,C0_SR
     219        mfc0    t1,C0_TLBHI
    220220        sll     a1,TLBHI_PIDSHIFT       /* possition the pid */
    221221        and     a1,TLBHI_PIDMASK
     
    268268#if __mips == 1
    269269        .set    noreorder
    270         mfc0    t0,C0_TLBHI             # fetch the current hi 
     270        mfc0    t0,C0_TLBHI             # fetch the current hi
    271271        mfc0    v0,C0_SR                # fetch the status reg.
    272272        li      t2,K0BASE&TLBHI_VPNMASK
     
    326326        mtc0    zero,C0_SR
    327327        mtc0    a1,C0_TLBHI             # set the hi entry
    328         mtc0    a2,C0_TLBLO             # set the lo entry 
     328        mtc0    a2,C0_TLBLO             # set the lo entry
    329329        mtc0    a0,C0_INX               # load the index
    330330        nop
    331331        tlbwi                           # put the hi/lo in tlb entry indexed
    332332        nop
    333         mtc0    a3,C0_TLBHI             # put back the tlb hi reg 
    334         mtc0    v0,C0_SR                # restore the status register 
     333        mtc0    a3,C0_TLBHI             # put back the tlb hi reg
     334        mtc0    v0,C0_SR                # restore the status register
    335335        j       ra
    336336        nop
     
    354354        mfc0    v0,C0_SR                # save SR and disable interrupts
    355355        mtc0    zero,C0_SR
    356         mtc0    t2,C0_PAGEMASK          # set 
     356        mtc0    t2,C0_PAGEMASK          # set
    357357        mtc0    a1,C0_TLBHI             # set VPN and TLBPID
    358358        mtc0    a2,C0_TLBLO0            # set PPN and access bits
  • c/src/lib/libbsp/mips/rbtx4925/console/console-io.c

    rd4b4664b refdfd48  
    7272    (rtems_device_minor_number) 0
    7373  );
    74  
     74
    7575  if (status != RTEMS_SUCCESSFUL)
    7676    rtems_fatal_error_occurred(status);
     
    169169  return RTEMS_SUCCESSFUL;
    170170}
    171  
     171
    172172/*
    173173 *  Close entry point
     
    201201  int maximum;
    202202  int count = 0;
    203  
     203
    204204  rw_args = (rtems_libio_rw_args_t *) arg;
    205205
     
    220220
    221221/*
    222  * write bytes to the serial port. Stdout and stderr are the same. 
     222 * write bytes to the serial port. Stdout and stderr are the same.
    223223 */
    224224
  • c/src/lib/libbsp/mips/rbtx4925/start/start.S

    rd4b4664b refdfd48  
    2222
    2323  $Id$
    24 */ 
     24*/
    2525
    2626/*************************************************************************
     
    3939#warning The call is "void boot_card(const char* cmdline);"
    4040#warning Please check and remove these warnings.
    41        
    42         .extern mon_flush_cache         
    43 
    44 #if 0   
     41
     42        .extern mon_flush_cache
     43
     44#if 0
    4545        .extern _fdata,4                /* this is defined by the linker */
    4646        .extern _edata,4                /* this is defined by the linker */
     
    6060
    6161/*
    62 ** P_STACKSIZE is the size of the Prom Stack. 
    63 ** the prom stack grows downward 
     62** P_STACKSIZE is the size of the Prom Stack.
     63** the prom stack grows downward
    6464*/
    6565#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
     
    7777**              d) Set kernel/disabled mode
    7878**      2)  Initialize Cause Register
    79 **              a)  clear software interrupt bits       
     79**              a)  clear software interrupt bits
    8080**      3)  Determine FPU installed or not
    8181**              if not, clear CoProcessor 1 usable bit
     
    8989**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
    9090**      11)  Execute initialization code if the IDT/c library is to be used
    91 ** 
     91**
    9292**      12)  Jump to user's "main()"
    9393**      13)  Jump to promexit
    9494**
    95 **      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
     95**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
    9696**      This is used to mark code specific to R3xxx or R4xxx processors.
    97 **      IDT/C 6.x defines __mips to be the ISA level for which we're 
    98 **      generating code. This is used to make sure the stack etc. is 
    99 **      double word aligned, when using -mips3 (default) or -mips2, 
     97**      IDT/C 6.x defines __mips to be the ISA level for which we're
     98**      generating code. This is used to make sure the stack etc. is
     99**      double word aligned, when using -mips3 (default) or -mips2,
    100100**      when compiling with IDT/C6.x
    101101**
     
    120120
    121121/*
    122 **      check to see if a fpu is really plugged in 
     122**      check to see if a fpu is really plugged in
    123123*/
    124124        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
    125         mtc1    t3,fp0                  /* try to write them into fp0   */     
     125        mtc1    t3,fp0                  /* try to write them into fp0   */
    126126        mtc1    zero,fp1                /* try to write zero in fp      */
    127127        mfc1    t0,fp0
     
    141141        mtc0    v0, C0_SR               /* reset status register */
    1421422:
    143         la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/                   
     143        la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/
    144144
    145145#if 0
     
    1611614:      sw      zero,0(v0)
    162162        bltu    v0,v1,4b
    163         add     v0,4 
     163        add     v0,4
    164164
    165165
     
    174174*************************************************************************/
    175175        /* For MIPS 3, we need to be sure that the stack is aligned on a
    176          * double word boundary. 
     176         * double word boundary.
    177177         */
    178178        andi    t0, v0, 0x7
     
    186186        sub     v1, v1, (4*4)           /* overhead */
    187187        move    sp, v1                  /* set sp to top of stack */
    188 4:      sw      zero, 0(v0) 
     1884:      sw      zero, 0(v0)
    189189        bltu    v0, v1, 4b              /* clear out temp stack */
    190         add     v0, 4 
    191        
    192 /*      jal     init_exc_vecs */                /* install exception handlers */ 
     190        add     v0, 4
     191
     192/*      jal     init_exc_vecs */                /* install exception handlers */
    193193/*      nop */                          /* MUST do before memory probes */
    194194
    195195                                        /* Force processor into uncached space during memory/cache probes */
    196196        la      v0, 5f
    197         li      v1, K1BASE             
     197        li      v1, K1BASE
    198198        or      v0, v1
    199199        j       v0
     
    217217
    218218        /* For MIPS 3, we need to be sure that the stack (and hence v0
    219          * here) is aligned on a double word boundary. 
     219         * here) is aligned on a double word boundary.
    220220         */
    221221        andi    t0, v0, 0x7
     
    229229/**************************************************************************
    230230**
    231 **  Permanent Stack - now know top of memory, put permanent stack there 
    232 **
    233 ***************************************************************************/ 
     231**  Permanent Stack - now know top of memory, put permanent stack there
     232**
     233***************************************************************************/
    234234
    235235        la      t2, _fbss               /* cache mode as linked */
     
    245245        subu    v1, P_STACKSIZE         /* clear requested stack size */
    246246
    247 7:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */ 
     2477:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
    248248        bltu    v1,v0,7b
    249         add     v1, 4 
     249        add     v1, 4
    250250
    251251
     
    287287        nop
    288288
    289 /* Lock first 4k of PMON into instruction cache. This includes interrupt service code which 
     289/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
    290290 we don't want to run out of slow flash device. */
    291291
    292292        la      t0,0x9fc00000
    293293        li      t1, 0x1000
    294        
     294
    295295        move    t3, t0
    296296        addu    t1, t0, t1
     
    315315/*
    316316** Clear Translation Lookaside Buffer (TLB)
    317 */ 
     317*/
    318318        jal     init_tlb                /* clear the tlb */
    319319
     
    332332        beq     zero,zero,1b
    333333        nop
    334        
     334
    335335ENDFRAME(start)
    336336
     
    350350        b       13b                             # but loop back just in-case
    351351        nop
    352        
     352
    353353ENDFRAME(_sys_exit)
    354354
  • c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c

    rd4b4664b refdfd48  
    1717#include <bsp.h>
    1818#include <libcpu/isr_entries.h>
    19  
     19
    2020/*
    2121 *  bsp_start
  • c/src/lib/libbsp/mips/rbtx4925/startup/exception.S

    rd4b4664b refdfd48  
    138138        .set noreorder
    139139
    140 #if 0   
     140#if 0
    141141/* Activate TX4925 PIO19 signal for diagnostics */
    142142        lui     k0,0xff1f
     
    149149        sw      k1,(k0)
    150150#endif
    151        
     151
    152152        mfc0 k0,C0_CAUSE        /* Determine if an interrupt generated this exception */
    153153        nop
     
    191191        ADDIU    sp,sp,-EXCP_STACK_SIZE
    192192
    193         STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
     193        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
    194194        STREG v0, R_V0*R_SZ(sp)
    195195        STREG v1, R_V1*R_SZ(sp)
     
    208208        mflo  t0
    209209        STREG t8, R_T8*R_SZ(sp)
    210         STREG t0, R_MDLO*R_SZ(sp) 
     210        STREG t0, R_MDLO*R_SZ(sp)
    211211        STREG t9, R_T9*R_SZ(sp)
    212212        mfhi  t0
    213213        STREG gp, R_GP*R_SZ(sp)
    214         STREG t0, R_MDHI*R_SZ(sp) 
     214        STREG t0, R_MDHI*R_SZ(sp)
    215215        STREG fp, R_FP*R_SZ(sp)
    216        
     216
    217217        .set noat
    218218        STREG AT, R_AT*R_SZ(sp)
     
    288288        nop
    289289#endif
    290        
     290
    291291_ISR_Handler_cleanup:
    292292
     
    318318   *    restore stack
    319319   *  #endif
    320    * 
     320   *
    321321   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    322322   *    goto the label "exit interrupt (simple case)"
     
    352352        la      t0,__exceptionStackFrame
    353353        STREG   sp,(t0)
    354                                        
     354
    355355        jal     _Thread_Dispatch
    356356        NOP
     
    362362        NOP
    363363
    364 /* 
     364/*
    365365** turn interrupts back off while we restore context so
    366366** a badly timed interrupt won't accidentally mess things up
     
    376376        mtc0    t0, C0_SR
    377377        NOP
    378        
     378
    379379  /*
    380380   *  prepare to get out of interrupt
     
    392392        LDREG t0, R_T0*R_SZ(sp)
    393393        mtlo  t8
    394         LDREG t8, R_MDHI*R_SZ(sp)           
     394        LDREG t8, R_MDHI*R_SZ(sp)
    395395        LDREG t1, R_T1*R_SZ(sp)
    396396        mthi  t8
     
    412412        LDREG v1, R_V1*R_SZ(sp)
    413413        LDREG v0, R_V0*R_SZ(sp)
    414        
     414
    415415        LDREG k1, R_EPC*R_SZ(sp)
    416416        mtc0  k1,C0_EPC
    417        
     417
    418418        .set noat
    419419        LDREG     AT, R_AT*R_SZ(sp)
     
    429429#if 0
    430430        .global int7_isr
    431         .extern Interrupt_7_isr 
     431        .extern Interrupt_7_isr
    432432int7_isr:
    433433        /* Verify interrupt is from Timer */
     
    465465        sw      k1,(k0)
    466466#endif
    467        
     467
    468468        la  k0,_brk_esr_link    /* Jump to next exception handler in PMON exception chain */
    469469        lw  k0,(k0)
     
    493493
    494494        .extern mon_onintr
    495        
     495
    496496/* Install interrupt handler in PMON exception handling chain */
    497497
     
    523523FRAME(enable_int7,sp,0,ra)
    524524        .set noreorder
    525        
     525
    526526        la      t0,IRDM1        # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
    527527        li      t1,0x0
     
    531531        li      t1,0x200
    532532        sw      t1,(t0)
    533        
     533
    534534        la      t0,IRMSK        # Set interrupt controller mask
    535535        li      t1,0x0
     
    567567*       Diagnostic code that can be hooked to PMON interrupt handler.
    568568*       Generates pulse on PIO22 pin.
    569 *       Called from _exception code in PMON (see mips.s of PMON). 
     569*       Called from _exception code in PMON (see mips.s of PMON).
    570570*       Return address is located in k1.
    571571*/
     
    610610
    611611k1tmp:  .word   0       /* Temporary strage for K1 during interrupt service */
    612        
     612
    613613/*************************************************************
    614614*
     
    620620        .word   0
    621621        .word   rbtx4925_ISR_Handler
    622        
     622
    623623        /* Break exception service routine link */
    624624        .global _brk_esr_link
     
    628628
    629629
    630        
    631 
     630
     631
  • c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S

    rd4b4664b refdfd48  
    187187#if __mips == 1
    188188        .set    noreorder
    189         mfc0    v0,C0_TLBHI             # fetch tlb high 
     189        mfc0    v0,C0_TLBHI             # fetch tlb high
    190190        nop
    191191        and     v0,TLBHI_PIDMASK        # isolate and position
     
    220220        and     a0,TLBHI_VPNMASK        /* isolate just the vpn */
    221221        and     t0,~SR_PE               /* don't inadvertantly clear pe */
    222         mtc0    zero,C0_SR 
    223         mfc0    t1,C0_TLBHI     
     222        mtc0    zero,C0_SR
     223        mfc0    t1,C0_TLBHI
    224224        sll     a1,TLBHI_PIDSHIFT       /* possition the pid */
    225225        and     a1,TLBHI_PIDMASK
     
    272272#if __mips == 1
    273273        .set    noreorder
    274         mfc0    t0,C0_TLBHI             # fetch the current hi 
     274        mfc0    t0,C0_TLBHI             # fetch the current hi
    275275        mfc0    v0,C0_SR                # fetch the status reg.
    276276        li      t2,K0BASE&TLBHI_VPNMASK
     
    330330        mtc0    zero,C0_SR
    331331        mtc0    a1,C0_TLBHI             # set the hi entry
    332         mtc0    a2,C0_TLBLO             # set the lo entry 
     332        mtc0    a2,C0_TLBLO             # set the lo entry
    333333        mtc0    a0,C0_INX               # load the index
    334334        nop
    335335        tlbwi                           # put the hi/lo in tlb entry indexed
    336336        nop
    337         mtc0    a3,C0_TLBHI             # put back the tlb hi reg 
    338         mtc0    v0,C0_SR                # restore the status register 
     337        mtc0    a3,C0_TLBHI             # put back the tlb hi reg
     338        mtc0    v0,C0_SR                # restore the status register
    339339        j       ra
    340340        nop
     
    358358        mfc0    v0,C0_SR                # save SR and disable interrupts
    359359        mtc0    zero,C0_SR
    360         mtc0    t2,C0_PAGEMASK          # set 
     360        mtc0    t2,C0_PAGEMASK          # set
    361361        mtc0    a1,C0_TLBHI             # set VPN and TLBPID
    362362        mtc0    a2,C0_TLBLO0            # set PPN and access bits
  • c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h

    rd4b4664b refdfd48  
    99 *
    1010 * mips_start_of_legal_notice
    11  * 
     11 *
    1212 * Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
    1313 *
     
    5353 * third party.
    5454 *
    55  * 
     55 *
    5656 * mips_end_of_legal_notice
    57  * 
     57 *
    5858 *
    5959 ************************************************************************/
     
    171171 *  ------------
    172172 *
    173  *  'rc' (OUT) : Return code 
     173 *  'rc' (OUT) : Return code
    174174 *
    175175 *  Return values :
     
    179179 *
    180180 ************************************************************************/
    181 typedef void 
     181typedef void
    182182(*t_yamon_exit)(
    183183    t_yamon_uint32 rc );        /* Return code                          */
     
    208208 *
    209209 ************************************************************************/
    210 typedef void 
     210typedef void
    211211(*t_yamon_print)(
    212212    t_yamon_uint32 port, /* Output port (not used, always tty0)         */
     
    239239 *
    240240 ************************************************************************/
    241 typedef void 
     241typedef void
    242242(*t_yamon_print_count)(
    243243    t_yamon_uint32 port,        /* Output port (not used, always tty0   */
     
    358358 *  Registers an exception handler, also known as an "Exception Service
    359359 *  Routine" (ESR) for the specified exception.
    360  * 
     360 *
    361361 *  Two special exception IDs are defined :
    362362 *      YAMON_DEFAULT_HANDLER used for a default ESR.
    363363 *      YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
    364  *     
     364 *
    365365 *  The default ESR is called if no other ESR is registered
    366366 *  for an exception. If no default ESR is registered, a static
     
    368368 *  This function prints out the registers and halts.
    369369 *
    370  *  Deregistration of an ESR may be be done by calling this function 
     370 *  Deregistration of an ESR may be be done by calling this function
    371371 *  with 'esr' set to NULL.
    372372 *  An ESR can also be deregistered using the 'yamon_deregister_esr'
    373373 *  function.
    374374 *
    375  *  An ESR may be registered even if a previously registered 
     375 *  An ESR may be registered even if a previously registered
    376376 *  ESR has not been deregistered. In this case the previously
    377377 *  registered ESR is lost.
    378378 *
    379  *  The ESR will get called with registers in the state they were 
    380  *  when the exception occurred. This includes all CP0 registers and 
     379 *  The ESR will get called with registers in the state they were
     380 *  when the exception occurred. This includes all CP0 registers and
    381381 *  CPU registers $0..$31, except for k0,k1 ($26,$27).
    382382 *
     
    384384 *  call the return function passed in the 'retfunc' parameter.
    385385 *
    386  *  Case 1 : 'retfunc' called by ESR registered for the 
     386 *  Case 1 : 'retfunc' called by ESR registered for the
    387387 *           INTERRUPT exception.
    388388 *
     
    397397 *  Case 3 : 'retfunc' is called by the ESR registered as default ESR.
    398398 *
    399  *  The exception will be handled as though no ESR is registered 
     399 *  The exception will be handled as though no ESR is registered
    400400 *  (i.e. the "super default" function is called).
    401401 *
     
    437437 *
    438438 *  Deregisters ESR..
    439  * 
     439 *
    440440 *  Parameters :
    441441 *  ------------
     
    465465 *  -------------
    466466 *
    467  *  Registers an Interrupt Service Routine (ISR) for the specified 
     467 *  Registers an Interrupt Service Routine (ISR) for the specified
    468468 *  CPU interrupt.
    469469 *  The highest service priority is attached to HW-INT5, which is
     
    475475 *  A special ID is defined :
    476476 *      YAMON_DEFAULT_HANDLER used for a default ISR.
    477  *     
     477 *
    478478 *  The default ISR is called if no other ISR is registered
    479479 *  for a CPU interrupt.
     
    481481 *  Deregistration of the default ISR may be done by calling
    482482 *  this function with 'isr' set to NULL.
    483  *  Also, a new default ISR may be registered even if a 
     483 *  Also, a new default ISR may be registered even if a
    484484 *  previously registered ISR has not been deregistered.
    485  *  ISRs for specific CPU interrupts must be deregistered using 
     485 *  ISRs for specific CPU interrupts must be deregistered using
    486486 *  'yamon_deregister_cpu_isr'.
    487487 *
     
    522522 *
    523523 *  Deregisters ISR for CPU interrupt.
    524  * 
     524 *
    525525 *  Parameters :
    526526 *  ------------
     
    550550 *  -------------
    551551 *
    552  *  Registers an Interrupt Service Routine (ISR) for the specified 
    553  *  source in the interrupt controller. 
     552 *  Registers an Interrupt Service Routine (ISR) for the specified
     553 *  source in the interrupt controller.
    554554 *
    555555 *  A special ID is defined :
    556556 *      YAMON_DEFAULT_HANDLER used for a default ISR.
    557  *     
     557 *
    558558 *  The default ISR is called if no other ISR is registered
    559559 *  for an interrupt.
     
    561561 *  Deregistration of the default ISR may be done by calling
    562562 *  this function with 'isr' set to NULL.
    563  *  Also, a new default ISR may be registered even if a 
     563 *  Also, a new default ISR may be registered even if a
    564564 *  previously registered ISR has not been deregistered.
    565  *  ISRs for specific interrupts must be deregistered using 
     565 *  ISRs for specific interrupts must be deregistered using
    566566 *  'yamon_deregister_ic_isr'.
    567567 *
     
    602602 *
    603603 *  Deregisters ISR for source in interrupt controller.
    604  * 
     604 *
    605605 *  Parameters :
    606606 *  ------------
  • c/src/lib/libbsp/mips/rbtx4938/console/console-io.c

    rd4b4664b refdfd48  
    7474    (rtems_device_minor_number) 0
    7575  );
    76  
     76
    7777  if (status != RTEMS_SUCCESSFUL)
    7878    rtems_fatal_error_occurred(status);
     
    175175  return RTEMS_SUCCESSFUL;
    176176}
    177  
     177
    178178/*
    179179 *  Close entry point
     
    207207  int maximum;
    208208  int count = 0;
    209  
     209
    210210  rw_args = (rtems_libio_rw_args_t *) arg;
    211211
     
    226226
    227227/*
    228  * write bytes to the serial port. Stdout and stderr are the same. 
     228 * write bytes to the serial port. Stdout and stderr are the same.
    229229 */
    230230
  • c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h

    rd4b4664b refdfd48  
    99 *
    1010 * mips_start_of_legal_notice
    11  * 
     11 *
    1212 * Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
    1313 *
     
    5353 * third party.
    5454 *
    55  * 
     55 *
    5656 * mips_end_of_legal_notice
    57  * 
     57 *
    5858 *
    5959 ************************************************************************/
     
    171171 *  ------------
    172172 *
    173  *  'rc' (OUT) : Return code 
     173 *  'rc' (OUT) : Return code
    174174 *
    175175 *  Return values :
     
    179179 *
    180180 ************************************************************************/
    181 typedef void 
     181typedef void
    182182(*t_yamon_exit)(
    183183    t_yamon_uint32 rc );        /* Return code                          */
     
    208208 *
    209209 ************************************************************************/
    210 typedef void 
     210typedef void
    211211(*t_yamon_print)(
    212212    t_yamon_uint32 port, /* Output port (not used, always tty0)         */
     
    239239 *
    240240 ************************************************************************/
    241 typedef void 
     241typedef void
    242242(*t_yamon_print_count)(
    243243    t_yamon_uint32 port,        /* Output port (not used, always tty0   */
     
    358358 *  Registers an exception handler, also known as an "Exception Service
    359359 *  Routine" (ESR) for the specified exception.
    360  * 
     360 *
    361361 *  Two special exception IDs are defined :
    362362 *      YAMON_DEFAULT_HANDLER used for a default ESR.
    363363 *      YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
    364  *     
     364 *
    365365 *  The default ESR is called if no other ESR is registered
    366366 *  for an exception. If no default ESR is registered, a static
     
    368368 *  This function prints out the registers and halts.
    369369 *
    370  *  Deregistration of an ESR may be be done by calling this function 
     370 *  Deregistration of an ESR may be be done by calling this function
    371371 *  with 'esr' set to NULL.
    372372 *  An ESR can also be deregistered using the 'yamon_deregister_esr'
    373373 *  function.
    374374 *
    375  *  An ESR may be registered even if a previously registered 
     375 *  An ESR may be registered even if a previously registered
    376376 *  ESR has not been deregistered. In this case the previously
    377377 *  registered ESR is lost.
    378378 *
    379  *  The ESR will get called with registers in the state they were 
    380  *  when the exception occurred. This includes all CP0 registers and 
     379 *  The ESR will get called with registers in the state they were
     380 *  when the exception occurred. This includes all CP0 registers and
    381381 *  CPU registers $0..$31, except for k0,k1 ($26,$27).
    382382 *
     
    384384 *  call the return function passed in the 'retfunc' parameter.
    385385 *
    386  *  Case 1 : 'retfunc' called by ESR registered for the 
     386 *  Case 1 : 'retfunc' called by ESR registered for the
    387387 *           INTERRUPT exception.
    388388 *
     
    397397 *  Case 3 : 'retfunc' is called by the ESR registered as default ESR.
    398398 *
    399  *  The exception will be handled as though no ESR is registered 
     399 *  The exception will be handled as though no ESR is registered
    400400 *  (i.e. the "super default" function is called).
    401401 *
     
    437437 *
    438438 *  Deregisters ESR..
    439  * 
     439 *
    440440 *  Parameters :
    441441 *  ------------
     
    465465 *  -------------
    466466 *
    467  *  Registers an Interrupt Service Routine (ISR) for the specified 
     467 *  Registers an Interrupt Service Routine (ISR) for the specified
    468468 *  CPU interrupt.
    469469 *  The highest service priority is attached to HW-INT5, which is
     
    475475 *  A special ID is defined :
    476476 *      YAMON_DEFAULT_HANDLER used for a default ISR.
    477  *     
     477 *
    478478 *  The default ISR is called if no other ISR is registered
    479479 *  for a CPU interrupt.
     
    481481 *  Deregistration of the default ISR may be done by calling
    482482 *  this function with 'isr' set to NULL.
    483  *  Also, a new default ISR may be registered even if a 
     483 *  Also, a new default ISR may be registered even if a
    484484 *  previously registered ISR has not been deregistered.
    485  *  ISRs for specific CPU interrupts must be deregistered using 
     485 *  ISRs for specific CPU interrupts must be deregistered using
    486486 *  'yamon_deregister_cpu_isr'.
    487487 *
     
    522522 *
    523523 *  Deregisters ISR for CPU interrupt.
    524  * 
     524 *
    525525 *  Parameters :
    526526 *  ------------
     
    550550 *  -------------
    551551 *
    552  *  Registers an Interrupt Service Routine (ISR) for the specified 
    553  *  source in the interrupt controller. 
     552 *  Registers an Interrupt Service Routine (ISR) for the specified
     553 *  source in the interrupt controller.
    554554 *
    555555 *  A special ID is defined :
    556556 *      YAMON_DEFAULT_HANDLER used for a default ISR.
    557  *     
     557 *
    558558 *  The default ISR is called if no other ISR is registered
    559559 *  for an interrupt.
     
    561561 *  Deregistration of the default ISR may be done by calling
    562562 *  this function with 'isr' set to NULL.
    563  *  Also, a new default ISR may be registered even if a 
     563 *  Also, a new default ISR may be registered even if a
    564564 *  previously registered ISR has not been deregistered.
    565  *  ISRs for specific interrupts must be deregistered using 
     565 *  ISRs for specific interrupts must be deregistered using
    566566 *  'yamon_deregister_ic_isr'.
    567567 *
     
    602602 *
    603603 *  Deregisters ISR for source in interrupt controller.
    604  * 
     604 *
    605605 *  Parameters :
    606606 *  ------------
  • c/src/lib/libbsp/mips/rbtx4938/start/start.S

    rd4b4664b refdfd48  
    2222
    2323  $Id$
    24 */ 
     24*/
    2525
    2626/*************************************************************************
     
    4343/* #include <idtmon.h>  */
    4444
    45         .extern mon_flush_cache         
    46 
    47 #if 0   
     45        .extern mon_flush_cache
     46
     47#if 0
    4848        .extern _fdata,4                /* this is defined by the linker */
    4949        .extern _edata,4                /* this is defined by the linker */
     
    6060#define PMON_VECTOR 0xbfc00500
    6161
    62 #define TMP_STKSIZE  1024 
    63 
    64 /*
    65 ** P_STACKSIZE is the size of the Prom Stack. 
    66 ** the prom stack grows downward 
     62#define TMP_STKSIZE  1024
     63
     64/*
     65** P_STACKSIZE is the size of the Prom Stack.
     66** the prom stack grows downward
    6767*/
    6868#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
     
    7979**              d) Set kernel/disabled mode
    8080**      2)  Initialize Cause Register
    81 **              a)  clear software interrupt bits       
     81**              a)  clear software interrupt bits
    8282**      3)  Determine FPU installed or not
    8383**              if not, clear CoProcessor 1 usable bit
     
    9191**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
    9292**      11)  Execute initialization code if the IDT/c library is to be used
    93 ** 
     93**
    9494**      12)  Jump to user's "main()"
    9595**      13)  Jump to promexit
    9696**
    97 **      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
     97**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
    9898**      This is used to mark code specific to R3xxx or R4xxx processors.
    99 **      IDT/C 6.x defines __mips to be the ISA level for which we're 
    100 **      generating code. This is used to make sure the stack etc. is 
    101 **      double word aligned, when using -mips3 (default) or -mips2, 
     99**      IDT/C 6.x defines __mips to be the ISA level for which we're
     100**      generating code. This is used to make sure the stack etc. is
     101**      double word aligned, when using -mips3 (default) or -mips2,
    102102**      when compiling with IDT/C6.x
    103103**
     
    122122
    123123/*
    124 **      check to see if a fpu is really plugged in 
     124**      check to see if a fpu is really plugged in
    125125*/
    126126        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
    127         mtc1    t3,fp0                  /* try to write them into fp0   */     
     127        mtc1    t3,fp0                  /* try to write them into fp0   */
    128128        mtc1    zero,fp1                /* try to write zero in fp      */
    129129        mfc1    t0,fp0
     
    143143        mtc0    v0, C0_SR               /* reset status register */
    1441442:
    145         la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/                   
     145        la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/
    146146
    147147#if 0
     
    1631634:      sw      zero,0(v0)
    164164        bltu    v0,v1,4b
    165         add     v0,4 
     165        add     v0,4
    166166
    167167
     
    176176*************************************************************************/
    177177        /* For MIPS 3, we need to be sure that the stack is aligned on a
    178          * double word boundary. 
     178         * double word boundary.
    179179         */
    180180        andi    t0, v0, 0x7
     
    188188        sub     v1, v1, (4*4)           /* overhead */
    189189        move    sp, v1                  /* set sp to top of stack */
    190 4:      sw      zero, 0(v0) 
     1904:      sw      zero, 0(v0)
    191191        bltu    v0, v1, 4b              /* clear out temp stack */
    192         add     v0, 4 
    193        
    194 /*      jal     init_exc_vecs */                /* install exception handlers */ 
     192        add     v0, 4
     193
     194/*      jal     init_exc_vecs */                /* install exception handlers */
    195195/*      nop */                          /* MUST do before memory probes */
    196196
    197197                                        /* Force processor into uncached space during memory/cache probes */
    198198        la      v0, 5f
    199         li      v1, K1BASE             
     199        li      v1, K1BASE
    200200        or      v0, v1
    201201        j       v0
     
    219219
    220220        /* For MIPS 3, we need to be sure that the stack (and hence v0
    221          * here) is aligned on a double word boundary. 
     221         * here) is aligned on a double word boundary.
    222222         */
    223223        andi    t0, v0, 0x7
     
    231231/**************************************************************************
    232232**
    233 **  Permanent Stack - now know top of memory, put permanent stack there 
    234 **
    235 ***************************************************************************/ 
     233**  Permanent Stack - now know top of memory, put permanent stack there
     234**
     235***************************************************************************/
    236236
    237237        la      t2, _fbss               /* cache mode as linked */
     
    247247        subu    v1, P_STACKSIZE         /* clear requested stack size */
    248248
    249 7:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */ 
     2497:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
    250250        bltu    v1,v0,7b
    251         add     v1, 4 
     251        add     v1, 4
    252252
    253253
     
    289289        nop
    290290
    291 /* Lock first 4k of PMON into instruction cache. This includes interrupt service code which 
     291/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
    292292 we don't want to run out of slow flash device. */
    293293
    294294        la      t0,0x9fc00000
    295295        li      t1, 0x1000
    296        
     296
    297297        move    t3, t0
    298298        addu    t1, t0, t1
     
    317317/*
    318318** Clear Translation Lookaside Buffer (TLB)
    319 */ 
     319*/
    320320        jal     init_tlb                /* clear the tlb */
    321321
     
    334334        beq     zero,zero,1b
    335335        nop
    336        
     336
    337337ENDFRAME(start)
    338338
     
    352352        b       13b                             # but loop back just in-case
    353353        nop
    354        
     354
    355355ENDFRAME(_sys_exit)
    356356
  • c/src/lib/libbsp/mips/rbtx4938/startup/exception.S

    rd4b4664b refdfd48  
    138138        .set noreorder
    139139
    140 #if 0   
     140#if 0
    141141/* Activate TX4938 PIO19 signal for diagnostics */
    142142        lui     k0,0xff1f
     
    149149        sw      k1,(k0)
    150150#endif
    151        
     151
    152152        mfc0 k0,C0_CAUSE        /* Determine if an interrupt generated this exception */
    153153        nop
     
    191191        ADDIU    sp,sp,-EXCP_STACK_SIZE
    192192
    193         STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
     193        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
    194194        STREG v0, R_V0*R_SZ(sp)
    195195        STREG v1, R_V1*R_SZ(sp)
     
    208208        mflo  t0
    209209        STREG t8, R_T8*R_SZ(sp)
    210         STREG t0, R_MDLO*R_SZ(sp) 
     210        STREG t0, R_MDLO*R_SZ(sp)
    211211        STREG t9, R_T9*R_SZ(sp)
    212212        mfhi  t0
    213213        STREG gp, R_GP*R_SZ(sp)
    214         STREG t0, R_MDHI*R_SZ(sp) 
     214        STREG t0, R_MDHI*R_SZ(sp)
    215215        STREG fp, R_FP*R_SZ(sp)
    216        
     216
    217217        .set noat
    218218        STREG AT, R_AT*R_SZ(sp)
     
    288288        nop
    289289#endif
    290        
     290
    291291_ISR_Handler_cleanup:
    292292
     
    318318   *    restore stack
    319319   *  #endif
    320    * 
     320   *
    321321   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    322322   *    goto the label "exit interrupt (simple case)"
     
    352352        la      t0,__exceptionStackFrame
    353353        STREG   sp,(t0)
    354                                        
     354
    355355        jal     _Thread_Dispatch
    356356        NOP
     
    362362        NOP
    363363
    364 /* 
     364/*
    365365** turn interrupts back off while we restore context so
    366366** a badly timed interrupt won't accidentally mess things up
     
    376376        mtc0    t0, C0_SR
    377377        NOP
    378        
     378
    379379  /*
    380380   *  prepare to get out of interrupt
     
    392392        LDREG t0, R_T0*R_SZ(sp)
    393393        mtlo  t8
    394         LDREG t8, R_MDHI*R_SZ(sp)           
     394        LDREG t8, R_MDHI*R_SZ(sp)
    395395        LDREG t1, R_T1*R_SZ(sp)
    396396        mthi  t8
     
    412412        LDREG v1, R_V1*R_SZ(sp)
    413413        LDREG v0, R_V0*R_SZ(sp)
    414        
     414
    415415        LDREG k1, R_EPC*R_SZ(sp)
    416416        mtc0  k1,C0_EPC
    417        
     417
    418418        .set noat
    419419        LDREG     AT, R_AT*R_SZ(sp)
     
    429429#if 0
    430430        .global int7_isr
    431         .extern Interrupt_7_isr 
     431        .extern Interrupt_7_isr
    432432int7_isr:
    433433        /* Verify interrupt is from Timer */
     
    465465        sw      k1,(k0)
    466466#endif
    467        
     467
    468468        la  k0,_brk_esr_link    /* Jump to next exception handler in PMON exception chain */
    469469        lw  k0,(k0)
     
    493493
    494494        .extern mon_onintr
    495        
     495
    496496/* Install interrupt handler in PMON exception handling chain */
    497497
     
    523523FRAME(enable_int7,sp,0,ra)
    524524        .set noreorder
    525        
     525
    526526        la      t0,IRDM1        # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
    527527        li      t1,0x0
     
    531531        li      t1,0x200
    532532        sw      t1,(t0)
    533        
     533
    534534        la      t0,IRMSK        # Set interrupt controller mask
    535535        li      t1,0x0
     
    567567*       Diagnostic code that can be hooked to PMON interrupt handler.
    568568*       Generates pulse on PIO22 pin.
    569 *       Called from _exception code in PMON (see mips.s of PMON). 
     569*       Called from _exception code in PMON (see mips.s of PMON).
    570570*       Return address is located in k1.
    571571*/
     
    610610
    611611k1tmp:  .word   0       /* Temporary strage for K1 during interrupt service */
    612        
     612
    613613/*************************************************************
    614614*
     
    620620        .word   0
    621621        .word   rbtx4938_ISR_Handler
    622        
     622
    623623        /* Break exception service routine link */
    624624        .global _brk_esr_link
     
    628628
    629629
    630        
    631 
     630
     631
  • c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S

    rd4b4664b refdfd48  
    187187#if __mips == 1
    188188        .set    noreorder
    189         mfc0    v0,C0_TLBHI             # fetch tlb high 
     189        mfc0    v0,C0_TLBHI             # fetch tlb high
    190190        nop
    191191        and     v0,TLBHI_PIDMASK        # isolate and position
     
    220220        and     a0,TLBHI_VPNMASK        /* isolate just the vpn */
    221221        and     t0,~SR_PE               /* don't inadvertantly clear pe */
    222         mtc0    zero,C0_SR 
    223         mfc0    t1,C0_TLBHI     
     222        mtc0    zero,C0_SR
     223        mfc0    t1,C0_TLBHI
    224224        sll     a1,TLBHI_PIDSHIFT       /* possition the pid */
    225225        and     a1,TLBHI_PIDMASK
     
    272272#if __mips == 1
    273273        .set    noreorder
    274         mfc0    t0,C0_TLBHI             # fetch the current hi 
     274        mfc0    t0,C0_TLBHI             # fetch the current hi
    275275        mfc0    v0,C0_SR                # fetch the status reg.
    276276        li      t2,K0BASE&TLBHI_VPNMASK
     
    330330        mtc0    zero,C0_SR
    331331        mtc0    a1,C0_TLBHI             # set the hi entry
    332         mtc0    a2,C0_TLBLO             # set the lo entry 
     332        mtc0    a2,C0_TLBLO             # set the lo entry
    333333        mtc0    a0,C0_INX               # load the index
    334334        nop
    335335        tlbwi                           # put the hi/lo in tlb entry indexed
    336336        nop
    337         mtc0    a3,C0_TLBHI             # put back the tlb hi reg 
    338         mtc0    v0,C0_SR                # restore the status register 
     337        mtc0    a3,C0_TLBHI             # put back the tlb hi reg
     338        mtc0    v0,C0_SR                # restore the status register
    339339        j       ra
    340340        nop
     
    358358        mfc0    v0,C0_SR                # save SR and disable interrupts
    359359        mtc0    zero,C0_SR
    360         mtc0    t2,C0_PAGEMASK          # set 
     360        mtc0    t2,C0_PAGEMASK          # set
    361361        mtc0    a1,C0_TLBHI             # set VPN and TLBPID
    362362        mtc0    a2,C0_TLBLO0            # set PPN and access bits
  • c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c

    rd4b4664b refdfd48  
    119119*
    120120*******************************************************************************/
    121 
    122121
    123122
     
    258257
    259258
    260 
    261259/*
    262260 * Convert an int to hex.
     
    336334  return (buf);
    337335}
    338 
    339336
    340337
     
    534531  return mem;
    535532}
    536 
    537533
    538534
     
    653649  while  (getAck () != '+');
    654650}
    655 
    656651
    657652
     
    815810
    816811
    817 
    818812/*
    819813 * Translate the R4600 exception code into a Unix-compatible signal.
     
    923917   *optr++ = '\0';
    924918}
    925 
    926919
    927920
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    5353 * Hidden API data per task.
    5454 */
    55  
     55
    5656static BDIdx BDHead[MAX_TASKS];
    5757static BDIdx BDTail[MAX_TASKS];
     
    104104 *                      or TASK_ERR_API_ALREADY_INITIALIZED.
    105105 *
    106  * This function is only used with physical addresses. 
     106 * This function is only used with physical addresses.
    107107 *
    108108 * This function will also initialize API internal variables. The return
     
    117117         */
    118118        MBarGlobal = MBarRef;
    119        
     119
    120120        /*
    121121         * The offset is 0 if physical and virtual are the same.
    122122         */
    123123        MBarPhysOffsetGlobal = 0;
    124        
     124
    125125        /*
    126126         * IF API has not been initialized yet then...
     
    132132        return TASK_ERR_NO_ERR;
    133133}
    134  
     134
    135135/*!
    136136 * \brief       Initialize the API when virtual memory is used.
     
    159159         */
    160160        MBarGlobal = MBarRef;
    161         MBarPhysOffsetGlobal = MBarPhys - MBarRef;     
    162        
     161        MBarPhysOffsetGlobal = MBarPhys - MBarRef;
     162
    163163        /*
    164164         * If API has not been initialized yet then...
     
    170170        return TASK_ERR_NO_ERR;
    171171}
    172  
     172
    173173/*!
    174174 * \brief       \em Deprecated
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    248248#include "bestcomm_priv.h"
    249249#include "dma_image.capi.h"
    250  
     250
    251251/*!
    252252 * \brief       Initialize a single task.
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    4747
    4848/* MBAR_TASK_TABLE is the first address of task table */
    49 #ifndef MBAR_TASK_TABLE                   
     49#ifndef MBAR_TASK_TABLE
    5050#define MBAR_TASK_TABLE                     0xf0008000UL
    5151#endif
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    41410x00000700,  /* Task 0 Variable Table */
    42420x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    43 0x00000000, 
    44 0x00000000, 
     430x00000000,
     440x00000000,
    45450x00001000,  /* Task 0 context save space */
    46 0x00000000, 
     460x00000000,
    4747/* Task1(TASK_PCI_RX): Start of Entry -> 0xf0008020 */
    48480x0000023c,  /* Task 0 Descriptor Table */
     
    50500x00000780,  /* Task 0 Variable Table */
    51510x00000027, /* No FDT */
    52 0x00000000, 
    53 0x00000000, 
     520x00000000,
     530x00000000,
    54540x00001050,  /* Task 0 context save space */
    55 0x00000000, 
     550x00000000,
    5656/* Task2(TASK_FEC_TX): Start of Entry -> 0xf0008040 */
    57570x0000026c,  /* Task 0 Descriptor Table */
     
    59590x00000800,  /* Task 0 Variable Table */
    60600x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    61 0x00000000, 
    62 0x00000000, 
     610x00000000,
     620x00000000,
    63630x000010a0,  /* Task 0 context save space */
    64 0x00000000, 
     640x00000000,
    6565/* Task3(TASK_FEC_RX): Start of Entry -> 0xf0008060 */
    66660x000002fc,  /* Task 0 Descriptor Table */
     
    68680x00000880,  /* Task 0 Variable Table */
    69690x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    70 0x00000000, 
    71 0x00000000, 
     700x00000000,
     710x00000000,
    72720x000010f0,  /* Task 0 context save space */
    73 0x00000000, 
     730x00000000,
    7474/* Task4(TASK_LPC): Start of Entry -> 0xf0008080 */
    75750x0000035c,  /* Task 0 Descriptor Table */
     
    77770x00000900,  /* Task 0 Variable Table */
    78780x00000027, /* No FDT */
    79 0x00000000, 
    80 0x00000000, 
     790x00000000,
     800x00000000,
    81810x00001140,  /* Task 0 context save space */
    82 0x00000000, 
     820x00000000,
    8383/* Task5(TASK_ATA): Start of Entry -> 0xf00080a0 */
    84840x00000390,  /* Task 0 Descriptor Table */
     
    86860x00000980,  /* Task 0 Variable Table */
    87870x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    88 0x00000000, 
    89 0x00000000, 
     880x00000000,
     890x00000000,
    90900x00001190,  /* Task 0 context save space */
    91 0x00000000, 
     910x00000000,
    9292/* Task6(TASK_CRC16_DP_0): Start of Entry -> 0xf00080c0 */
    93930x000003c8,  /* Task 0 Descriptor Table */
     
    95950x00000a00,  /* Task 0 Variable Table */
    96960x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    97 0x00000000, 
    98 0x00000000, 
     970x00000000,
     980x00000000,
    99990x000011e0,  /* Task 0 context save space */
    100 0x00000000, 
     1000x00000000,
    101101/* Task7(TASK_CRC16_DP_1): Start of Entry -> 0xf00080e0 */
    1021020x00000410,  /* Task 0 Descriptor Table */
     
    1041040x00000a80,  /* Task 0 Variable Table */
    1051050x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    106 0x00000000, 
    107 0x00000000, 
     1060x00000000,
     1070x00000000,
    1081080x00001230,  /* Task 0 context save space */
    109 0x00000000, 
     1090x00000000,
    110110/* Task8(TASK_GEN_DP_0): Start of Entry -> 0xf0008100 */
    1111110x00000458,  /* Task 0 Descriptor Table */
     
    1131130x00000b00,  /* Task 0 Variable Table */
    1141140x00000027, /* No FDT */
    115 0x00000000, 
    116 0x00000000, 
     1150x00000000,
     1160x00000000,
    1171170x00001280,  /* Task 0 context save space */
    118 0x00000000, 
     1180x00000000,
    119119/* Task9(TASK_GEN_DP_1): Start of Entry -> 0xf0008120 */
    1201200x0000048c,  /* Task 0 Descriptor Table */
     
    1221220x00000b80,  /* Task 0 Variable Table */
    1231230x00000027, /* No FDT */
    124 0x00000000, 
    125 0x00000000, 
     1240x00000000,
     1250x00000000,
    1261260x000012d0,  /* Task 0 context save space */
    127 0x00000000, 
     1270x00000000,
    128128/* Task10(TASK_GEN_DP_2): Start of Entry -> 0xf0008140 */
    1291290x000004c0,  /* Task 0 Descriptor Table */
     
    1311310x00000c00,  /* Task 0 Variable Table */
    1321320x00000027, /* No FDT */
    133 0x00000000, 
    134 0x00000000, 
     1330x00000000,
     1340x00000000,
    1351350x00001320,  /* Task 0 context save space */
    136 0x00000000, 
     1360x00000000,
    137137/* Task11(TASK_GEN_DP_3): Start of Entry -> 0xf0008160 */
    1381380x000004f4,  /* Task 0 Descriptor Table */
     
    1401400x00000c80,  /* Task 0 Variable Table */
    1411410x00000027, /* No FDT */
    142 0x00000000, 
    143 0x00000000, 
     1420x00000000,
     1430x00000000,
    1441440x00001370,  /* Task 0 context save space */
    145 0x00000000, 
     1450x00000000,
    146146/* Task12(TASK_GEN_TX_BD): Start of Entry -> 0xf0008180 */
    1471470x00000528,  /* Task 0 Descriptor Table */
     
    1491490x00000d00,  /* Task 0 Variable Table */
    1501500x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    151 0x00000000, 
    152 0x00000000, 
     1510x00000000,
     1520x00000000,
    1531530x000013c0,  /* Task 0 context save space */
    154 0x00000000, 
     1540x00000000,
    155155/* Task13(TASK_GEN_RX_BD): Start of Entry -> 0xf00081a0 */
    1561560x00000564,  /* Task 0 Descriptor Table */
     
    1581580x00000d80,  /* Task 0 Variable Table */
    1591590x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    160 0x00000000, 
    161 0x00000000, 
     1600x00000000,
     1610x00000000,
    1621620x00001410,  /* Task 0 context save space */
    163 0x00000000, 
     1630x00000000,
    164164/* Task14(TASK_GEN_DP_BD_0): Start of Entry -> 0xf00081c0 */
    1651650x00000598,  /* Task 0 Descriptor Table */
     
    1671670x00000e00,  /* Task 0 Variable Table */
    1681680x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    169 0x00000000, 
    170 0x00000000, 
     1690x00000000,
     1700x00000000,
    1711710x00001460,  /* Task 0 context save space */
    172 0x00000000, 
     1720x00000000,
    173173/* Task15(TASK_GEN_DP_BD_1): Start of Entry -> 0xf00081e0 */
    1741740x000005d0,  /* Task 0 Descriptor Table */
     
    1761760x00000e80,  /* Task 0 Variable Table */
    1771770x00000f27,     /* Task 0 Function Descriptor Table & Flags */
    178 0x00000000, 
    179 0x00000000, 
     1780x00000000,
     1790x00000000,
    1801800x000014b0,  /* Task 0 context save space */
    181 0x00000000, 
     1810x00000000,
    182182
    183183/* Task0(TASK_PCI_TX): Start of TDT -> 0xf0008200 */
     
    10481048
    10491049/* Task0(TASK_PCI_TX): Start of FDT -> 0xf0008f00 */
    1050 0x00000000, 
    1051 0x00000000, 
    1052 0x00000000, 
    1053 0x00000000, 
    1054 0x00000000, 
    1055 0x00000000, 
    1056 0x00000000, 
    1057 0x00000000, 
    1058 0x00000000, 
    1059 0x00000000, 
    1060 0x00000000, 
    1061 0x00000000, 
    1062 0x00000000, 
    1063 0x00000000, 
    1064 0x00000000, 
    1065 0x00000000, 
    1066 0x00000000, 
    1067 0x00000000, 
    1068 0x00000000, 
    1069 0x00000000, 
    1070 0x00000000, 
    1071 0x00000000, 
    1072 0x00000000, 
    1073 0x00000000, 
    1074 0x00000000, 
    1075 0x00000000, 
    1076 0x00000000, 
    1077 0x00000000, 
    1078 0x00000000, 
    1079 0x00000000, 
    1080 0x00000000, 
    1081 0x00000000, 
    1082 0x00000000, 
    1083 0x00000000, 
    1084 0x00000000, 
    1085 0x00000000, 
    1086 0x00000000, 
    1087 0x00000000, 
    1088 0x00000000, 
    1089 0x00000000, 
    1090 0x00000000, 
    1091 0x00000000, 
    1092 0x00000000, 
    1093 0x00000000, 
    1094 0x00000000, 
    1095 0x00000000, 
    1096 0x00000000, 
    1097 0x00000000, 
     10500x00000000,
     10510x00000000,
     10520x00000000,
     10530x00000000,
     10540x00000000,
     10550x00000000,
     10560x00000000,
     10570x00000000,
     10580x00000000,
     10590x00000000,
     10600x00000000,
     10610x00000000,
     10620x00000000,
     10630x00000000,
     10640x00000000,
     10650x00000000,
     10660x00000000,
     10670x00000000,
     10680x00000000,
     10690x00000000,
     10700x00000000,
     10710x00000000,
     10720x00000000,
     10730x00000000,
     10740x00000000,
     10750x00000000,
     10760x00000000,
     10770x00000000,
     10780x00000000,
     10790x00000000,
     10800x00000000,
     10810x00000000,
     10820x00000000,
     10830x00000000,
     10840x00000000,
     10850x00000000,
     10860x00000000,
     10870x00000000,
     10880x00000000,
     10890x00000000,
     10900x00000000,
     10910x00000000,
     10920x00000000,
     10930x00000000,
     10940x00000000,
     10950x00000000,
     10960x00000000,
     10970x00000000,
    109810980xa0045670, /* load_acc(), EU# 3 */
    109910990x80045670, /* unload_acc(), EU# 3 */
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    2525*
    2626******************************************************************************/
    27  
     27
    2828#define MBAR_CS         0x0000
    2929#define MBAR_SDRAM      0x0100
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    3535    volatile uint8  IntVect2;   /* MBAR_SDMA + 0x11 sdPtd */
    3636    volatile uint16 PtdCntrl;   /* MBAR_SDMA + 0x12 sdPtd */
    37    
     37
    3838    volatile uint32 IntPend;    /* MBAR_SDMA + 0x14 sdPtd */
    3939    volatile uint32 IntMask;    /* MBAR_SDMA + 0x18 sdPtd */
    40    
     40
    4141    volatile uint32 TCR01;      /* MBAR_SDMA + 0x1c sdPtd */
    4242    volatile uint32 TCR23;      /* MBAR_SDMA + 0x20 sdPtd */
     
    4747    volatile uint32 TCRCD;      /* MBAR_SDMA + 0x34 sdPtd */
    4848    volatile uint32 TCREF;      /* MBAR_SDMA + 0x38 sdPtd */
    49    
     49
    5050    volatile uint8  IPR0;       /* MBAR_SDMA + 0x3c sdPtd */
    5151    volatile uint8  IPR1;       /* MBAR_SDMA + 0x3d sdPtd */
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    8282                tt->context     += sdma->taskBar;
    8383        }
    84        
     84
    8585        SramOffsetGlobal = taskTableBytes;
    8686}
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    2929
    3030/*
    31  * An extern global variable is used here for the MBAR since it must 
     31 * An extern global variable is used here for the MBAR since it must
    3232 * be passed into the API for processes that use virtual memory.
    3333 */
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    2727
    2828/*******************************************************************************
    29  * Defines to control SmartDMA and its tasks. These defines are used for the 
     29 * Defines to control SmartDMA and its tasks. These defines are used for the
    3030 * task build process to minimize disconnects at the task/driver interface.
    3131 ******************************************************************************/
     
    5050#define SDMA_DRD_MASK_LENGTH         0x03FFFFFF  /* BD_FLAGS length mask          */
    5151#define SDMA_BD_BIT_READY            30          /* Status BD ready bit           */
    52 #ifdef SAS_COMPILE 
     52#ifdef SAS_COMPILE
    5353 #define SDMA_BD_MASK_READY          constant(1<<SDMA_BD_BIT_READY)
    5454#else
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h

    rd4b4664b refdfd48  
    55*
    66* Copyright (c) 2004 Freescale Semiconductor, Inc.
    7 * 
     7*
    88* Permission is hereby granted, free of charge, to any person obtaining a
    99* copy of this software and associated documentation files (the "Software"),
     
    1212* and/or sell copies of the Software, and to permit persons to whom the
    1313* Software is furnished to do so, subject to the following conditions:
    14 * 
     14*
    1515* The above copyright notice and this permission notice shall be included
    1616* in all copies or substantial portions of the Software.
    17 * 
     17*
    1818* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1919* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    6666                                                 */
    6767        uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/
    68                                                 /*   not released yet.                              */                                 
     68                                                /*   not released yet.                              */
    6969} TaskBDIdxTable_t;
    7070
     
    7878 * Do we want to hide this from the C API since it operates on task API?
    7979 */
    80 void TaskSetup_BDTable(volatile uint32 *BasePtr, 
     80void TaskSetup_BDTable(volatile uint32 *BasePtr,
    8181                       volatile uint32 *LastPtr,
    8282                       volatile uint32 *StartPtr,
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     
    374374                                                        | (TaskSetupParams->Initiator << DRD_INIT_OFFSET);
    375375                        }
    376                        
     376
    377377                        if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0)
    378378                        {
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c

    rd4b4664b refdfd48  
    22*
    33* Copyright (c) 2004 Freescale Semiconductor, Inc.
    4 * 
     4*
    55* Permission is hereby granted, free of charge, to any person obtaining a
    66* copy of this software and associated documentation files (the "Software"),
     
    99* and/or sell copies of the Software, and to permit persons to whom the
    1010* Software is furnished to do so, subject to the following conditions:
    11 * 
     11*
    1212* The above copyright notice and this permission notice shall be included
    1313* in all copies or substantial portions of the Software.
    14 * 
     14*
    1515* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1616* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  • c/src/lib/libbsp/powerpc/gen5200/clock/clock.c

    rd4b4664b refdfd48  
    148148
    149149  gpt->status = GPT_STATUS_RESET;
    150   gpt->emsel  = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN | 
     150  gpt->emsel  = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN |
    151151                GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO;
    152152
  • c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c

    rd4b4664b refdfd48  
    7373    if (sc != RTEMS_SUCCESSFUL)
    7474        return I2C_RESOURCE_NOT_AVAILABLE;
    75     sc = i2c_transfer(bus, nmsg, msg, 
     75    sc = i2c_transfer(bus, nmsg, msg,
    7676                      i2c_transfer_sema_done_func, &sema);
    7777    if (sc != RTEMS_SUCCESSFUL)
     
    108108    rtems_status_code sc;
    109109    poll_done_flag = false;
    110     sc = i2c_transfer(bus, nmsg, msg, 
     110    sc = i2c_transfer(bus, nmsg, msg,
    111111                      i2c_transfer_poll_done_func,(void *)&poll_done_flag);
    112112    if (sc != RTEMS_SUCCESSFUL)
  • c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c

    rd4b4664b refdfd48  
    141141            mpc5200mbus_select_clock_divider(&mbus[qel->bus], i2cdrv_bus_clock_div_current);
    142142        }
    143         sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg, 
     143        sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg,
    144144                                      i2cdrv_done,qel);
    145145        if (sc != RTEMS_SUCCESSFUL)
  • c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c

    rd4b4664b refdfd48  
    196196    switch (bus->state)
    197197    {
    198      
     198
    199199        case STATE_UNINITIALIZED:
    200200          /* this should never happen. */
     
    207207                    bus->cmsg++;
    208208                    /* FALLTHRU */
    209                
     209
    210210                case EVENT_TRANSFER: /* Initiate new transfer */
    211211                    if (bus->cmsg - bus->msg >= bus->nmsg)
     
    218218                        break;
    219219                    }
    220                    
     220
    221221                    /* Initiate START or REPEATED START condition on the bus */
    222222                    if (event == EVENT_TRANSFER)
     
    228228                        mpc5200mbus_rstart(bus);
    229229                    }
    230                    
     230
    231231                    bus->byte = 0;
    232232                    mpc5200mbus_tx_mode(bus);
    233                    
     233
    234234                    /* Initiate slave address sending */
    235235                    if (bus->cmsg->flags & I2C_MSG_ADDR_10)
     
    265265                    }
    266266                    break;
    267                
     267
    268268                default:
    269269                    mpc5200mbus_machine_error(bus, event);
     
    271271            }
    272272            break;
    273        
     273
    274274        case STATE_ADDR_7:
    275275            switch (event)
     
    283283                    next_state(bus, STATE_RECEIVING);
    284284                    break;
    285                
     285
    286286                case EVENT_NACK:
    287287                    mpc5200mbus_error(bus, I2C_NO_DEVICE);
     
    295295                    mpc5200mbus_machine(bus, EVENT_NEXTMSG);
    296296                    break;
    297                    
     297
    298298                default:
    299299                    mpc5200mbus_machine_error(bus, event);
     
    302302            break;
    303303
    304         case STATE_ADDR_1_R:         
     304        case STATE_ADDR_1_R:
    305305        case STATE_ADDR_1_W:
    306306            switch (event)
     
    326326                    break;
    327327                }
    328                
     328
    329329                case EVENT_NACK:
    330330                    mpc5200mbus_error(bus, I2C_NO_DEVICE);
     
    332332                    mpc5200mbus_machine(bus, EVENT_NEXTMSG);
    333333                    break;
    334                
     334
    335335                case EVENT_ARB_LOST:
    336336                    mpc5200mbus_error(bus, I2C_ARBITRATION_LOST);
     
    338338                    mpc5200mbus_machine(bus, EVENT_NEXTMSG);
    339339                    break;
    340                
     340
    341341                default:
    342342                    mpc5200mbus_machine_error(bus, event);
     
    344344            }
    345345            break;
    346              
     346
    347347        case STATE_SENDING:
    348348            switch (event)
     
    360360                    }
    361361                    break;
    362                    
     362
    363363                case EVENT_NACK:
    364364                    if (bus->byte == 0)
     
    373373                    mpc5200mbus_machine(bus, EVENT_NEXTMSG);
    374374                    break;
    375                    
     375
    376376                case EVENT_ARB_LOST:
    377377                    mpc5200mbus_error(bus, I2C_ARBITRATION_LOST);
     
    379379                    mpc5200mbus_machine(bus, EVENT_NEXTMSG);
    380380                    break;
    381                
     381
    382382                default:
    383383                    mpc5200mbus_machine_error(bus, event);
    384384                    break;
    385                    
     385
    386386            }
    387387            break;
    388                
     388
    389389        case STATE_RECEIVING:
    390390            switch (event)
     
    445445    i2c_event event;
    446446    mpc5200mbus *bus = handle;
    447    
     447
    448448    event = mpc5200mbus_get_event(bus);
    449449    /*
     
    455455}
    456456
    457 /* 
     457/*
    458458 * mpc5200_mbus_irq_enable
    459459 *    enable irq for mbus
    460460 */
    461461void mpc5200mbus_irq_enable(const rtems_irq_connect_data* ptr)
    462 { 
     462{
    463463  int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
    464464
     
    466466}
    467467
    468 /* 
     468/*
    469469 * mpc5200_mbus_irq_disable
    470470 *    enable irq for mbus
    471471 */
    472472void mpc5200mbus_irq_disable(const rtems_irq_connect_data* ptr)
    473 { 
     473{
    474474  int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
    475475
     
    477477}
    478478
    479 /* 
     479/*
    480480 * mpc5200_mbus_isOn
    481  *    check, whether irq is enabled 
     481 *    check, whether irq is enabled
    482482 */
    483483int mpc5200mbus_irq_isOn(const rtems_irq_connect_data* ptr)
    484 { 
     484{
    485485  int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
    486486
     
    528528        int mbc;
    529529    } dividers[] ={
    530         { 20,   0x20 }, { 22,   0x21 }, { 24,   0x22 }, { 26,   0x23 }, 
     530        { 20,   0x20 }, { 22,   0x21 }, { 24,   0x22 }, { 26,   0x23 },
    531531        { 28,   0x00 }, { 30,   0x01 }, { 32,   0x25 }, { 34,   0x02 },
    532532        { 36,   0x26 }, { 40,   0x03 }, { 44,   0x04 }, { 48,   0x05 },
     
    545545    if (bus == NULL)
    546546        return RTEMS_INVALID_ADDRESS;
    547    
     547
    548548    for (i = 0, mbc = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++)
    549549    {
     
    579579    if (i2c_bus->state != STATE_UNINITIALIZED) /* Check if already initialized */
    580580        return RTEMS_RESOURCE_IN_USE;
    581            
     581
    582582    i2c_bus->state = STATE_IDLE;
    583583    i2c_bus->msg = NULL;
     
    585585    i2c_bus->nmsg = 0;
    586586    i2c_bus->byte = 0;
    587    
     587
    588588    /*
    589589     * install interrupt handler
     
    615615
    616616    rtems_interrupt_enable(level);
    617    
     617
    618618    return RTEMS_SUCCESSFUL;
    619619}
     
    640640    if (bus->state == STATE_UNINITIALIZED)
    641641        return RTEMS_NOT_CONFIGURED;
    642    
     642
    643643    bus->done = done;
    644644    bus->done_arg_ptr = done_arg_ptr;
     
    669669    if (i2c_bus->state == STATE_UNINITIALIZED)
    670670        return RTEMS_NOT_CONFIGURED;
    671    
     671
    672672    mpc5200.i2c_regs[i2c_bus->bus_idx].mcr = 0;
    673673
  • c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c

    rd4b4664b refdfd48  
    244244
    245245  pcmcia_ide_rxInterrupts++;            /* Rx int has occurred */
    246      
     246
    247247  if (pcmcia_ide_hdl_task != 0) {
    248248    rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
     
    259259
    260260  pcmcia_ide_txInterrupts++;            /* Tx int has occurred */
    261      
     261
    262262  if (pcmcia_ide_hdl_task != 0) {
    263263    rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
     
    280280  rxParam.Size.MaxBuf  = PCMCIA_IDE_RD_SECTOR_SIZE;
    281281  rxParam.Initiator    = INITIATOR_ALWAYS;
    282   rxParam.StartAddrSrc = 
     282  rxParam.StartAddrSrc =
    283283    (uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
    284284  rxParam.IncrSrc      = 0;
     
    303303  txParam.IncrDst      = 0;
    304304  txParam.SzDst        = sizeof(uint16_t);
    305  
     305
    306306  pcmcia_ide_txTaskId  = TaskSetup( TASK_GEN_DP_BD_1, &txParam );
    307307  /*
     
    314314  /*
    315315   * connect interrupt handlers
    316    */ 
     316   */
    317317  bestcomm_glue_irq_install(TASK_GEN_DP_BD_1,pcmcia_ide_xmit_dmairq_hdl,NULL);
    318318  bestcomm_glue_irq_install(TASK_GEN_DP_BD_0,pcmcia_ide_recv_dmairq_hdl,NULL);
     
    320320
    321321void mpc5200_pcmciaide_dma_blockop(bool is_write,
    322                                    int minor, 
    323                                    uint16_t block_size, 
     322                                   int minor,
     323                                   uint16_t block_size,
    324324                                   rtems_blkdev_sg_buffer *bufs,
    325                                    uint32_t *cbuf, 
     325                                   uint32_t *cbuf,
    326326                                   uint32_t *pos)
    327327
    328328{
    329329  /*
    330    * Nameing: 
     330   * Nameing:
    331331   * - a block is one unit of data on disk (multiple sectors)
    332332   * - a buffer is a contignuous chunk of data in memory
     
    361361  while ((rc == RTEMS_SUCCESSFUL) &&
    362362         (bufs_from_dma < bufs_total)) {
    363    
    364     while ((rc == RTEMS_SUCCESSFUL) && 
    365            (bufs_to_dma < bufs_total) && 
     363
     364    while ((rc == RTEMS_SUCCESSFUL) &&
     365           (bufs_to_dma < bufs_total) &&
    366366           (bds_free > 0)) {
    367367      /*
     
    370370    SDMA_CLEAR_IEVENT(&mpc5200.IntPend,(is_write
    371371                                          ? TASK_GEN_DP_BD_1
    372                                           : TASK_GEN_DP_BD_0)); 
     372                                          : TASK_GEN_DP_BD_0));
    373373      if (is_write) {
    374374        TaskBDAssign(pcmcia_ide_txTaskId ,
     
    395395    }
    396396    if (is_write) {
    397       TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE, 
     397      TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE,
    398398                 pcmcia_ide_txTaskId, TASK_INTERRUPT_DISABLE );
    399399    }
     
    408408       */
    409409      rtems_task_ident(RTEMS_SELF,0,(rtems_id *)&pcmcia_ide_hdl_task);
    410       bestcomm_glue_irq_enable((is_write 
    411                                 ? TASK_GEN_DP_BD_1 
     410      bestcomm_glue_irq_enable((is_write
     411                                ? TASK_GEN_DP_BD_1
    412412                                : TASK_GEN_DP_BD_0));
    413413
    414       rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT, 
    415                           RTEMS_WAIT | RTEMS_EVENT_ANY, 
     414      rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT,
     415                          RTEMS_WAIT | RTEMS_EVENT_ANY,
    416416                          RTEMS_NO_TIMEOUT, &events);
    417417
     
    430430
    431431    do {
    432           nxt_bd_idx = TaskBDRelease(is_write 
    433                                                      ? pcmcia_ide_txTaskId 
     432          nxt_bd_idx = TaskBDRelease(is_write
     433                                                     ? pcmcia_ide_txTaskId
    434434                                                     : pcmcia_ide_rxTaskId);
    435435      if ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
    436436          (nxt_bd_idx != TASK_ERR_BD_BUSY)) {
    437         (*cbuf)++;     
    438         (*pos) += bufs[bufs_from_dma].length;     
     437        (*cbuf)++;
     438        (*pos) += bufs[bufs_from_dma].length;
    439439        bufs_from_dma++;
    440440          }
     
    456456  uint32_t  llength = bufs[(*cbuf)].length;
    457457  bool      use_dma;
    458  
     458
    459459#if IDE_USE_STATISTICS
    460460      mpc5200_pcmciaide_read_block_call_cnt++;
     
    478478     */
    479479    while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
    480                                                  (mpc5200.ata_dctr_dasr)) & 
     480                                                 (mpc5200.ata_dctr_dasr)) &
    481481            IDE_REGISTER_STATUS_DRQ) == 0);
    482482    /*
     
    496496      cnt += 2;
    497497      (*pos) += 2;
    498      
     498
    499499      if((*pos) == llength) {
    500          
     500
    501501          (*pos) = 0;
    502502          (*cbuf)++;
    503503          lbuf = bufs[(*cbuf)].buffer;
    504504          llength = bufs[(*cbuf)].length;
    505          
     505
    506506      }
    507507    }
     
    513513      cnt += 2;
    514514      (*pos) += 2;
    515      
     515
    516516      if((*pos) == llength) {
    517517        (*pos) = 0;
    518518        (*cbuf)++;
    519519        lbuf = bufs[(*cbuf)].buffer;
    520         llength = bufs[(*cbuf)].length; 
     520        llength = bufs[(*cbuf)].length;
    521521      }
    522522    }
     
    526526      cnt += 2;
    527527      (*pos) += 2;
    528      
     528
    529529      if((*pos) == llength) {
    530530        (*pos) = 0;
    531531        (*cbuf)++;
    532532        lbuf = bufs[(*cbuf)].buffer;
    533         llength = bufs[(*cbuf)].length; 
     533        llength = bufs[(*cbuf)].length;
    534534      }
    535535    }
     
    571571     */
    572572    while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
    573                                                  (mpc5200.ata_dctr_dasr)) & 
     573                                                 (mpc5200.ata_dctr_dasr)) &
    574574            IDE_REGISTER_STATUS_DRQ) == 0);
    575575    /*
     
    596596      }
    597597      for (loop_cnt = loop_max/2;loop_cnt > 0;loop_cnt--) {
    598         *(volatile uint32_t *)(ata_reg) = 
     598        *(volatile uint32_t *)(ata_reg) =
    599599          SET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*lbuf++); /* only 16 bit data port */
    600600      }
    601601      cnt += loop_max;
    602602      (*pos) += loop_max;
    603      
     603
    604604      if((*pos) == llength) {
    605        
     605
    606606        (*pos) = 0;
    607607        (*cbuf)++;
    608608        lbuf = bufs[(*cbuf)].buffer;
    609         llength = bufs[(*cbuf)].length; 
     609        llength = bufs[(*cbuf)].length;
    610610      }
    611611    }
    612612#else
    613     while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr)) 
    614            & IDE_REGISTER_STATUS_DRQ) 
     613    while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr))
     614           & IDE_REGISTER_STATUS_DRQ)
    615615          && (cnt < block_size)) {
    616616      *(volatile uint16_t *)(ata_reg) = *lbuf++; /* only 16 bit data port */
    617617      cnt += 2;
    618618      (*pos) += 2;
    619      
     619
    620620      if((*pos) == llength) {
    621621        (*pos) = 0;
     
    658658#if IDE_USE_DMA
    659659  mpc5200_pcmciaide_dma_init(minor);
    660 #endif 
     660#endif
    661661  }
    662662
  • c/src/lib/libbsp/powerpc/gen5200/include/bsp.h

    rd4b4664b refdfd48  
    2626#include <bspopts.h>
    2727
    28 #include <libcpu/powerpc-utility.h> 
     28#include <libcpu/powerpc-utility.h>
    2929
    3030/*
     
    110110 *  Codename: IceCube
    111111 *  Compatible Boards:
    112  *     Freescape MPC5200LITE 
     112 *     Freescape MPC5200LITE
    113113 *     Embedded Planet EP5200
    114114 */
  • c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c

    rd4b4664b refdfd48  
    163163    /* Leave initialization mode */
    164164    mscan_initialization_mode_leave( m, &context);
    165    
     165
    166166    return false;
    167167  }
     
    455455    &m->idar7
    456456  };
    457  
     457
    458458  return idar [i];
    459459}
     
    477477    &m->idmr7
    478478  };
    479  
     479
    480480  return idmr [i];
    481481}
  • c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c

    rd4b4664b refdfd48  
    116116 * since a single frame often uses four or more buffer descriptors.
    117117 */
    118 #define RX_BUF_COUNT     SDMA_BD_RX_NUM 
     118#define RX_BUF_COUNT     SDMA_BD_RX_NUM
    119119#define TX_BUF_COUNT     SDMA_BD_TX_NUM
    120120#define TX_BD_PER_BUF    1
     
    273273    m->m_pkthdr.rcvif = ifp;
    274274    sc->rxMbuf[rxBdIndex] = m;
    275     bdi = TaskBDAssign( rxTaskId, 
     275    bdi = TaskBDAssign( rxTaskId,
    276276                        mtod(m, void *),
    277                         NULL, 
    278                         ETHER_MAX_LEN, 
     277                        NULL,
     278                        ETHER_MAX_LEN,
    279279                        0 );
    280280    if (bdi != rxBdIndex) {
     
    527527  mpc5200.rfifo_status &= FEC_FIFO_STAT_ERROR;
    528528  mpc5200.tfifo_status &= FEC_FIFO_STAT_ERROR;
    529  
     529
    530530  /*
    531531   * reset the FIFOs
     
    536536
    537537  mpc5200.reset_cntrl = 0x01000000;
    538  
     538
    539539  /*
    540540   * Issue a reset command to the FEC chip
    541541   */
    542542  mpc5200.ecntrl |= FEC_ECNTRL_RESET;
    543  
     543
    544544  /*
    545545   * wait at least 16 clock cycles
    546546   */
    547547  for (delay = 0;delay < 16*4;delay++) {};
    548  
     548
    549549  return true;
    550550}
     
    565565  {
    566566  int            counter = 0xffff;
    567  
     567
    568568
    569569#if defined(ETH_DEBUG)
     
    620620  mpc5200.ecntrl &= ~(FEC_ECNTRL_OE | FEC_ECNTRL_EN);
    621621
    622   /* 
     622  /*
    623623   * cleanup all buffers
    624624   */
     
    656656    sc->rxOverrun++;
    657657  }
    658   /* 
     658  /*
    659659   * fatal error ocurred?
    660660   */
     
    679679
    680680      enet_driver[0].rxInterrupts++;            /* Rx int has occurred */
    681      
     681
    682682      rtems_event_send(enet_driver[0].rxDaemonTid, INTERRUPT_EVENT);
    683683
     
    729729   * from fecExceptionHandler(TFINT).
    730730   */
    731  
     731
    732732  while ((sc->txBdActiveCount > 0) &&
    733733         (force || (bdRing[sc->txBdTail].Status == 0x0))) {
     
    742742    if(++sc->txBdTail >= sc->txBdCount) {
    743743      sc->txBdTail = 0;
    744     }   
     744    }
    745745  }
    746746}
     
    763763   * from fecExceptionHandler(TFINT).
    764764   */
    765  
     765
    766766  while (sc->txBdActiveCount > 0) {
    767767    if (sc->txMbuf[sc->txBdHead] != NULL) {
     
    775775    if(--sc->txBdHead < 0) {
    776776      sc->txBdHead = sc->txBdCount-1;
    777     }   
     777    }
    778778  }
    779779}
     
    812812    */
    813813    if((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
    814      
     814
    815815      /*
    816816       * Clear old events
    817817       */
    818818      SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_XMIT_TASK_NO);
    819      
     819
    820820      /*
    821821       * Wait for buffer descriptor to become available.
     
    831831       */
    832832      mpc5200_fec_retire_tbd(sc,false);
    833      
     833
    834834      while((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
    835835        bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO);
    836         rtems_bsdnet_event_receive(INTERRUPT_EVENT, 
    837                                    RTEMS_WAIT | RTEMS_EVENT_ANY, 
     836        rtems_bsdnet_event_receive(INTERRUPT_EVENT,
     837                                   RTEMS_WAIT | RTEMS_EVENT_ANY,
    838838                                   RTEMS_NO_TIMEOUT, &events);
    839839        mpc5200_fec_retire_tbd(sc,false);
     
    847847      struct mbuf *n;
    848848      MFREE(m, n);
    849       m = n;     
     849      m = n;
    850850      if(l != NULL) {
    851851        l->m_next = m;
     
    867867       * doing this every quarter of BDs is much more efficent
    868868       */
    869       status             = ((m->m_next == NULL) 
     869      status             = ((m->m_next == NULL)
    870870                            ? TASK_BD_TFD | TASK_BD_INT
    871871                            : 0);
     
    879879      else {
    880880        firstBd = thisBd;
    881       }     
     881      }
    882882
    883883      data_ptr = mtod(m, void *);
     
    905905        firstBd->Status     |= SDMA_BD_MASK_READY;
    906906        SDMA_TASK_ENABLE(SDMA_TCR, txTaskId);
    907         sc->txBdActiveCount += nAdded; 
     907        sc->txBdActiveCount += nAdded;
    908908      }
    909909      break;
     
    928928    */
    929929    bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO);
    930     rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT, 
    931                                RTEMS_EVENT_ANY | RTEMS_WAIT, 
    932                                RTEMS_NO_TIMEOUT, 
     930    rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
     931                               RTEMS_EVENT_ANY | RTEMS_WAIT,
     932                               RTEMS_NO_TIMEOUT,
    933933                               &events);
    934934
     
    979979   */
    980980  rxBdIndex = 0;
    981  
     981
    982982  for (;;) {
    983983    /*
     
    991991    status = bd->Status;
    992992    len    = (uint16)GET_BD_LENGTH( bd );
    993      
     993
    994994    /*
    995995     * Loop through BDs until we find an empty one. This indicates that
     
    997997     */
    998998    while( !(status & SDMA_BD_MASK_READY) ) {
    999    
     999
    10001000      /*
    10011001       * Remember the data pointer from this transfer.
     
    10031003      dptr = (void *)bd->DataPtr[0];
    10041004      m    = sc->rxMbuf[rxBdIndex];
    1005       m->m_len = m->m_pkthdr.len = (len 
    1006                                     - sizeof(uint32_t) 
     1005      m->m_len = m->m_pkthdr.len = (len
     1006                                    - sizeof(uint32_t)
    10071007                                    - sizeof(struct ether_header));
    10081008      eh = mtod(m, struct ether_header *);
    10091009      m->m_data += sizeof(struct ether_header);
    10101010      ether_input(ifp, eh, m);
    1011        
     1011
    10121012      /*
    10131013       * Done w/ the BD. Clean it.
    10141014       */
    10151015      sc->rxMbuf[rxBdIndex] = NULL;
    1016        
     1016
    10171017      /*
    10181018       * Add a new buffer to the ring.
     
    10271027      bd->Status = ( (  (uint32)SDMA_DRD_MASK_LENGTH & (uint32)size)
    10281028                     | ((uint32)SDMA_BD_MASK_READY));
    1029        
     1029
    10301030      /*
    10311031       * advance to next BD
     
    10391039      bd     = bdRing + rxBdIndex;
    10401040      status = bd->Status;
    1041       len    = (uint16)GET_BD_LENGTH( bd );   
     1041      len    = (uint16)GET_BD_LENGTH( bd );
    10421042    }
    10431043    /*
     
    10451045     */
    10461046    bestcomm_glue_irq_enable(FEC_RECV_TASK_NO);
    1047      
    1048     rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT, 
    1049                                 RTEMS_WAIT | RTEMS_EVENT_ANY, 
     1047
     1048    rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
     1049                                RTEMS_WAIT | RTEMS_EVENT_ANY,
    10501050                                RTEMS_NO_TIMEOUT, &events);
    10511051    if (events & FATAL_INT_EVENT) {
     
    10921092   * frame length=1518, MII mode for 18-wire-transceiver
    10931093   */
    1094   mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT) 
    1095                    | FEC_RCNTRL_FCE 
     1094  mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT)
     1095                   | FEC_RCNTRL_FCE
    10961096                   | FEC_RCNTRL_MII_MODE);
    1097  
     1097
    10981098  /*
    10991099   * Set FEC-Lite transmit control register (X_CNTRL)
     
    13021302  rxParam.StartAddrDst = (uint32)NULL;
    13031303  rxParam.IncrDst      = sizeof(uint32_t);
    1304   rxParam.SzDst        = sizeof(uint32_t); 
     1304  rxParam.SzDst        = sizeof(uint32_t);
    13051305  rxTaskId             = TaskSetup(TASK_FEC_RX,&rxParam );
    13061306
     
    13171317  txParam.IncrDst      = 0;
    13181318  txParam.SzDst        = sizeof(uint32_t);
    1319  
     1319
    13201320  txTaskId             = TaskSetup( TASK_FEC_TX, &txParam );
    13211321
     
    13621362       * Allocate a set of mbuf pointers
    13631363       */
    1364       sc->rxMbuf = 
     1364      sc->rxMbuf =
    13651365        malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
    1366       sc->txMbuf = 
     1366      sc->txMbuf =
    13671367        malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
    1368      
     1368
    13691369      if(!sc->rxMbuf || !sc->txMbuf)
    13701370        rtems_panic ("No memory for mbuf pointers");
     
    13731373
    13741374      mpc5200_sdma_task_setup(sc);
    1375    
     1375
    13761376      /*
    13771377       * Set up interrupts
     
    14141414       */
    14151415      TaskIntClear( rxTaskId );
    1416    
     1416
    14171417      /*
    14181418       * Enable the SmartDMA receive task.
     
    14531453  printf ("         Overrun:%-8lu", sc->rxOverrun);
    14541454  printf ("       Collision:%-8lu\n", sc->rxCollision);
    1455  
     1455
    14561456  printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
    14571457  printf ("        Deferred:%-8lu", sc->txDeferred);
     
    14651465/*
    14661466 * restart the driver, reinit the fec
    1467  * this function is responsible to reinitialize the FEC in case a fatal 
     1467 * this function is responsible to reinitialize the FEC in case a fatal
    14681468 * error has ocurred. This is needed, wen a RxFIFO Overrun or a TxFIFO underrun
    14691469 * has ocurred. In these cases, the FEC is automatically disabled, and
    14701470 * both FIFOs must be reset and the BestComm tasks must be restarted
    14711471 *
    1472  * Note: the daemon tasks will continue to run 
     1472 * Note: the daemon tasks will continue to run
    14731473 * (in fact this function will be called in the context of the rx daemon task)
    14741474 */
     
    15311531   */
    15321532  TaskIntClear( rxTaskId );
    1533  
     1533
    15341534  /*
    15351535   * Enable the SmartDMA receive/transmit task.
     
    15881588                  ? ether_addmulti(ifr, &sc->arpcom)
    15891589                  : ether_delmulti(ifr, &sc->arpcom);
    1590        
     1590
    15911591       if (error == ENETRESET) {
    15921592         if (ifp->if_flags & IFF_RUNNING)
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    rd4b4664b refdfd48  
    105105.set    BOOTSTR,                0x4C
    106106.set    BOOTSTP,                0x50
    107 .set    ADREN,                  0x54   
     107.set    ADREN,                  0x54
    108108.set    CSSR0,                  0x58            /* Critical Interrupt SSR0 (603le only) */
    109109.set    CSSR1,                  0x59            /* Critical Interrupt SSR1 (603le only) */
     
    123123/* Register offsets of MPC5x00 GPIO registers needed */
    124124.set    GPIOPCR,                0xb00
    125 .set    GPIOWE,                 0xc00   
     125.set    GPIOWE,                 0xc00
    126126.set    GPIOWOD,                0xc04
    127127.set    GPIOWDD,                0xc08
     
    157157.extern boot_card
    158158
    159 .section ".entry" 
     159.section ".entry"
    160160PUBLIC_VAR (start)
    161161start:
     
    165165        CLRBITS r30, r29, MSR_EE
    166166        mtmsr   r30                             /* Set RI/ME, Clr EE in MSR */
    167        
     167
    168168#if defined(HAS_UBOOT)
    169 /* store pointer to UBoot bd_info board info structure */       
     169/* store pointer to UBoot bd_info board info structure */
    170170        LWI     r31,bsp_uboot_board_info_ptr
    171171        stw     r3,0(r31)
     
    177177        LWI     r29, MBAR
    178178        rlwinm  r30, r29,16,16,31
    179         stw     r30, 0(r31)                     /* Set the MBAR */     
    180 #endif         
     179        stw     r30, 0(r31)                     /* Set the MBAR */
     180#endif
    181181
    182182        LWI     r31, MBAR                       /* set r31 to current MBAR */
     
    189189        or      r29,r29,r30
    190190        stw     r29, GPIOPCR(r31)
    191        
    192 /* further initialization work (common RAM/ROM startup) */   
    193         bl      TLB_init                        /* Initialize TLBs */   
    194        
    195        
     191
     192/* further initialization work (common RAM/ROM startup) */
     193        bl      TLB_init                        /* Initialize TLBs */
     194
     195
    196196        bl      FID_DCache                      /* Flush, inhibit and disable data cache */
    197        
    198        
     197
     198
    199199        bl      IDUL_ICache                     /* Inhibit, disable and unlock instruction cache */
    200        
    201        
    202         bl      FPU_init                        /* Initialize FPU */   
    203        
    204        
     200
     201
     202        bl      FPU_init                        /* Initialize FPU */
     203
     204
    205205#if defined(NEED_LOW_LEVEL_INIT)
    206         bl      SPRG_init                       /* Initialize special purpose registers */     
    207 #endif 
    208        
     206        bl      SPRG_init                       /* Initialize special purpose registers */
     207#endif
     208
    209209#if defined(NEED_LOW_LEVEL_INIT)
    210210/* detect RAM/ROM startup (common for RAM/ROM startup) */
    211211        LWI     r20, bsp_rom_start              /* set the relocation offset */
    212        
    213        
     212
     213
    214214        LWI     r30, CFG_VAL                    /* get CFG register content */
    215215        lwz     r30, CFG(r31)                   /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
    216          
    217        
     216
     217
    218218
    219219        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    220          
    221        
    222        
     220
     221
     222
    223223        TSTBITS r30, r29, ADREN_BOOT_EN
    224224        bne     skip_ROM_start                  /* If BOOT_ROM is not enabled, skip further initialization */
    225225
    226 /* do some board dependent configuration (unique for ROM startup) */   
    227         bl      SPRG_brk_init                   /* Initialize special purpose onchip breakpoint registers */   
    228        
    229    
     226/* do some board dependent configuration (unique for ROM startup) */
     227        bl      SPRG_brk_init                   /* Initialize special purpose onchip breakpoint registers */
     228
     229
    230230        LWI     r30, CSCONTROL_VAL              /* get CSCONTROL register content */
    231231        stw     r30, CSCONTROL(r31)             /* enable internal/external bus error and master for CS */
    232          
    233        
     232
     233
    234234
    235235#ifdef BRS5L
    236236        LWI     r30, CSBOOTROM_VAL
    237237        stw     r30, CSBOOTROM(r31)             /* Set CSBOOTROM */
    238        
    239        
     238
     239
    240240#endif
    241        
     241
    242242
    243243        /* FIXME: map BOOT ROM into final location with CS0 registers */
    244244        LWI     r30, bsp_rom_start
    245245        rlwinm  r30, r30,17,15,31
    246         stw     r30, CS0STR(r31)                /* Set CS0STR */       
    247                        
     246        stw     r30, CS0STR(r31)                /* Set CS0STR */
     247
    248248        LWI     r30, bsp_rom_end
    249        
     249
    250250        rlwinm  r30, r30,17,15,31
    251251        stw     r30, CS0STP(r31)                /* Set CS0STP */
    252                        
     252
    253253        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    254         SETBITS r30, r29, ADREN_CS0_EN     
     254        SETBITS r30, r29, ADREN_CS0_EN
    255255        stw     r30, ADREN(r31)                 /* enable CS0 mapping */
    256256        isync
     
    263263        mtctr   r30
    264264        bctr
    265        
    266 reloc_in_CS0:   
     265
     266reloc_in_CS0:
    267267        /* disable CSBOOT (or map it to CS0 range) */
    268268        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    269         CLRBITS r30, r29, ADREN_BOOT_EN     
     269        CLRBITS r30, r29, ADREN_BOOT_EN
    270270        stw     r30, ADREN(r31)                 /* disable BOOT mapping */
    271        
     271
    272272        /* init SDRAM */
    273273        LWI     r30, bsp_ram_start
     
    279279        ori     r30, r30, 0x1a                  /* size code: bank is 128MByte */
    280280        stw     r30, SDRAMCS1(r31)              /* Set SDRAMCS1 */
    281        
     281
    282282        bl      SDRAM_init                      /* Initialize SDRAM controller */
    283283
     
    285285        LWI     r30, 0x8000a06e
    286286        stw     r30, ARBCFG(r31)                /* Set ARBCFG */
    287        
     287
    288288        LWI     r30, 0x000000ff
    289289        stw     r30, ARBMPREN(r31)              /* Set ARBMPREN */
    290        
     290
    291291        LWI     r30, 0x00001234
    292         stw     r30, ARBMPRIO(r31)              /* Set ARBPRIO */       
     292        stw     r30, ARBMPRIO(r31)              /* Set ARBPRIO */
    293293
    294294        LWI     r30, 0x0000001e
    295         stw     r30, ARBSNOOP(r31)              /* Set ARBSNOOP */     
     295        stw     r30, ARBSNOOP(r31)              /* Set ARBSNOOP */
    296296/* copy .text section from ROM to RAM location (unique for ROM startup) */
    297297        LA      r30, bsp_section_text_start     /* get start address of text section in RAM */
    298        
    299        
     298
     299
    300300        add     r30, r20, r30                   /* get start address of text section in ROM (add reloc offset) */
    301        
    302        
     301
     302
    303303        LA      r29, bsp_section_text_start     /* get start address of text section in RAM */
    304        
     304
    305305
    306306        LA      r28, bsp_section_text_size      /* get size of RAM image */
    307                
    308        
     307
     308
    309309        bl      copy_image                      /* copy text section from ROM to RAM location */
    310        
     310
    311311
    312312/* copy .data section from ROM to RAM location (unique for ROM startup) */
    313313        LA      r30, bsp_section_data_start     /* get start address of data section in RAM */
    314        
    315                
     314
     315
    316316        add     r30, r20, r30                   /* get start address of data section in ROM (add reloc offset) */
    317        
    318                
     317
     318
    319319        LA      r29, bsp_section_data_start     /* get start address of data section in RAM */
    320        
    321        
     320
     321
    322322        LA      r28, bsp_section_data_size      /* get size of RAM image */
    323                
    324        
     323
     324
    325325        bl      copy_image                      /* copy initialized data section from ROM to RAM location */
    326        
     326
    327327
    328328        LA      r29, remap_rom                  /* get compile time address of label */
    329329        mtlr    r29
    330        
     330
    331331        blrl                                    /* now further execution RAM */
    332332
    333 remap_rom:     
     333remap_rom:
    334334/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
    335335        lwz     r30, CSBOOTROM(r31)             /* get content of CSBOOTROM */
    336          
    337        
    338                
    339         CLRBITS r30, r29, CSCONF_CE         
    340         stw     r30, CSBOOTROM(r31)             /* disable BOOT CS */ 
    341        
    342        
     336
     337
     338
     339        CLRBITS r30, r29, CSCONF_CE
     340        stw     r30, CSBOOTROM(r31)             /* disable BOOT CS */
     341
     342
    343343
    344344        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    345          
    346        
     345
     346
    347347
    348348        mr      r29, r30                        /* move content of r30 to r29 */
    349        
    350        
     349
     350
    351351        LWI     r30, ADREN_BOOT_EN              /* mask ADREN_BOOT_EN */
    352         andc    r29,r29,r30     
    353        
    354                
     352        andc    r29,r29,r30
     353
     354
    355355        LWI     r30, ADREN_CS0_EN               /* unmask ADREN_CS0_EN */
    356         or      r29,r29,r30     
    357                
    358        
     356        or      r29,r29,r30
     357
     358
    359359        stw     r29,ADREN(r31)                  /* Simultaneous enable CS0 and disable BOOT address space */
    360        
    361        
    362        
     360
     361
     362
    363363        lwz     r30, CSBOOTROM(r31)             /* get content of CSBOOTROM */
    364          
    365        
    366                
    367         SETBITS r30, r29, CSCONF_CE         
    368         stw     r30, CSBOOTROM(r31)             /* disable BOOT CS */ 
    369        
    370        
     364
     365
     366
     367        SETBITS r30, r29, CSCONF_CE
     368        stw     r30, CSBOOTROM(r31)             /* disable BOOT CS */
     369
     370
    371371
    372372skip_ROM_start:
     
    385385
    386386        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    387                        
     387
    388388        LWI     r29, ADREN_CS1_EN               /* unmask ADREN_CS1_EN */
    389         or      r30, r30,r29   
    390        
     389        or      r30, r30,r29
     390
    391391        stw     r30, ADREN(r31)                 /* enable CS1 */
    392392
     
    395395        ori     r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
    396396        LWI     r29, ONCHIP_SRAM_SIZE           /* get size of onchip SRAM */
    397        
     397
    398398        bl      clr_mem                         /* Clear onchip SRAM */
    399        
     399
    400400#endif /* defined(BRS5L) */
    401401/* clear .bss section (unique for ROM startup) */
    402402        LWI     r30, bsp_section_bss_start      /* get start address of bss section */
    403403        LWI     r29, bsp_section_bss_size       /* get size of bss section */
    404        
     404
    405405
    406406        bl      clr_mem                         /* Clear the bss section */
    407        
     407
    408408
    409409/* set stack pointer (common for RAM/ROM startup) */
    410         LA      r1, bsp_section_text_start 
     410        LA      r1, bsp_section_text_start
    411411        addi    r1, r1, -0x10                   /* Set up stack pointer = beginning of text section - 0x10 */
    412412
    413413        bl      __eabi                          /* Set up EABI and SYSV environment */
    414      
     414
    415415/* enable dynamic power management(common for RAM/ROM startup) */
    416416        bl      PPC_HID0_rd                     /* Get the content of HID0 */
    417                
    418         SETBITS r30, r29, HID0_DPM             
     417
     418        SETBITS r30, r29, HID0_DPM
    419419        bl      PPC_HID0_wr                     /* Set DPM in HID0 */
    420420
     
    423423        /* Clear cmdline */
    424424        xor r3, r3, r3
    425        
     425
    426426        bl      SYM (boot_card)                 /* Call the first C routine */
    427427
    428428#if defined(BRS5L)
    429 twiddle:                               
     429twiddle:
    430430        b       twiddle                         /* We don't expect to return from boot_card but if we do */
    431431                                                /* wait here for watchdog to kick us into hard reset     */
    432432
    433 SDRAM_init:             
     433SDRAM_init:
    434434#if defined (BRS5L)
    435435      /* set GPIO_WKUP7 pin low for 66MHz buffering */
    436436      /* or high for 133MHz registered buffering    */
    437437        LWI     r30, 0x80000000
    438        
     438
    439439        lwz     r29, GPIOWE(r31)
    440440        or      r29,r29,r30                     /* set bit 0 in r29/GPIOWE */
    441441        stw     r29,GPIOWE(r31)
    442        
     442
    443443        lwz     r29, GPIOWOD(r31)
    444444        andc    r29,r29,r30                     /* clear bit 0 in r29/GPIOWOD */
     
    448448        andc    r29,r29,r30                     /* clear bit 0 in r29/GPIOWDO */
    449449        stw     r29,GPIOWDO(r31)
    450        
     450
    451451        lwz     r29, GPIOWDD(r31)
    452452        or      r29,r29,r30                     /* set bit 0 in r29/GPIOWDD */
     
    460460#endif
    461461#if 0
    462         LWI     r30, 0xC2222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ 
    463         stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ 
     462        LWI     r30, 0xC2222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
     463        stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    464464                                                /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    465465#else
    466466        /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:       */
    467467        /* set 5 delays to their maximum to support two banks           */
    468         LWI     r30, 0xCC222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */ 
    469         stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */ 
     468        LWI     r30, 0xCC222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
     469        stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    470470                                                /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    471 #endif 
    472        
    473         LWI     r30, 0xCCC70004                 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ 
     471#endif
     472