Changeset efdb4a7 in rtems


Ignore:
Timestamp:
Nov 9, 2018, 8:37:53 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
0288536
Parents:
1e039fb3
git-author:
Sebastian Huber <sebastian.huber@…> (11/09/18 08:37:53)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/09/18 08:42:31)
Message:

bsp/beatnik: Fix warnings

Location:
bsps
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • bsps/powerpc/beatnik/include/bsp.h

    r1e039fb3 refdb4a7  
    158158#if defined(RTEMS_NETWORKING)
    159159#include <bsp/bsp_bsdnet_attach.h>
     160int rtems_em_attach(struct rtems_bsdnet_ifconfig *, int);
     161int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int);
     162int rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *, int);
    160163#endif
    161164
  • bsps/powerpc/beatnik/include/bsp/if_mve_pub.h

    r1e039fb3 refdb4a7  
    244244BSP_mve_detach(struct mveth_private *mp);
    245245
     246int
     247BSP_mve_send_buf_raw(struct mveth_private *mp, void *head_p, int h_len,
     248    void *data_p, int d_len);
     249
    246250/*
    247251 * Enqueue a mbuf chain or a raw data buffer for transmission;
  • bsps/powerpc/beatnik/net/if_em/if_em_hw.c

    r1e039fb3 refdb4a7  
    9696      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
    9797
    98 static const
    99 uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
    100     { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
    101       22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
    102       32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
    103       43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
    104       57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
    105       73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
    106       91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
    107       108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
    108 
    109 
    11098/******************************************************************************
    11199 * Set the phy type member in the hw struct.
     
    154142em_phy_init_script(struct em_hw *hw)
    155143{
    156     uint32_t ret_val;
    157144    uint16_t phy_saved_data;
    158145
     
    164151        /* Save off the current value of register 0x2F5B to be restored at
    165152         * the end of this routine. */
    166         ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
     153        em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
    167154
    168155        /* Disabled the PHY transmitter */
     
    397384    uint32_t ctrl;
    398385    uint32_t ctrl_ext;
    399     uint32_t icr;
    400386    uint32_t manc;
    401387    uint32_t led_ctrl;
     
    566552
    567553    /* Clear any pending interrupt events. */
    568     icr = E1000_READ_REG(hw, ICR);
     554    E1000_READ_REG(hw, ICR);
    569555
    570556    /* If MWI was previously enabled, reenable it. */
     
    12741260    if(hw->disable_polarity_correction == 1)
    12751261        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
    1276         ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
    1277         if(ret_val)
    1278             return ret_val;
     1262    ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
     1263    if(ret_val)
     1264        return ret_val;
    12791265
    12801266    /* Force TX_CLK in the Extended PHY Specific Control Register
     
    15081494        return ret_val;
    15091495
    1510         /* Read the MII 1000Base-T Control Register (Address 9). */
    1511         ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
    1512         if(ret_val)
    1513             return ret_val;
     1496    /* Read the MII 1000Base-T Control Register (Address 9). */
     1497    ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
     1498    if(ret_val)
     1499        return ret_val;
    15141500
    15151501    /* Need to parse both autoneg_advertised and fc and set up
     
    49194905em_clear_hw_cntrs(struct em_hw *hw)
    49204906{
    4921     volatile uint32_t temp;
    4922 
    4923     temp = E1000_READ_REG(hw, CRCERRS);
    4924     temp = E1000_READ_REG(hw, SYMERRS);
    4925     temp = E1000_READ_REG(hw, MPC);
    4926     temp = E1000_READ_REG(hw, SCC);
    4927     temp = E1000_READ_REG(hw, ECOL);
    4928     temp = E1000_READ_REG(hw, MCC);
    4929     temp = E1000_READ_REG(hw, LATECOL);
    4930     temp = E1000_READ_REG(hw, COLC);
    4931     temp = E1000_READ_REG(hw, DC);
    4932     temp = E1000_READ_REG(hw, SEC);
    4933     temp = E1000_READ_REG(hw, RLEC);
    4934     temp = E1000_READ_REG(hw, XONRXC);
    4935     temp = E1000_READ_REG(hw, XONTXC);
    4936     temp = E1000_READ_REG(hw, XOFFRXC);
    4937     temp = E1000_READ_REG(hw, XOFFTXC);
    4938     temp = E1000_READ_REG(hw, FCRUC);
    4939     temp = E1000_READ_REG(hw, PRC64);
    4940     temp = E1000_READ_REG(hw, PRC127);
    4941     temp = E1000_READ_REG(hw, PRC255);
    4942     temp = E1000_READ_REG(hw, PRC511);
    4943     temp = E1000_READ_REG(hw, PRC1023);
    4944     temp = E1000_READ_REG(hw, PRC1522);
    4945     temp = E1000_READ_REG(hw, GPRC);
    4946     temp = E1000_READ_REG(hw, BPRC);
    4947     temp = E1000_READ_REG(hw, MPRC);
    4948     temp = E1000_READ_REG(hw, GPTC);
    4949     temp = E1000_READ_REG(hw, GORCL);
    4950     temp = E1000_READ_REG(hw, GORCH);
    4951     temp = E1000_READ_REG(hw, GOTCL);
    4952     temp = E1000_READ_REG(hw, GOTCH);
    4953     temp = E1000_READ_REG(hw, RNBC);
    4954     temp = E1000_READ_REG(hw, RUC);
    4955     temp = E1000_READ_REG(hw, RFC);
    4956     temp = E1000_READ_REG(hw, ROC);
    4957     temp = E1000_READ_REG(hw, RJC);
    4958     temp = E1000_READ_REG(hw, TORL);
    4959     temp = E1000_READ_REG(hw, TORH);
    4960     temp = E1000_READ_REG(hw, TOTL);
    4961     temp = E1000_READ_REG(hw, TOTH);
    4962     temp = E1000_READ_REG(hw, TPR);
    4963     temp = E1000_READ_REG(hw, TPT);
    4964     temp = E1000_READ_REG(hw, PTC64);
    4965     temp = E1000_READ_REG(hw, PTC127);
    4966     temp = E1000_READ_REG(hw, PTC255);
    4967     temp = E1000_READ_REG(hw, PTC511);
    4968     temp = E1000_READ_REG(hw, PTC1023);
    4969     temp = E1000_READ_REG(hw, PTC1522);
    4970     temp = E1000_READ_REG(hw, MPTC);
    4971     temp = E1000_READ_REG(hw, BPTC);
     4907    E1000_READ_REG(hw, CRCERRS);
     4908    E1000_READ_REG(hw, SYMERRS);
     4909    E1000_READ_REG(hw, MPC);
     4910    E1000_READ_REG(hw, SCC);
     4911    E1000_READ_REG(hw, ECOL);
     4912    E1000_READ_REG(hw, MCC);
     4913    E1000_READ_REG(hw, LATECOL);
     4914    E1000_READ_REG(hw, COLC);
     4915    E1000_READ_REG(hw, DC);
     4916    E1000_READ_REG(hw, SEC);
     4917    E1000_READ_REG(hw, RLEC);
     4918    E1000_READ_REG(hw, XONRXC);
     4919    E1000_READ_REG(hw, XONTXC);
     4920    E1000_READ_REG(hw, XOFFRXC);
     4921    E1000_READ_REG(hw, XOFFTXC);
     4922    E1000_READ_REG(hw, FCRUC);
     4923    E1000_READ_REG(hw, PRC64);
     4924    E1000_READ_REG(hw, PRC127);
     4925    E1000_READ_REG(hw, PRC255);
     4926    E1000_READ_REG(hw, PRC511);
     4927    E1000_READ_REG(hw, PRC1023);
     4928    E1000_READ_REG(hw, PRC1522);
     4929    E1000_READ_REG(hw, GPRC);
     4930    E1000_READ_REG(hw, BPRC);
     4931    E1000_READ_REG(hw, MPRC);
     4932    E1000_READ_REG(hw, GPTC);
     4933    E1000_READ_REG(hw, GORCL);
     4934    E1000_READ_REG(hw, GORCH);
     4935    E1000_READ_REG(hw, GOTCL);
     4936    E1000_READ_REG(hw, GOTCH);
     4937    E1000_READ_REG(hw, RNBC);
     4938    E1000_READ_REG(hw, RUC);
     4939    E1000_READ_REG(hw, RFC);
     4940    E1000_READ_REG(hw, ROC);
     4941    E1000_READ_REG(hw, RJC);
     4942    E1000_READ_REG(hw, TORL);
     4943    E1000_READ_REG(hw, TORH);
     4944    E1000_READ_REG(hw, TOTL);
     4945    E1000_READ_REG(hw, TOTH);
     4946    E1000_READ_REG(hw, TPR);
     4947    E1000_READ_REG(hw, TPT);
     4948    E1000_READ_REG(hw, PTC64);
     4949    E1000_READ_REG(hw, PTC127);
     4950    E1000_READ_REG(hw, PTC255);
     4951    E1000_READ_REG(hw, PTC511);
     4952    E1000_READ_REG(hw, PTC1023);
     4953    E1000_READ_REG(hw, PTC1522);
     4954    E1000_READ_REG(hw, MPTC);
     4955    E1000_READ_REG(hw, BPTC);
    49724956
    49734957    if(hw->mac_type < em_82543) return;
    49744958
    4975     temp = E1000_READ_REG(hw, ALGNERRC);
    4976     temp = E1000_READ_REG(hw, RXERRC);
    4977     temp = E1000_READ_REG(hw, TNCRS);
    4978     temp = E1000_READ_REG(hw, CEXTERR);
    4979     temp = E1000_READ_REG(hw, TSCTC);
    4980     temp = E1000_READ_REG(hw, TSCTFC);
     4959    E1000_READ_REG(hw, ALGNERRC);
     4960    E1000_READ_REG(hw, RXERRC);
     4961    E1000_READ_REG(hw, TNCRS);
     4962    E1000_READ_REG(hw, CEXTERR);
     4963    E1000_READ_REG(hw, TSCTC);
     4964    E1000_READ_REG(hw, TSCTFC);
    49814965
    49824966    if(hw->mac_type <= em_82544) return;
    49834967
    4984     temp = E1000_READ_REG(hw, MGTPRC);
    4985     temp = E1000_READ_REG(hw, MGTPDC);
    4986     temp = E1000_READ_REG(hw, MGTPTC);
     4968    E1000_READ_REG(hw, MGTPRC);
     4969    E1000_READ_REG(hw, MGTPDC);
     4970    E1000_READ_REG(hw, MGTPTC);
    49874971
    49884972    if(hw->mac_type <= em_82547_rev_2) return;
    49894973
    4990     temp = E1000_READ_REG(hw, IAC);
    4991     temp = E1000_READ_REG(hw, ICRXOC);
    4992     temp = E1000_READ_REG(hw, ICRXPTC);
    4993     temp = E1000_READ_REG(hw, ICRXATC);
    4994     temp = E1000_READ_REG(hw, ICTXPTC);
    4995     temp = E1000_READ_REG(hw, ICTXATC);
    4996     temp = E1000_READ_REG(hw, ICTXQEC);
    4997     temp = E1000_READ_REG(hw, ICTXQMTC);
    4998     temp = E1000_READ_REG(hw, ICRXDMTC);
     4974    E1000_READ_REG(hw, IAC);
     4975    E1000_READ_REG(hw, ICRXOC);
     4976    E1000_READ_REG(hw, ICRXPTC);
     4977    E1000_READ_REG(hw, ICRXATC);
     4978    E1000_READ_REG(hw, ICTXPTC);
     4979    E1000_READ_REG(hw, ICTXATC);
     4980    E1000_READ_REG(hw, ICTXQEC);
     4981    E1000_READ_REG(hw, ICTXQMTC);
     4982    E1000_READ_REG(hw, ICRXDMTC);
    49994983
    50004984}
     
    58335817        return E1000_SUCCESS;
    58345818
    5835         ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
    5836         if(ret_val)
    5837             return ret_val;
     5819    ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
     5820    if(ret_val)
     5821        return ret_val;
    58385822
    58395823    if (!active) {
  • bsps/powerpc/beatnik/net/if_gfe/if_gfe.c

    r1e039fb3 refdb4a7  
    230230
    231231STATIC void gfe_tx_restart(void *);
     232STATIC void gfe_assign_desc(volatile struct gt_eth_desc *, struct mbuf *,
     233        uint32_t);
    232234STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio);
    233235STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t);
     
    24032405        int limit;
    24042406        int hash;
     2407#ifndef __rtems__
    24052408        int maybe_hash = 0;
     2409#endif /* __rtems__ */
    24062410
    24072411        GE_FUNC_ENTER(sc, "gfe_hash_entry_op");
     
    24752479                if (maybe_he_p == NULL && (thishe & HSH_S)) {
    24762480                        maybe_he_p = he_p;
     2481#ifndef __rtems__
    24772482                        maybe_hash = hash;
     2483#endif /* __rtems__ */
    24782484                }
    24792485
  • bsps/powerpc/beatnik/net/porting/rtemscompat.h

    r1e039fb3 refdb4a7  
    256256#endif
    257257
    258 #define _KERNEL
    259 
    260258#define device_printf(device,format,args...) printk(format,## args)
    261259
  • bsps/powerpc/shared/start/pgtbl_setup.c

    r1e039fb3 refdb4a7  
     1#include <sys/param.h>
    12#include <rtems.h>
    23#include <libcpu/mmu.h>
  • bsps/shared/net/if_dc.c

    r1e039fb3 refdb4a7  
    19141914        struct dc_type          *t;
    19151915        uint32_t                revision;
    1916         int                     error = 0, mac_offset;
     1916        int                     mac_offset;
    19171917        uint32_t                value;
    19181918
     
    19771977        if (!(command & PCI_COMMAND_IO)) {
    19781978                printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
    1979                 error = ENXIO;
    19801979                goto fail;
    19811980        }
     
    19831982        if (!(command & PCI_COMMAND_MEMORY)) {
    19841983                printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
    1985                 error = ENXIO;
    19861984                goto fail;
    19871985        }
     
    19951993        if (sc->dc_res == NULL) {
    19961994                printk("dc%d: couldn't map ports/memory\n", unit);
    1997                 error = ENXIO;
    19981995                goto fail;
    19991996        }
     
    20392036                printk("dc%d: couldn't map interrupt\n", unit);
    20402037                bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
    2041                 error = ENXIO;
    20422038                goto fail;
    20432039        }
     
    22712267                bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
    22722268#endif
    2273                 error = ENXIO;
    22742269                goto fail;
    22752270        }
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