Changeset eeec72f8 in rtems


Ignore:
Timestamp:
Aug 29, 2000, 2:47:09 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
0b456f72
Parents:
ce6411d6
Message:

2000-08-28 Joel Sherrill <joel.sherrill@…>

  • cpu.c: Spacing issues.
  • rtems/score/cpu.h: Removed warning by setting _level.
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/arm/cpu.c

    rce6411d6 reeec72f8  
    1414#include <rtems/system.h>
    1515#include <rtems.h>
    16 #include <bspio.h>
     16#include <bspIo.h>
    1717#include <rtems/score/isr.h>
    1818#include <rtems/score/wkspace.h>
     
    156156void rtems_exception_init_mngt()
    157157{
     158        ISR_Level level;
    158159     
    159160      _CPU_ISR_Disable(level);
    160       _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);    
    161       _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);    
    162       _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);    
     161      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);
     162      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);
     163      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);
    163164      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort    , NULL);
    164165      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,        _Exception_Handler_Abort    , NULL);
  • c/src/exec/score/cpu/arm/rtems/score/cpu.h

    rce6411d6 reeec72f8  
    526526#define _CPU_ISR_Disable( _level ) \
    527527  { \
     528    (_level) = 0; \
    528529    asm volatile ("MRS  r0, cpsr \n" ); \
    529530    asm volatile ("ORR  r0, r0, #0xc0 \n" ); \
  • cpukit/score/cpu/arm/cpu.c

    rce6411d6 reeec72f8  
    1414#include <rtems/system.h>
    1515#include <rtems.h>
    16 #include <bspio.h>
     16#include <bspIo.h>
    1717#include <rtems/score/isr.h>
    1818#include <rtems/score/wkspace.h>
     
    156156void rtems_exception_init_mngt()
    157157{
     158        ISR_Level level;
    158159     
    159160      _CPU_ISR_Disable(level);
    160       _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);    
    161       _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);    
    162       _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);    
     161      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);
     162      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);
     163      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);
    163164      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort    , NULL);
    164165      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,        _Exception_Handler_Abort    , NULL);
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    rce6411d6 reeec72f8  
    526526#define _CPU_ISR_Disable( _level ) \
    527527  { \
     528    (_level) = 0; \
    528529    asm volatile ("MRS  r0, cpsr \n" ); \
    529530    asm volatile ("ORR  r0, r0, #0xc0 \n" ); \
Note: See TracChangeset for help on using the changeset viewer.