Changeset eeec72f8 in rtems

Timestamp:

08/29/00 14:47:09 (23 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

0b456f72

Parents:

ce6411d6

Message:

2000-08-28 Joel Sherrill <joel.sherrill@…>

• cpu.c: Spacing issues.
• rtems/score/cpu.h: Removed warning by setting _level.

Files:

• c/src/exec/score/cpu/arm/cpu.c (modified) (2 diffs)
• c/src/exec/score/cpu/arm/rtems/score/cpu.h (modified) (1 diff)
• cpukit/score/cpu/arm/cpu.c (modified) (2 diffs)
• cpukit/score/cpu/arm/rtems/score/cpu.h (modified) (1 diff)

c/src/exec/score/cpu/arm/cpu.c

@@ -14 +14 @@
 #include <rtems/system.h>
 #include <rtems.h>
-#include <bspio.h>
+#include <bspIo.h>
 #include <rtems/score/isr.h>
 #include <rtems/score/wkspace.h>
@@ -156 +156 @@
 void rtems_exception_init_mngt()
 {
+        ISR_Level level;
       
       _CPU_ISR_Disable(level);
-      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);    
-      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);    
-      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);    
+      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL); 
+      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL); 
+      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL); 
       _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort    , NULL);
       _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,        _Exception_Handler_Abort    , NULL);

c/src/exec/score/cpu/arm/rtems/score/cpu.h

@@ -526 +526 @@
 #define _CPU_ISR_Disable( _level ) \
   { \
+    (_level) = 0; \
     asm volatile ("MRS  r0, cpsr \n" ); \
     asm volatile ("ORR  r0, r0, #0xc0 \n" ); \

cpukit/score/cpu/arm/cpu.c

@@ -14 +14 @@
 #include <rtems/system.h>
 #include <rtems.h>
-#include <bspio.h>
+#include <bspIo.h>
 #include <rtems/score/isr.h>
 #include <rtems/score/wkspace.h>
@@ -156 +156 @@
 void rtems_exception_init_mngt()
 {
+        ISR_Level level;
       
       _CPU_ISR_Disable(level);
-      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL);    
-      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL);    
-      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL);    
+      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,      _Exception_Handler_Undef_Swi, NULL); 
+      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,        _Exception_Handler_Undef_Swi, NULL); 
+      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort    , NULL); 
       _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort    , NULL);
       _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,        _Exception_Handler_Abort    , NULL);

cpukit/score/cpu/arm/rtems/score/cpu.h

@@ -526 +526 @@
 #define _CPU_ISR_Disable( _level ) \
   { \
+    (_level) = 0; \
     asm volatile ("MRS  r0, cpsr \n" ); \
     asm volatile ("ORR  r0, r0, #0xc0 \n" ); \