Changeset eebcc5b in rtems


Ignore:
Timestamp:
Sep 14, 2009, 2:50:39 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
4ea75f2
Parents:
7c411bd
Message:

2009-09-14 Sebastian Huber <sebastian.huber@…>

  • cpu_supplement/arm.t: Update.
  • cpu_supplement/preface.texi: Typo.
  • cpu_supplement/general.t: Expanded abbreviation.
Location:
doc
Files:
4 edited

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  • doc/ChangeLog

    r7c411bd reebcc5b  
     12009-09-14      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * cpu_supplement/arm.t: Update.
     4        * cpu_supplement/preface.texi: Typo.
     5        * cpu_supplement/general.t: Expanded abbreviation.
     6
     72009-09-14      Sebastian Huber <sebastian.huber@embedded-brains.de>
     8
     9        * cpu_supplement/arm.t: Update.
     10        * cpu_supplement/preface.texi: Typo.
     11        * cpu_supplement/general.t: Expanded abbreviation.
     12
    1132009-08-26      Sebastian Huber <sebastian.huber@embedded-brains.de>
    214
  • doc/cpu_supplement/arm.t

    r7c411bd reebcc5b  
    1111@chapter ARM Specific Information
    1212
    13 This chapter discusses the ARM architecture dependencies
    14 in this port of RTEMS.  The ARM family has a wide variety
    15 of implementations by a wide range of vendors.  Consequently,
    16 there are many, many CPU models within it.
     13This chapter discusses the
     14@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
     15dependencies in this port of RTEMS.  The ARM family has a wide variety of
     16implementations by a wide range of vendors.  Consequently, there are many, many
     17CPU models within it.  Currently the ARMv5 (and compatible) architecture
     18version as defined in the @code{ARMv5 Architecture Reference Manual} is supported by RTEMS.
    1719
    1820@subheading Architecture Documents
    1921
    20 For information on the ARM architecture, refer to the following documents
    21 available from Arm, Limited (@file{http//www.arm.com/}).  There does
    22 not appear to be an electronic version of a manual on the architecture
    23 in general on that site.  The following book is a good resource:
    24 
    25 @itemize @bullet
    26 @item @cite{David Seal. "ARM Architecture Reference Manual."
    27 Addison-Wesley. @b{ISBN 0-201-73719-1}. 2001.}
    28 
    29 @end itemize
    30 
    31 
    32 @c
    33 @c
    34 @c
     22For information on the ARM architecture refer to the
     23@uref{http://infocenter.arm.com,ARM Infocenter}.
    3524
    3625@section CPU Model Dependent Features
    3726
    3827This section presents the set of features which vary
    39 across ARM implementations and are of importance to RTEMS.
    40 The set of CPU model feature macros are defined in the file
    41 @code{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU
     28across ARM implementations and are of importance to RTEMS.  The set of CPU
     29model feature macros are defined in the file
     30@file{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU
    4231model flags specified on the compilation command line.
    4332
     
    4534
    4635The macro @code{CPU_MODEL_NAME} is a string which designates
    47 the architectural level of this CPU model.  The following is
    48 a list of the settings for this string based upon @code{gcc}
    49 CPU model predefines:
    50 
    51 @example
    52 __ARM_ARCH4__   "ARMv4"
    53 __ARM_ARCH4T__  "ARMv4T"
    54 __ARM_ARCH5__   "ARMv5"
    55 __ARM_ARCH5T__  "ARMv5T"
    56 __ARM_ARCH5E__  "ARMv5E"
    57 __ARM_ARCH5TE__ "ARMv5TE"
    58 @end example
     36the architectural level of this CPU model.  See in
     37@file{cpukit/score/cpu/arm/rtems/score/arm.h} for the values.
    5938
    6039@subsection Count Leading Zeroes Instruction
    6140
    62 The ARMv5 and later has the count leading zeroes (@code{clz})
    63 instruction which could be used to speed up the find first bit
    64 operation.  The use of this instruction should significantly speed up
    65 the scheduling associated with a thread blocking.
     41The ARMv5 and later has the count leading zeroes @code{clz} instruction which
     42could be used to speed up the find first bit operation.  The use of this
     43instruction should significantly speed up the scheduling associated with a
     44thread blocking.  This is currently not used.
    6645
    6746@subsection Floating Point Unit
    6847
    69 The macro ARM_HAS_FPU is set to 1 to indicate that
    70 this CPU model has a hardware floating point unit and 0
    71 otherwise.  It does not matter whether the hardware floating
    72 point support is incorporated on-chip or is an external
    73 coprocessor.
     48A floating point unit is currently not supported.
    7449
    75 @c
    76 @c
    77 @c
    7850@section Calling Conventions
    7951
    80 The ARM architecture supports a simple yet effective call and
    81 return mechanism.  A subroutine is invoked via the branch and link
    82 (@code{bl}) instruction.  This instruction saves the return address
    83 in the @code{lr} register.  Returning from a subroutine only requires
    84 that the return address be moved into the program counter (@code{pc}),
    85 possibly with an offset.  It is is important to note that the @code{bl}
    86 instruction does not automatically save or restore any registers.
    87 It is the responsibility of the high-level language compiler to define
    88 the register preservation and usage convention.
    89 
    90 @subsection Calling Mechanism
    91 
    92 All RTEMS directives are invoked using the @code{bl} instruction and
    93 return to the user application via the mechanism described above.
    94 
    95 @subsection Register Usage
    96 
    97 As discussed above, the ARM's call and return mechanism dos
    98 not automatically save any registers.  RTEMS uses the registers
    99 @code{r0}, @code{r1}, @code{r2}, and @code{r3} as scratch registers and
    100 per ARM calling convention, the @code{lr} register is altered
    101 as well.  These registers are not preserved by RTEMS directives
    102 therefore, the contents of these registers should not be assumed
    103 upon return from any RTEMS directive.
    104 
    105 @subsection Parameter Passing
    106 
    107 RTEMS assumes that ARM calling conventions are followed and that
    108 the first four arguments are placed in registers @code{r0} through
    109 @code{r3}.  If there are more arguments, than that, then they
    110 are place on the stack.
    111 
    112 @c
    113 @c
    114 @c
     52Please refer to the
     53@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf,Procedure Call Standard for the ARM Architecture}.
    11554
    11655@section Memory Model
    11756
    118 @subsection Flat Memory Model
     57A flat 32-bit memory model is supported.  The board support package must take
     58care about the MMU if necessary.
    11959
    120 Members of the ARM family newer than Version 3 support a flat 32-bit
    121 address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
    122 gigabytes).  Each address is represented by a 32-bit value and is byte
    123 addressable.  The address may be used to reference a single byte, word
    124 (2-bytes), or long word (4 bytes).  Memory accesses within this address
    125 space are performed in the endian mode that the processor is configured
    126 for.   In general, ARM processors are used in little endian mode.
    127 
    128 Some of the ARM family members such as the 920 and 720 include an MMU
    129 and thus support virtual memory and segmentation.  RTEMS does not support
    130 virtual memory or segmentation on any of the ARM family members.
    131 
    132 @c
    133 @c
    134 @c
    13560@section Interrupt Processing
    13661
    137 Although RTEMS hides many of the processor dependent
    138 details of interrupt processing, it is important to understand
    139 how the RTEMS interrupt manager is mapped onto the processor's
    140 unique architecture. Discussed in this chapter are the ARM's
    141 interrupt response and control mechanisms as they pertain to
    142 RTEMS.
    143 
    144 The ARM has 7 exception types:
     62The ARMv5 (and compatible) architecture has seven exception types:
    14563
    14664@itemize @bullet
    14765
    14866@item Reset
    149 @item Undefined instruction
    150 @item Software interrupt (SWI)
     67@item Undefined
     68@item Software Interrupt (SWI)
    15169@item Prefetch Abort
    15270@item Data Abort
     
    15674@end itemize
    15775
    158 Of these types, only IRQ and FIQ are handled through RTEMS's interrupt
    159 vectoring.
    160 
    161 @subsection Vectoring of an Interrupt Handler
    162 
    163 Unlike many other architectures, the ARM has seperate stacks for each
    164 interrupt. When the CPU receives an interrupt, it:
    165 
    166 @itemize @bullet
    167 @item switches to the exception mode corresponding to the interrupt,
    168 
    169 @item saves the Current Processor Status Register (CPSR) to the
    170 exception mode's Saved Processor Status Register (SPSR),
    171 
    172 @item masks off the IRQ and if the interrupt source was FIQ, the FIQ
    173 is masked off as well,
    174 
    175 @item saves the Program Counter (PC) to the exception mode's Link
    176 Register (LR - same as R14),
    177  
    178 @item and sets the PC to the exception's vector address.
    179 
    180 @end itemize
    181 
    182 The vectors for both IRQ and FIQ point to the _ISR_Handler function.
    183 _ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before
    184 calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so
    185 that it is safe to call C functions. Even ExecuteITHandler() can be written
    186 in C.
     76Of these types only the IRQ has explicit operating system support.  It is
     77intentional that the FIQ is not supported by the operating system.  Without
     78operating system support for the FIQ it is not necessary to disable them during
     79critical sections of the system.
    18780
    18881@subsection Interrupt Levels
    18982
    190 The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ
    191 has a higher priority than IRQ, and has its own version of register R8 - R14,
    192 however RTEMS does not take advantage of them. Both interrupts are enabled
    193 through the CPSR.
    194 
    195 The RTEMS interrupt level mapping scheme for the AEM is not a numeric level
    196 as on most RTEMS ports. It is a bit mapping that corresponds the enable
    197 bits's postions in the CPSR:
    198 
    199 @table @b
    200 @item FIQ
    201 Setting bit 6 (0 is least significant bit) disables the FIQ.
    202 
    203 @item IRQ
    204 Setting bit 7 (0 is least significant bit) disables the IRQ.
    205  
    206 @end table
     83The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as
     84on most RTEMS ports.  It is a bit mapping that corresponds the enable bit
     85postions in the Current Program Status Register (CPSR).  There are only two
     86levels: IRQ enabled and IRQ disabled.
    20787 
    20888@subsection Interrupt Stack
    20989
    210 RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory
    211 for the stacks is reserved in the linker script.
     90The board support package must initialize the interrupt stack. The memory for
     91the stacks is usually reserved in the linker script.
    21292
    213 @c
    214 @c
    215 @c
    21693@section Default Fatal Error Processing
    21794
     
    22097
    22198@itemize @bullet
    222 @item disables processor interrupts,
    223 @item places the error code in @b{r0}, and
    224 @item executes an infinite loop (@code{while(0);} to
    225 simulate a halt processor instruction.
     99@item disables operating system supported interrupts (IRQ),
     100@item places the error code in @code{r0}, and
     101@item executes an infinite loop to simulate a halt processor instruction.
    226102@end itemize
    227 
    228 @c
    229 @c
    230 @c
    231 @section Board Support Packages
    232 
    233 @subsection System Reset
    234 
    235 An RTEMS based application is initiated or re-initiated when the processor
    236 is reset.  When the processor is reset, the processor performs the
    237 following actions:
    238 
    239 @itemize @bullet
    240 @item TBD
    241 
    242 @end itemize
    243 
    244 @subsection Processor Initialization
    245 
    246 TBD
  • doc/cpu_supplement/general.t

    r7c411bd reebcc5b  
    3939such as the SPARC or PowerPC are based on an architectural specification
    4040which is independent or any particular CPU model or implementation.
    41 Older families such as the M68xxx and the iX86 evolved as the manufacturer
    42 strived to produce higher performance processor models which maintained
    43 binary compatibility with older models.
     41Older families such as the Motorola 68000 and the Intel x86 evolved as the
     42manufacturer strived to produce higher performance processor models which
     43maintained binary compatibility with older models.
    4444
    4545RTEMS takes advantage of the similarity of the various models within a
  • doc/cpu_supplement/preface.texi

    r7c411bd reebcc5b  
    3434there are many ARM CPU models from numerous semiconductor
    3535vendors and a wide variety of peripherals.  But at the
    36 ISA level, they share a common compaability.
     36ISA level, they share a common compatibility.
    3737
    3838RTEMS depends upon this core similarity across the CPU models
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