Changeset ee4f57d in rtems
- Timestamp:
- 03/23/04 09:59:52 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- e7ceef91
- Parents:
- 83c5fc1
- Location:
- c/src
- Files:
-
- 51 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/ChangeLog
r83c5fc1 ree4f57d 1 2004-03-23 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * libchip/ide/ata.c, libchip/ide/ata_internal.h, 4 libchip/ide/ide_controller.c, libchip/ide/ide_ctrl_cfg.h, 5 libchip/ide/ide_ctrl_io.h, libchip/network/cs8900.c, 6 libchip/network/dec21140.c, libchip/network/elnk.c, 7 libchip/network/if_fxp.c, libchip/network/open_eth.c, 8 libchip/network/open_eth.h, libchip/network/sonic.c, 9 libchip/network/sonic.h, libchip/rtc/icm7170.c, libchip/rtc/icm7170.h, 10 libchip/rtc/icm7170_reg.c, libchip/rtc/icm7170_reg2.c, 11 libchip/rtc/icm7170_reg4.c, libchip/rtc/icm7170_reg8.c, 12 libchip/rtc/m48t08.c, libchip/rtc/m48t08.h, libchip/rtc/m48t08_reg.c, 13 libchip/rtc/m48t08_reg2.c, libchip/rtc/m48t08_reg4.c, 14 libchip/rtc/m48t08_reg8.c, libchip/rtc/rtc.h, libchip/serial/mc68681.c, 15 libchip/serial/mc68681.h, libchip/serial/mc68681_reg.c, 16 libchip/serial/mc68681_reg2.c, libchip/serial/mc68681_reg4.c, 17 libchip/serial/mc68681_reg8.c, libchip/serial/ns16550.c, 18 libchip/serial/ns16550_p.h, libchip/serial/serial.h, 19 libchip/serial/z85c30.c, libchip/serial/z85c30.h, 20 libchip/serial/z85c30_p.h, libchip/serial/z85c30_reg.c, 21 libchip/shmdr/addlq.c, libchip/shmdr/cnvpkt.c, libchip/shmdr/dump.c, 22 libchip/shmdr/fatal.c, libchip/shmdr/getlq.c, libchip/shmdr/init.c, 23 libchip/shmdr/initlq.c, libchip/shmdr/intr.c, libchip/shmdr/poll.c, 24 libchip/shmdr/send.c, libchip/shmdr/shm_driver.h: Convert to using c99 25 fixed-size types. 26 1 27 2004-03-14 Chris Johns <chrisj@rtems.org> 2 28 3 * cs8900.c.bsp, cs8900.h.bsp: Updated the BSP example code. 4 5 * cs8900.c, cs8900.h: 6 Changes made to support the DIMMPC. This is a pc396 target with IO port 7 support. 8 Minor formating clean up. 9 Add documentation to the header file. 10 11 * README.cs8900: 12 The CS8900 driver is documented in the cs8900.h header file. 29 * libchip/network/cs8900.c.bsp, libchip/network/cs8900.h.bsp: Updated 30 the BSP example code. 31 * libchip/network/cs8900.c, libchip/network/cs8900.h: Changes made to 32 support the DIMMPC. This is a pc386 target with IO port support. Minor 33 formating clean up. Add documentation to the header file. 34 * libchip/network/README.cs8900: The CS8900 driver is documented in the 35 cs8900.h header file. 13 36 14 37 2004-03-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> -
c/src/libchip/ide/ata.c
r83c5fc1 ree4f57d 135 135 */ 136 136 rtems_device_minor_number ctrl_minor; 137 u nsigned8dev;137 uint8_t dev; 138 138 139 139 rel_minor = (rtems_filesystem_dev_minor_t(device)) / … … 218 218 if (ATA_DEV_INFO(ctrl_minor, dev).lba_avaible) 219 219 { 220 areq->regs.regs[IDE_REGISTER_LBA0] = (u nsigned8)req->start;221 areq->regs.regs[IDE_REGISTER_LBA1] = (u nsigned8)(req->start >> 8);222 areq->regs.regs[IDE_REGISTER_LBA2] = (u nsigned8)(req->start >> 16);223 areq->regs.regs[IDE_REGISTER_LBA3] |= (u nsigned8) (req->start >> 24);220 areq->regs.regs[IDE_REGISTER_LBA0] = (uint8_t )req->start; 221 areq->regs.regs[IDE_REGISTER_LBA1] = (uint8_t )(req->start >> 8); 222 areq->regs.regs[IDE_REGISTER_LBA2] = (uint8_t )(req->start >> 16); 223 areq->regs.regs[IDE_REGISTER_LBA3] |= (uint8_t ) (req->start >> 24); 224 224 areq->regs.regs[IDE_REGISTER_LBA3] |= IDE_REGISTER_LBA3_L; 225 225 } 226 226 else 227 227 { 228 u nsigned32count = req->start;228 uint32_t count = req->start; 229 229 230 230 areq->regs.regs[IDE_REGISTER_SECTOR_NUMBER] = … … 238 238 /* now count = number of cylinders */ 239 239 count %= ATA_DEV_INFO(ctrl_minor, dev).cylinders; 240 areq->regs.regs[IDE_REGISTER_CYLINDER_LOW] = (u nsigned8)count;241 areq->regs.regs[IDE_REGISTER_CYLINDER_HIGH] = (u nsigned8)(count >> 8);240 areq->regs.regs[IDE_REGISTER_CYLINDER_LOW] = (uint8_t )count; 241 areq->regs.regs[IDE_REGISTER_CYLINDER_HIGH] = (uint8_t )(count >> 8); 242 242 areq->regs.regs[IDE_REGISTER_DEVICE_HEAD] &= 243 243 ~IDE_REGISTER_DEVICE_HEAD_L; … … 275 275 */ 276 276 rtems_device_minor_number ctrl_minor; 277 u nsigned8dev;277 uint8_t dev; 278 278 ata_queue_msg_t msg; 279 279 … … 313 313 areq->regs.to_write |= 314 314 ATA_REGISTERS_VALUE(IDE_REGISTER_SECTOR_COUNT); 315 areq->regs.regs[IDE_REGISTER_SECTOR_COUNT] = *(u nsigned8*)argp;315 areq->regs.regs[IDE_REGISTER_SECTOR_COUNT] = *(uint8_t *)argp; 316 316 break; 317 317 … … 357 357 case ATAIO_SET_MULTIPLE_MODE: 358 358 ATA_DEV_INFO(ctrl_minor, dev).current_multiple = 359 *(u nsigned8*)argp;359 *(uint8_t *)argp; 360 360 break; 361 361 … … 392 392 { 393 393 ata_req_t *areq; 394 u nsigned16byte; /* emphasize that only 8 low bits is meaningful */394 uint16_t byte; /* emphasize that only 8 low bits is meaningful */ 395 395 ata_queue_msg_t msg; 396 u nsigned8i, dev;397 u nsigned16val;398 u nsigned16data_bs; /* the number of 512-bytes sectors in one396 uint8_t i, dev; 397 uint16_t val; 398 uint16_t data_bs; /* the number of 512-bytes sectors in one 399 399 * data block 400 400 */ … … 430 430 for (i=0; i< ATA_MAX_CMD_REG_OFFSET; i++) 431 431 { 432 u nsigned32reg = (1 << i);432 uint32_t reg = (1 << i); 433 433 if (areq->regs.to_write & reg) 434 434 ide_controller_write_register(ctrl_minor, i, areq->regs.regs[i]); … … 555 555 if (Chain_Has_only_one_node(&ata_ide_ctrls[ctrl_minor].reqs)) 556 556 { 557 u nsigned16val;557 uint16_t val; 558 558 ata_queue_msg_t msg; 559 559 … … 590 590 Chain_Node *the_node = ((Chain_Control *)(&ata_int_vec[vec]))->first; 591 591 ata_queue_msg_t msg; 592 u nsigned16byte; /* emphasize that only 8 low bits is meaningful */592 uint16_t byte; /* emphasize that only 8 low bits is meaningful */ 593 593 594 594 for ( ; !Chain_Is_tail(&ata_int_vec[vec], the_node) ; ) … … 622 622 ata_pio_in_protocol(rtems_device_minor_number ctrl_minor, ata_req_t *areq) 623 623 { 624 u nsigned16bs, val;625 u nsigned8dev;626 u nsigned32min_val;624 uint16_t bs, val; 625 uint8_t dev; 626 uint32_t min_val; 627 627 ata_queue_msg_t msg; 628 628 … … 665 665 ata_pio_out_protocol(rtems_device_minor_number ctrl_minor, ata_req_t *areq) 666 666 { 667 u nsigned16bs, val;668 u nsigned8dev;669 u nsigned32min_val;667 uint16_t bs, val; 668 uint8_t dev; 669 uint32_t min_val; 670 670 ata_queue_msg_t msg; 671 671 … … 716 716 { 717 717 ata_queue_msg_t msg; 718 rtems_unsigned32size;718 uint32_t size; 719 719 ata_req_t *areq; 720 720 rtems_device_minor_number ctrl_minor; 721 u nsigned16val;722 u nsigned16val1;721 uint16_t val; 722 uint16_t val1; 723 723 rtems_status_code rc; 724 724 ISR_Level level; … … 898 898 void *args) 899 899 { 900 u nsigned32ctrl_minor;900 uint32_t ctrl_minor; 901 901 rtems_status_code status; 902 902 ata_req_t areq; 903 903 blkdev_request1 breq; 904 u nsigned8i, dev = 0;905 u nsigned16*buffer;906 u nsigned16ec;904 uint8_t i, dev = 0; 905 uint16_t *buffer; 906 uint16_t ec; 907 907 char name[ATA_MAX_NAME_LENGTH]; 908 908 dev_t device; … … 963 963 } 964 964 965 buffer = (u nsigned16*)malloc(ATA_SECTOR_SIZE);965 buffer = (uint16_t *)malloc(ATA_SECTOR_SIZE); 966 966 if (buffer == NULL) 967 967 { … … 1148 1148 (CF_LE_W(buffer[ATA_IDENT_WORD_CAPABILITIES]) >> 9) & 0x1; 1149 1149 ATA_DEV_INFO(ctrl_minor, dev).max_multiple = 1150 (u nsigned8) (CF_LE_W(buffer[ATA_IDENT_WORD_RW_MULT]));1150 (uint8_t ) (CF_LE_W(buffer[ATA_IDENT_WORD_RW_MULT])); 1151 1151 ATA_DEV_INFO(ctrl_minor, dev).current_multiple = 1152 1152 (CF_LE_W(buffer[ATA_IDENT_WORD_MULT_SECS]) & 0x100) ? 1153 (u nsigned8)(CF_LE_W(buffer[ATA_IDENT_WORD_MULT_SECS])) :1153 (uint8_t )(CF_LE_W(buffer[ATA_IDENT_WORD_MULT_SECS])) : 1154 1154 0; 1155 1155 … … 1237 1237 ata_req_t *areq) 1238 1238 { 1239 u nsigned16byte;/* emphasize that only 8 low bits is meaningful */1240 u nsigned8i, dev;1241 u nsigned16val, val1;1242 u nsigned16data_bs; /* the number of 512 bytes sectors into one1239 uint16_t byte;/* emphasize that only 8 low bits is meaningful */ 1240 uint8_t i, dev; 1241 uint16_t val, val1; 1242 uint16_t data_bs; /* the number of 512 bytes sectors into one 1243 1243 * data block 1244 1244 */ … … 1261 1261 for (i=0; i< ATA_MAX_CMD_REG_OFFSET; i++) 1262 1262 { 1263 u nsigned32reg = (1 << i);1263 uint32_t reg = (1 << i); 1264 1264 if (areq->regs.to_write & reg) 1265 1265 ide_controller_write_register(ctrl_minor, i, -
c/src/libchip/ide/ata_internal.h
r83c5fc1 ree4f57d 211 211 /* Command block registers */ 212 212 typedef struct ata_registers_s { 213 u nsigned16regs[8]; /* command block registers */214 u nsigned16to_read; /* mask: which ata registers should be read */215 u nsigned16to_write; /* mask: which ata registers should be written */213 uint16_t regs[8]; /* command block registers */ 214 uint16_t to_read; /* mask: which ata registers should be read */ 215 uint16_t to_write; /* mask: which ata registers should be written */ 216 216 } ata_registers_t; 217 217 … … 221 221 char type; /* request type */ 222 222 ata_registers_t regs; /* ATA command */ 223 rtems_unsigned32cnt; /* Number of sectors to be exchanged */224 rtems_unsigned32cbuf; /* number of current buffer from breq in use */225 rtems_unsigned32pos; /* current position in 'cbuf' */223 uint32_t cnt; /* Number of sectors to be exchanged */ 224 uint32_t cbuf; /* number of current buffer from breq in use */ 225 uint32_t pos; /* current position in 'cbuf' */ 226 226 blkdev_request *breq; /* blkdev_request which corresponds to the 227 227 * ata request … … 296 296 */ 297 297 typedef struct ata_dev_s { 298 signed8present; /* 1 -- present, 0 -- not present, */298 int8_t present; /* 1 -- present, 0 -- not present, */ 299 299 /* -1 -- non-initialized */ 300 u nsigned16cylinders;301 u nsigned16heads;302 u nsigned16sectors;303 u nsigned32lba_sectors; /* for small disk */300 uint16_t cylinders; 301 uint16_t heads; 302 uint16_t sectors; 303 uint32_t lba_sectors; /* for small disk */ 304 304 /* == cylinders * heads * sectors */ 305 305 306 u nsigned8lba_avaible; /* 0 - CHS mode, 1 - LBA mode */307 308 u nsigned8max_multiple; /* 0 if READ/WRITE MULTIPLE is unsupported */309 u nsigned8current_multiple;310 311 u nsigned8modes_avaible; /* OR of values for this modes */312 u nsigned8mode_active;306 uint8_t lba_avaible; /* 0 - CHS mode, 1 - LBA mode */ 307 308 uint8_t max_multiple; /* 0 if READ/WRITE MULTIPLE is unsupported */ 309 uint8_t current_multiple; 310 311 uint8_t modes_avaible; /* OR of values for this modes */ 312 uint8_t mode_active; 313 313 } ata_dev_t; 314 314 -
c/src/libchip/ide/ide_controller.c
r83c5fc1 ree4f57d 85 85 void 86 86 ide_controller_read_data_block(rtems_device_minor_number minor, 87 u nsigned16block_size,87 uint16_t block_size, 88 88 blkdev_sg_buffer *bufs, 89 rtems_unsigned32*cbuf,90 rtems_unsigned32*pos)89 uint32_t *cbuf, 90 uint32_t *pos) 91 91 { 92 92 IDE_Controller_Table[minor].fns->ctrl_read_block(minor, block_size, bufs, … … 110 110 void 111 111 ide_controller_write_data_block(rtems_device_minor_number minor, 112 u nsigned16block_size,112 uint16_t block_size, 113 113 blkdev_sg_buffer *bufs, 114 rtems_unsigned32*cbuf,115 rtems_unsigned32*pos)114 uint32_t *cbuf, 115 uint32_t *pos) 116 116 117 117 { … … 135 135 ide_controller_read_register(rtems_device_minor_number minor, 136 136 int reg, 137 u nsigned16*value)137 uint16_t *value) 138 138 { 139 139 IDE_Controller_Table[minor].fns->ctrl_reg_read(minor, reg, value); … … 154 154 void 155 155 ide_controller_write_register(rtems_device_minor_number minor, int reg, 156 u nsigned16value)156 uint16_t value) 157 157 { 158 158 IDE_Controller_Table[minor].fns->ctrl_reg_write(minor, reg, value); … … 172 172 */ 173 173 rtems_status_code 174 ide_controller_config_io_speed(int minor, u nsigned8modes_avaible)174 ide_controller_config_io_speed(int minor, uint8_t modes_avaible) 175 175 { 176 176 return IDE_Controller_Table[minor].fns->ctrl_config_io_speed( -
c/src/libchip/ide/ide_ctrl_cfg.h
r83c5fc1 ree4f57d 39 39 boolean (*ctrl_probe)(int minor); /* probe routine */ 40 40 void (*ctrl_initialize)(int minor); 41 int (*ctrl_control)(int minor, u nsigned32command,41 int (*ctrl_control)(int minor, uint32_t command, 42 42 void *arg); 43 43 /* … … 46 46 * ide_controller_write_register) 47 47 */ 48 void (*ctrl_reg_read)(int minor, int regist, u nsigned16*value);49 void (*ctrl_reg_write)(int minor, int regist, u nsigned16value);48 void (*ctrl_reg_read)(int minor, int regist, uint16_t *value); 49 void (*ctrl_reg_write)(int minor, int regist, uint16_t value); 50 50 51 51 /* … … 53 53 * functions calls 54 54 */ 55 void (*ctrl_read_block)(int minor, u nsigned16block_size,56 blkdev_sg_buffer *bufs, rtems_unsigned32*cbuf,57 rtems_unsigned32*pos);58 void (*ctrl_write_block)(int minor, u nsigned16block_size,59 blkdev_sg_buffer *bufs, rtems_unsigned32*cbuf,60 rtems_unsigned32*pos);55 void (*ctrl_read_block)(int minor, uint16_t block_size, 56 blkdev_sg_buffer *bufs, uint32_t *cbuf, 57 uint32_t *pos); 58 void (*ctrl_write_block)(int minor, uint16_t block_size, 59 blkdev_sg_buffer *bufs, uint32_t *cbuf, 60 uint32_t *pos); 61 61 62 62 rtems_status_code (*ctrl_config_io_speed)(int minor, 63 u nsigned8modes_available);63 uint8_t modes_available); 64 64 } ide_ctrl_fns_t; 65 65 … … 73 73 ide_ctrl_fns_t *fns; /* pointer to the set of driver routines */ 74 74 boolean (*probe)(int minor); /* general probe routine */ 75 u nsigned8status; /* initialized/non initialized. Should be set75 uint8_t status; /* initialized/non initialized. Should be set 76 76 * to zero by static initialization 77 77 */ 78 u nsigned32port1; /* port number for the port of the device */78 uint32_t port1; /* port number for the port of the device */ 79 79 rtems_boolean int_driven; /* interrupt/poll driven */ 80 80 rtems_vector_number int_vec; /* the interrupt vector of the device */ -
c/src/libchip/ide/ide_ctrl_io.h
r83c5fc1 ree4f57d 104 104 void 105 105 ide_controller_read_data_block(rtems_device_minor_number minor, 106 u nsigned16block_size,106 uint16_t block_size, 107 107 blkdev_sg_buffer *bufs, 108 rtems_unsigned32*cbuf,109 rtems_unsigned32*pos);108 uint32_t *cbuf, 109 uint32_t *pos); 110 110 111 111 /* … … 125 125 void 126 126 ide_controller_write_data_block(rtems_device_minor_number minor, 127 u nsigned16block_size,127 uint16_t block_size, 128 128 blkdev_sg_buffer *bufs, 129 rtems_unsigned32*cbuf,130 rtems_unsigned32*pos);129 uint32_t *cbuf, 130 uint32_t *pos); 131 131 132 132 /* … … 145 145 ide_controller_read_register(rtems_device_minor_number minor, 146 146 int reg, 147 u nsigned16*value);147 uint16_t *value); 148 148 149 149 /* … … 161 161 void 162 162 ide_controller_write_register(rtems_device_minor_number minor, 163 int reg, u nsigned16value);163 int reg, uint16_t value); 164 164 165 165 /* … … 176 176 */ 177 177 rtems_status_code 178 ide_controller_config_io_speed(int minor, u nsigned8modes_avaible);178 ide_controller_config_io_speed(int minor, uint8_t modes_avaible); 179 179 180 180 #ifdef __cplusplus -
c/src/libchip/network/cs8900.c
r83c5fc1 ree4f57d 199 199 */ 200 200 201 rtems_unsigned32rtems_read_timer ();201 uint32_t rtems_read_timer (); 202 202 203 203 static inline void -
c/src/libchip/network/dec21140.c
r83c5fc1 ree4f57d 171 171 struct MD { 172 172 /* used by hardware */ 173 volatile u nsigned32status;174 volatile u nsigned32counts;175 volatile u nsigned32buf1, buf2;173 volatile uint32_t status; 174 volatile uint32_t counts; 175 volatile uint32_t buf1, buf2; 176 176 /* used by software */ 177 177 volatile struct mbuf *m; … … 244 244 #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE 245 245 246 inline void st_le32(volatile u nsigned32 *addr, unsigned32value)246 inline void st_le32(volatile uint32_t *addr, uint32_t value) 247 247 { 248 248 *(addr)=value ; 249 249 } 250 250 251 inline u nsigned32 ld_le32(volatile unsigned32*addr)251 inline uint32_t ld_le32(volatile uint32_t *addr) 252 252 { 253 253 return(*addr); … … 426 426 dec21140Enet_interrupt_handler ( struct dec21140_softc *sc ) 427 427 { 428 volatile u nsigned32*tbase;429 u nsigned32status;430 431 tbase = (u nsigned32*)(sc->base);428 volatile uint32_t *tbase; 429 uint32_t status; 430 431 tbase = (uint32_t *)(sc->base); 432 432 433 433 /* … … 1191 1191 pci_write_config_word(pbus, pdev, pfun, 1192 1192 PCI_COMMAND, 1193 (u nsigned16) ( PCI_COMMAND_MEMORY |1193 (uint16_t ) ( PCI_COMMAND_MEMORY | 1194 1194 PCI_COMMAND_MASTER | 1195 1195 PCI_COMMAND_INVALIDATE | -
c/src/libchip/network/elnk.c
r83c5fc1 ree4f57d 205 205 #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE 206 206 207 inline void st_le32(volatile u nsigned32 *addr, unsigned32value)207 inline void st_le32(volatile uint32_t *addr, uint32_t value) 208 208 { 209 209 *(addr)=value ; 210 210 } 211 211 212 inline u nsigned32 ld_le32(volatile unsigned32*addr)212 inline uint32_t ld_le32(volatile uint32_t *addr) 213 213 { 214 214 return(*addr); … … 880 880 { 881 881 /* used by hardware */ 882 volatile u nsigned32next;883 volatile u nsigned32status;884 volatile u nsigned32addr;885 volatile u nsigned32length;882 volatile uint32_t next; 883 volatile uint32_t status; 884 volatile uint32_t addr; 885 volatile uint32_t length; 886 886 /* used by software */ 887 887 struct mbuf *mbuf; /* scratch variable used in the tx ring */ … … 901 901 struct tfrag 902 902 { 903 volatile u nsigned32addr;904 volatile u nsigned32length;903 volatile uint32_t addr; 904 volatile uint32_t length; 905 905 } __attribute__ ((packed)); 906 906 … … 908 908 { 909 909 /* used by hardware */ 910 volatile u nsigned32next;911 volatile u nsigned32status;910 volatile uint32_t next; 911 volatile uint32_t status; 912 912 struct tfrag txfrags[NUM_FRAGS]; 913 913 /* used by software */ … … 941 941 942 942 rtems_id stat_timer_id; 943 u nsigned32stats_update_ticks;943 uint32_t stats_update_ticks; 944 944 945 945 struct xl_stats xl_stats; … … 2048 2048 #if 0 2049 2049 { 2050 u nsigned16intstatus, intenable, indenable;2050 uint16_t intstatus, intenable, indenable; 2051 2051 2052 2052 intstatus = CSR_READ_2(sc, XL_STATUS ); … … 2133 2133 for(i=0 ; i<sc->numRxbuffers; i++) 2134 2134 { 2135 if( ((u nsigned32)&sc->rx_ring[i] & 0x7) )2135 if( ((uint32_t )&sc->rx_ring[i] & 0x7) ) 2136 2136 { 2137 2137 rtems_panic ("etherlink : unit elnk%d rx ring entry %d not aligned to 8 bytes\n", sc->xl_unit, i ); … … 2152 2152 2153 2153 st_le32( &sc->rx_ring[i].status, 0); 2154 st_le32( &sc->rx_ring[i].next, (u nsigned32)phys_to_bus( nxtmd ));2155 st_le32( &sc->rx_ring[i].addr, (u nsigned32)phys_to_bus( mtod(m, void *) ));2154 st_le32( &sc->rx_ring[i].next, (uint32_t )phys_to_bus( nxtmd )); 2155 st_le32( &sc->rx_ring[i].addr, (uint32_t )phys_to_bus( mtod(m, void *) )); 2156 2156 st_le32( &sc->rx_ring[i].length, XL_LAST_FRAG | XL_PACKET_SIZE ); 2157 2157 } … … 2182 2182 for(i=0 ; i<sc->numTxbuffers; i++) 2183 2183 { 2184 if( ((u nsigned32)&sc->tx_ring[i] & 0x7) )2184 if( ((uint32_t )&sc->tx_ring[i] & 0x7) ) 2185 2185 { 2186 2186 rtems_panic ("etherlink : unit elnk%d tx ring entry %d not aligned to 8 bytes\n", sc->xl_unit, i ); … … 2328 2328 rmd->mbuf = m; 2329 2329 st_le32( &rmd->status, 0 ); 2330 st_le32( &rmd->addr, (u nsigned32)phys_to_bus(mtod(m, void *)) );2330 st_le32( &rmd->addr, (uint32_t )phys_to_bus(mtod(m, void *)) ); 2331 2331 } 2332 2332 else … … 2416 2416 { 2417 2417 struct TXMD *chainhead, *chaintail; 2418 u nsigned32esize;2418 uint32_t esize; 2419 2419 2420 2420 if( rtems_message_queue_receive( chainRecoveryQueue, &chainhead, &esize, … … 2476 2476 { 2477 2477 st_le32( &nextmd->txfrags[i].length, ((m->m_next)?0:XL_LAST_FRAG) | ( m->m_len & XL_TXSTAT_LENMASK) ); 2478 st_le32( &nextmd->txfrags[i].addr, (u nsigned32)phys_to_bus( m->m_data ) );2478 st_le32( &nextmd->txfrags[i].addr, (uint32_t )phys_to_bus( m->m_data ) ); 2479 2479 if ((m = m->m_next) == NULL) 2480 2480 break; … … 2492 2492 char *pkt = bus_to_phys( ld_le32( &nextmd->txfrags[i].addr )), *delim; 2493 2493 int i; 2494 printk("unit %d queued pkt (%08x) ", sc->xl_unit, (u nsigned32)pkt );2494 printk("unit %d queued pkt (%08x) ", sc->xl_unit, (uint32_t )pkt ); 2495 2495 for(delim="", i=0; i < sizeof(struct ether_header); i++, delim=":") 2496 2496 printk("%s%02x", delim, (char) pkt[i] ); … … 2523 2523 { 2524 2524 /* hook this packet to the previous one */ 2525 st_le32( &lastmd->next, (u nsigned32)phys_to_bus( nextmd ));2525 st_le32( &lastmd->next, (uint32_t )phys_to_bus( nextmd )); 2526 2526 } 2527 2527 … … 2575 2575 sc->xl_unit, 2576 2576 chainCount, 2577 (u nsigned32)ld_le32( &lastmd->status) );2577 (uint32_t )ld_le32( &lastmd->status) ); 2578 2578 #endif 2579 2579 … … 2658 2658 2659 2659 { 2660 u nsigned32cr,sr;2660 uint32_t cr,sr; 2661 2661 2662 2662 xl_miibus_writereg(sc, 0x18, MII_BMCR, BMCR_RESET ); … … 2928 2928 { 2929 2929 struct TXMD *chainhead; 2930 u nsigned32esize;2930 uint32_t esize; 2931 2931 2932 2932 while( rtems_message_queue_receive( chainRecoveryQueue, &chainhead, &esize, … … 3330 3330 pci_write_config_word(pbus, pdev, pfun, 3331 3331 PCI_COMMAND, 3332 (u nsigned16)( PCI_COMMAND_IO |3332 (uint16_t )( PCI_COMMAND_IO | 3333 3333 PCI_COMMAND_MASTER | 3334 3334 PCI_COMMAND_INVALIDATE | … … 3341 3341 &lvalue); 3342 3342 3343 sc->ioaddr = (u nsigned32)lvalue & PCI_BASE_ADDRESS_IO_MASK;3343 sc->ioaddr = (uint32_t )lvalue & PCI_BASE_ADDRESS_IO_MASK; 3344 3344 /* 3345 3345 ** Store the interrupt name, we'll use it later when we initialize … … 3361 3361 3362 3362 { 3363 u nsigned8pci_latency;3364 u nsigned8new_latency = 248;3363 uint8_t pci_latency; 3364 uint8_t new_latency = 248; 3365 3365 3366 3366 /* Check the PCI latency value. On the 3c590 series the latency timer -
c/src/libchip/network/if_fxp.c
r83c5fc1 ree4f57d 77 77 #include <pcibios.h> 78 78 #include <irq.h> 79 #include "pci.h"79 #include <rtems/pci.h> 80 80 81 81 #ifdef NS -
c/src/libchip/network/open_eth.c
r83c5fc1 ree4f57d 163 163 open_eth_interrupt_handler (rtems_vector_number v) 164 164 { 165 u nsigned32status;165 uint32_t status; 166 166 167 167 /* read and clear interrupt cause */ … … 191 191 } 192 192 193 static u nsigned32 read_mii(unsigned32addr)193 static uint32_t read_mii(uint32_t addr) 194 194 { 195 195 while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} … … 205 205 } 206 206 207 static void write_mii(u nsigned32 addr, unsigned32data)207 static void write_mii(uint32_t addr, uint32_t data) 208 208 { 209 209 while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} … … 301 301 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 302 302 sc->rxdesc[i].m = m; 303 sc->regs->xd[i + sc->txbufs].addr = mtod (m, u nsigned32*);303 sc->regs->xd[i + sc->txbufs].addr = mtod (m, uint32_t *); 304 304 sc->regs->xd[i + sc->txbufs].len_status = 305 305 OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; … … 419 419 dp->rxdesc[dp->rx_ptr].m = m; 420 420 dp->regs->xd[dp->rx_ptr + dp->txbufs].addr = 421 (u nsigned32*) mtod (m, void *);421 (uint32_t *) mtod (m, void *); 422 422 dp->rxPackets++; 423 423 } … … 459 459 len = 0; 460 460 temp = (unsigned char *) dp->txdesc[dp->tx_ptr].buf; 461 dp->regs->xd[dp->tx_ptr].addr = (u nsigned32*) temp;461 dp->regs->xd[dp->tx_ptr].addr = (uint32_t *) temp; 462 462 463 463 #ifdef OPEN_ETH_DEBUG -
c/src/libchip/network/open_eth.h
r83c5fc1 ree4f57d 9 9 10 10 typedef struct { 11 u nsigned32base_address;12 u nsigned32vector;13 u nsigned32txd_count;14 u nsigned32rxd_count;11 uint32_t base_address; 12 uint32_t vector; 13 uint32_t txd_count; 14 uint32_t rxd_count; 15 15 } open_eth_configuration_t; 16 16 … … 19 19 20 20 typedef struct _oeth_rxtxdesc { 21 volatile u nsigned32len_status; /* Length and status */22 volatile u nsigned32*addr; /* Buffer pointer */21 volatile uint32_t len_status; /* Length and status */ 22 volatile uint32_t *addr; /* Buffer pointer */ 23 23 } oeth_rxtxdesc; 24 24 … … 26 26 27 27 typedef struct _oeth_regs { 28 volatile u nsigned32moder; /* Mode Register */29 volatile u nsigned32int_src; /* Interrupt Source Register */30 volatile u nsigned32int_mask; /* Interrupt Mask Register */31 volatile u nsigned32ipgt; /* Back to Bak Inter Packet Gap Register */32 volatile u nsigned32ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */33 volatile u nsigned32ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */34 volatile u nsigned32packet_len; /* Packet Length Register (min. and max.) */35 volatile u nsigned32collconf; /* Collision and Retry Configuration Register */36 volatile u nsigned32tx_bd_num; /* Transmit Buffer Descriptor Number Register */37 volatile u nsigned32ctrlmoder; /* Control Module Mode Register */38 volatile u nsigned32miimoder; /* MII Mode Register */39 volatile u nsigned32miicommand; /* MII Command Register */40 volatile u nsigned32miiaddress; /* MII Address Register */41 volatile u nsigned32miitx_data; /* MII Transmit Data Register */42 volatile u nsigned32miirx_data; /* MII Receive Data Register */43 volatile u nsigned32miistatus; /* MII Status Register */44 volatile u nsigned32mac_addr0; /* MAC Individual Address Register 0 */45 volatile u nsigned32mac_addr1; /* MAC Individual Address Register 1 */46 volatile u nsigned32hash_addr0; /* Hash Register 0 */47 volatile u nsigned32hash_addr1; /* Hash Register 1 */48 volatile u nsigned32txctrl; /* Transmitter control register */49 u nsigned32empty[235]; /* Unused space */28 volatile uint32_t moder; /* Mode Register */ 29 volatile uint32_t int_src; /* Interrupt Source Register */ 30 volatile uint32_t int_mask; /* Interrupt Mask Register */ 31 volatile uint32_t ipgt; /* Back to Bak Inter Packet Gap Register */ 32 volatile uint32_t ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ 33 volatile uint32_t ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ 34 volatile uint32_t packet_len; /* Packet Length Register (min. and max.) */ 35 volatile uint32_t collconf; /* Collision and Retry Configuration Register */ 36 volatile uint32_t tx_bd_num; /* Transmit Buffer Descriptor Number Register */ 37 volatile uint32_t ctrlmoder; /* Control Module Mode Register */ 38 volatile uint32_t miimoder; /* MII Mode Register */ 39 volatile uint32_t miicommand; /* MII Command Register */ 40 volatile uint32_t miiaddress; /* MII Address Register */ 41 volatile uint32_t miitx_data; /* MII Transmit Data Register */ 42 volatile uint32_t miirx_data; /* MII Receive Data Register */ 43 volatile uint32_t miistatus; /* MII Status Register */ 44 volatile uint32_t mac_addr0; /* MAC Individual Address Register 0 */ 45 volatile uint32_t mac_addr1; /* MAC Individual Address Register 1 */ 46 volatile uint32_t hash_addr0; /* Hash Register 0 */ 47 volatile uint32_t hash_addr1; /* Hash Register 1 */ 48 volatile uint32_t txctrl; /* Transmitter control register */ 49 uint32_t empty[235]; /* Unused space */ 50 50 oeth_rxtxdesc xd[128]; /* TX & RX descriptors */ 51 51 } oeth_regs; -
c/src/libchip/network/sonic.c
r83c5fc1 ree4f57d 59 59 */ 60 60 61 void *set_vector(void *, u nsigned32, unsigned32);61 void *set_vector(void *, uint32_t , uint32_t ); 62 62 63 63 #if (SONIC_DEBUG & SONIC_DEBUG_DUMP_MBUFS) … … 117 117 * Macros for manipulating 32-bit pointers as 16-bit fragments 118 118 */ 119 #define LSW(p) (( rtems_unsigned16)((rtems_unsigned32)(p)))120 #define MSW(p) (( rtems_unsigned16)((rtems_unsigned32)(p) >> 16))121 #define PTR(m,l) ((void*)((( rtems_unsigned16)(m)<<16)|(rtems_unsigned16)(l)))119 #define LSW(p) ((uint16_t )((uint32_t )(p))) 120 #define MSW(p) ((uint16_t )((uint32_t )(p) >> 16)) 121 #define PTR(m,l) ((void*)(((uint16_t )(m)<<16)|(uint16_t )(l))) 122 122 123 123 /* … … 152 152 * Data Configuration Register values 153 153 */ 154 rtems_unsigned32dcr_value;155 rtems_unsigned32dc2_value;154 uint32_t dcr_value; 155 uint32_t dc2_value; 156 156 157 157 /* … … 264 264 void sonic_enable_interrupts( 265 265 struct sonic_softc *sc, 266 u nsigned32mask266 uint32_t mask 267 267 ) 268 268 { … … 281 281 void sonic_disable_interrupts( 282 282 struct sonic_softc *sc, 283 u nsigned32mask283 uint32_t mask 284 284 ) 285 285 { … … 298 298 void sonic_clear_interrupts( 299 299 struct sonic_softc *sc, 300 u nsigned32mask300 uint32_t mask 301 301 ) 302 302 { … … 311 311 void sonic_command( 312 312 struct sonic_softc *sc, 313 u nsigned32mask313 uint32_t mask 314 314 ) 315 315 { … … 403 403 { 404 404 struct sonic_softc *sc = sonic_softc; 405 u nsigned32isr, imr;405 uint32_t isr, imr; 406 406 void *rp; 407 407 … … 466 466 SONIC_STATIC void sonic_retire_tda (struct sonic_softc *sc) 467 467 { 468 rtems_unsigned16status;468 uint16_t status; 469 469 unsigned int collisions; 470 470 struct mbuf *m, *n; … … 501 501 * packets waiting to go. 502 502 */ 503 rtems_unsigned16link;503 uint16_t link; 504 504 #if (SONIC_DEBUG & SONIC_DEBUG_ERRORS) 505 505 printf("restarting sonic after error\n"); … … 931 931 void *rp = sc->sonic; 932 932 struct mbuf *m; 933 rtems_unsigned16status;933 uint16_t status; 934 934 ReceiveDescriptorPointer_t rdp; 935 935 ReceiveResourcePointer_t rwp, rea; 936 rtems_unsigned16newMissedTally, oldMissedTally;936 uint16_t newMissedTally, oldMissedTally; 937 937 938 938 rwp = sc->rsa; … … 986 986 m = rdp->mbufp; 987 987 m->m_len = m->m_pkthdr.len = rdp->byte_count - 988 sizeof( rtems_unsigned32) -988 sizeof(uint32_t ) - 989 989 sizeof(struct ether_header); 990 990 eh = mtod (m, struct ether_header *); -
c/src/libchip/network/sonic.h
r83c5fc1 ree4f57d 72 72 typedef void (*sonic_write_register_t)( 73 73 void *base, 74 u nsigned32regno,75 u nsigned32value74 uint32_t regno, 75 uint32_t value 76 76 ); 77 77 78 typedef u nsigned32(*sonic_read_register_t)(78 typedef uint32_t (*sonic_read_register_t)( 79 79 void *base, 80 u nsigned32regno80 uint32_t regno 81 81 ); 82 82 83 83 typedef struct { 84 u nsigned32base_address;85 u nsigned32vector;86 u nsigned32dcr_value;87 u nsigned32dc2_value;88 u nsigned32tda_count;89 u nsigned32rda_count;84 uint32_t base_address; 85 uint32_t vector; 86 uint32_t dcr_value; 87 uint32_t dc2_value; 88 uint32_t tda_count; 89 uint32_t rda_count; 90 90 sonic_write_register_t write_register; 91 91 sonic_read_register_t read_register; … … 303 303 #define MAXIMUM_FRAGS_PER_DESCRIPTOR 6 304 304 struct TransmitDescriptor { 305 rtems_unsigned32status;306 rtems_unsigned32pkt_config;307 rtems_unsigned32pkt_size;308 rtems_unsigned32frag_count;305 uint32_t status; 306 uint32_t pkt_config; 307 uint32_t pkt_size; 308 uint32_t frag_count; 309 309 310 310 /* … … 312 312 */ 313 313 struct TransmitDescriptorFragLink { 314 rtems_unsigned32frag_lsw; /* LSW of fragment address */314 uint32_t frag_lsw; /* LSW of fragment address */ 315 315 #define frag_link frag_lsw 316 rtems_unsigned32frag_msw; /* MSW of fragment address */317 rtems_unsigned32frag_size;316 uint32_t frag_msw; /* MSW of fragment address */ 317 uint32_t frag_size; 318 318 } frag[MAXIMUM_FRAGS_PER_DESCRIPTOR]; 319 319 … … 321 321 * Space for link if all fragment pointers are used. 322 322 */ 323 rtems_unsigned32link_pad;323 uint32_t link_pad; 324 324 325 325 /* … … 328 328 struct TransmitDescriptor *next; /* Circularly-linked list */ 329 329 struct mbuf *mbufp; /* First mbuf in packet */ 330 volatile rtems_unsigned32*linkp; /* Pointer to un[xxx].link */330 volatile uint32_t *linkp; /* Pointer to un[xxx].link */ 331 331 }; 332 332 typedef struct TransmitDescriptor TransmitDescriptor_t; … … 379 379 */ 380 380 struct ReceiveResource { 381 rtems_unsigned32buff_ptr_lsw; /* LSW of RBA address */382 rtems_unsigned32buff_ptr_msw; /* MSW of RBA address */383 rtems_unsigned32buff_wc_lsw; /* LSW of RBA size (16-bit words) */384 rtems_unsigned32buff_wc_msw; /* MSW of RBA size (16-bit words) */381 uint32_t buff_ptr_lsw; /* LSW of RBA address */ 382 uint32_t buff_ptr_msw; /* MSW of RBA address */ 383 uint32_t buff_wc_lsw; /* LSW of RBA size (16-bit words) */ 384 uint32_t buff_wc_msw; /* MSW of RBA size (16-bit words) */ 385 385 }; 386 386 typedef struct ReceiveResource ReceiveResource_t; … … 392 392 */ 393 393 struct ReceiveDescriptor { 394 rtems_unsigned32status;395 rtems_unsigned32byte_count;396 rtems_unsigned32pkt_lsw; /* LSW of packet address */397 rtems_unsigned32pkt_msw; /* MSW of packet address */398 rtems_unsigned32seq_no;399 rtems_unsigned32link;400 rtems_unsigned32in_use;394 uint32_t status; 395 uint32_t byte_count; 396 uint32_t pkt_lsw; /* LSW of packet address */ 397 uint32_t pkt_msw; /* MSW of packet address */ 398 uint32_t seq_no; 399 uint32_t link; 400 uint32_t in_use; 401 401 402 402 /* … … 410 410 411 411 typedef struct { 412 rtems_unsigned32cep; /* CAM Entry Pointer */413 rtems_unsigned32cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */414 rtems_unsigned32cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */415 rtems_unsigned32cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */416 rtems_unsigned32ce;412 uint32_t cep; /* CAM Entry Pointer */ 413 uint32_t cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ 414 uint32_t cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */ 415 uint32_t cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ 416 uint32_t ce; 417 417 } CamDescriptor_t; 418 418 -
c/src/libchip/rtc/icm7170.c
r83c5fc1 ree4f57d 42 42 ) 43 43 { 44 u nsigned32icm7170;44 uint32_t icm7170; 45 45 setRegister_f setReg; 46 u nsigned32clock;46 uint32_t clock; 47 47 48 48 icm7170 = RTC_Table[ minor ].ulCtrlPort1; … … 53 53 */ 54 54 55 clock = (u nsigned32) RTC_Table[ minor ].pDeviceParams;55 clock = (uint32_t ) RTC_Table[ minor ].pDeviceParams; 56 56 (*setReg)( icm7170, ICM7170_CONTROL, 0x0c | clock ); 57 57 } … … 66 66 ) 67 67 { 68 u nsigned32icm7170;68 uint32_t icm7170; 69 69 getRegister_f getReg; 70 70 setRegister_f setReg; 71 u nsigned32year;71 uint32_t year; 72 72 73 73 icm7170 = RTC_Table[ minor ].ulCtrlPort1; … … 119 119 ) 120 120 { 121 u nsigned32icm7170;121 uint32_t icm7170; 122 122 getRegister_f getReg; 123 123 setRegister_f setReg; 124 u nsigned32year;125 u nsigned32clock;124 uint32_t year; 125 uint32_t clock; 126 126 127 127 icm7170 = RTC_Table[ minor ].ulCtrlPort1; 128 128 getReg = RTC_Table[ minor ].getRegister; 129 129 setReg = RTC_Table[ minor ].setRegister; 130 clock = (u nsigned32) RTC_Table[ minor ].pDeviceParams;130 clock = (uint32_t ) RTC_Table[ minor ].pDeviceParams; 131 131 132 132 year = time->year; -
c/src/libchip/rtc/icm7170.h
r83c5fc1 ree4f57d 52 52 */ 53 53 54 u nsigned32icm7170_get_register( /* registers are at 1 byte boundaries */55 u nsigned32ulCtrlPort, /* and accessed as bytes */56 u nsigned8ucRegNum54 uint32_t icm7170_get_register( /* registers are at 1 byte boundaries */ 55 uint32_t ulCtrlPort, /* and accessed as bytes */ 56 uint8_t ucRegNum 57 57 ); 58 58 59 59 void icm7170_set_register( 60 u nsigned32ulCtrlPort,61 u nsigned8ucRegNum,62 u nsigned32ucData60 uint32_t ulCtrlPort, 61 uint8_t ucRegNum, 62 uint32_t ucData 63 63 ); 64 64 65 u nsigned32icm7170_get_register_2( /* registers are at 2 byte boundaries */66 u nsigned32ulCtrlPort, /* and accessed as bytes */67 u nsigned8ucRegNum65 uint32_t icm7170_get_register_2( /* registers are at 2 byte boundaries */ 66 uint32_t ulCtrlPort, /* and accessed as bytes */ 67 uint8_t ucRegNum 68 68 ); 69 69 70 70 void icm7170_set_register_2( 71 u nsigned32ulCtrlPort,72 u nsigned8ucRegNum,73 u nsigned32ucData71 uint32_t ulCtrlPort, 72 uint8_t ucRegNum, 73 uint32_t ucData 74 74 ); 75 75 76 u nsigned32icm7170_get_register_4( /* registers are at 4 byte boundaries */77 u nsigned32ulCtrlPort, /* and accessed as bytes */78 u nsigned8ucRegNum76 uint32_t icm7170_get_register_4( /* registers are at 4 byte boundaries */ 77 uint32_t ulCtrlPort, /* and accessed as bytes */ 78 uint8_t ucRegNum 79 79 ); 80 80 81 81 void icm7170_set_register_4( 82 u nsigned32ulCtrlPort,83 u nsigned8ucRegNum,84 u nsigned32ucData82 uint32_t ulCtrlPort, 83 uint8_t ucRegNum, 84 uint32_t ucData 85 85 ); 86 86 87 u nsigned32icm7170_get_register_8( /* registers are at 8 byte boundaries */88 u nsigned32ulCtrlPort, /* and accessed as bytes */89 u nsigned8ucRegNum87 uint32_t icm7170_get_register_8( /* registers are at 8 byte boundaries */ 88 uint32_t ulCtrlPort, /* and accessed as bytes */ 89 uint8_t ucRegNum 90 90 ); 91 91 92 92 void icm7170_set_register_8( 93 u nsigned32ulCtrlPort,94 u nsigned8ucRegNum,95 u nsigned32ucData93 uint32_t ulCtrlPort, 94 uint8_t ucRegNum, 95 uint32_t ucData 96 96 ); 97 97 -
c/src/libchip/rtc/icm7170_reg.c
r83c5fc1 ree4f57d 21 21 #define _ICM7170_MULTIPLIER 1 22 22 #define _ICM7170_NAME(_X) _X 23 #define _ICM7170_TYPE u nsigned823 #define _ICM7170_TYPE uint8_t 24 24 #endif 25 25 … … 31 31 */ 32 32 33 u nsigned32_ICM7170_NAME(icm7170_get_register)(34 u nsigned32ulCtrlPort,35 u nsigned8ucRegNum33 uint32_t _ICM7170_NAME(icm7170_get_register)( 34 uint32_t ulCtrlPort, 35 uint8_t ucRegNum 36 36 ) 37 37 { … … 48 48 49 49 void _ICM7170_NAME(icm7170_set_register)( 50 u nsigned32ulCtrlPort,51 u nsigned8ucRegNum,52 u nsigned32ucData50 uint32_t ulCtrlPort, 51 uint8_t ucRegNum, 52 uint32_t ucData 53 53 ) 54 54 { -
c/src/libchip/rtc/icm7170_reg2.c
r83c5fc1 ree4f57d 18 18 #define _ICM7170_MULTIPLIER 2 19 19 #define _ICM7170_NAME(_X) _X##_2 20 #define _ICM7170_TYPE u nsigned820 #define _ICM7170_TYPE uint8_t 21 21 22 22 #include "icm7170_reg.c" -
c/src/libchip/rtc/icm7170_reg4.c
r83c5fc1 ree4f57d 18 18 #define _ICM7170_MULTIPLIER 4 19 19 #define _ICM7170_NAME(_X) _X##_4 20 #define _ICM7170_TYPE u nsigned820 #define _ICM7170_TYPE uint8_t 21 21 22 22 #include "icm7170_reg.c" -
c/src/libchip/rtc/icm7170_reg8.c
r83c5fc1 ree4f57d 18 18 #define _ICM7170_MULTIPLIER 8 19 19 #define _ICM7170_NAME(_X) _X##_8 20 #define _ICM7170_TYPE u nsigned820 #define _ICM7170_TYPE uint8_t 21 21 22 22 #include "icm7170_reg.c" -
c/src/libchip/rtc/m48t08.c
r83c5fc1 ree4f57d 58 58 ) 59 59 { 60 u nsigned32m48t08;60 uint32_t m48t08; 61 61 getRegister_f getReg; 62 62 setRegister_f setReg; 63 u nsigned8controlReg;64 u nsigned32value1;65 u nsigned32value2;63 uint8_t controlReg; 64 uint32_t value1; 65 uint32_t value2; 66 66 67 67 m48t08 = RTC_Table[ minor ].ulCtrlPort1; … … 118 118 ) 119 119 { 120 u nsigned32m48t08;120 uint32_t m48t08; 121 121 getRegister_f getReg; 122 122 setRegister_f setReg; 123 u nsigned8controlReg;123 uint8_t controlReg; 124 124 125 125 m48t08 = RTC_Table[ minor ].ulCtrlPort1; -
c/src/libchip/rtc/m48t08.h
r83c5fc1 ree4f57d 42 42 */ 43 43 44 u nsigned32m48t08_get_register( /* registers are at 1 byte boundaries */45 u nsigned32ulCtrlPort, /* and accessed as bytes */46 u nsigned8ucRegNum44 uint32_t m48t08_get_register( /* registers are at 1 byte boundaries */ 45 uint32_t ulCtrlPort, /* and accessed as bytes */ 46 uint8_t ucRegNum 47 47 ); 48 48 49 49 void m48t08_set_register( 50 u nsigned32ulCtrlPort,51 u nsigned8ucRegNum,52 u nsigned32ucData50 uint32_t ulCtrlPort, 51 uint8_t ucRegNum, 52 uint32_t ucData 53 53 ); 54 54 55 u nsigned32m48t08_get_register_2( /* registers are at 2 byte boundaries */56 u nsigned32ulCtrlPort, /* and accessed as bytes */57 u nsigned8ucRegNum55 uint32_t m48t08_get_register_2( /* registers are at 2 byte boundaries */ 56 uint32_t ulCtrlPort, /* and accessed as bytes */ 57 uint8_t ucRegNum 58 58 ); 59 59 60 60 void m48t08_set_register_2( 61 u nsigned32ulCtrlPort,62 u nsigned8ucRegNum,63 u nsigned32ucData61 uint32_t ulCtrlPort, 62 uint8_t ucRegNum, 63 uint32_t ucData 64 64 ); 65 65 66 u nsigned32m48t08_get_register_4( /* registers are at 4 byte boundaries */67 u nsigned32ulCtrlPort, /* and accessed as bytes */68 u nsigned8ucRegNum66 uint32_t m48t08_get_register_4( /* registers are at 4 byte boundaries */ 67 uint32_t ulCtrlPort, /* and accessed as bytes */ 68 uint8_t ucRegNum 69 69 ); 70 70 71 71 void m48t08_set_register_4( 72 u nsigned32ulCtrlPort,73 u nsigned8ucRegNum,74 u nsigned32ucData72 uint32_t ulCtrlPort, 73 uint8_t ucRegNum, 74 uint32_t ucData 75 75 ); 76 76 77 u nsigned32m48t08_get_register_8( /* registers are at 8 byte boundaries */78 u nsigned32ulCtrlPort, /* and accessed as bytes */79 u nsigned8ucRegNum77 uint32_t m48t08_get_register_8( /* registers are at 8 byte boundaries */ 78 uint32_t ulCtrlPort, /* and accessed as bytes */ 79 uint8_t ucRegNum 80 80 ); 81 81 82 82 void m48t08_set_register_8( 83 u nsigned32ulCtrlPort,84 u nsigned8ucRegNum,85 u nsigned32ucData83 uint32_t ulCtrlPort, 84 uint8_t ucRegNum, 85 uint32_t ucData 86 86 ); 87 87 -
c/src/libchip/rtc/m48t08_reg.c
r83c5fc1 ree4f57d 21 21 #define _M48T08_MULTIPLIER 1 22 22 #define _M48T08_NAME(_X) _X 23 #define _M48T08_TYPE u nsigned823 #define _M48T08_TYPE uint8_t 24 24 #endif 25 25 … … 31 31 */ 32 32 33 u nsigned32_M48T08_NAME(m48t08_get_register)(34 u nsigned32ulCtrlPort,35 u nsigned8ucRegNum33 uint32_t _M48T08_NAME(m48t08_get_register)( 34 uint32_t ulCtrlPort, 35 uint8_t ucRegNum 36 36 ) 37 37 { … … 48 48 49 49 void _M48T08_NAME(m48t08_set_register)( 50 u nsigned32ulCtrlPort,51 u nsigned8ucRegNum,52 u nsigned32ucData50 uint32_t ulCtrlPort, 51 uint8_t ucRegNum, 52 uint32_t ucData 53 53 ) 54 54 { -
c/src/libchip/rtc/m48t08_reg2.c
r83c5fc1 ree4f57d 18 18 #define _M48T08_MULTIPLIER 2 19 19 #define _M48T08_NAME(_X) _X##_2 20 #define _M48T08_TYPE u nsigned820 #define _M48T08_TYPE uint8_t 21 21 22 22 #include "m48t08_reg.c" -
c/src/libchip/rtc/m48t08_reg4.c
r83c5fc1 ree4f57d 18 18 #define _M48T08_MULTIPLIER 4 19 19 #define _M48T08_NAME(_X) _X##_4 20 #define _M48T08_TYPE u nsigned820 #define _M48T08_TYPE uint8_t 21 21 22 22 #include "m48t08_reg.c" -
c/src/libchip/rtc/m48t08_reg8.c
r83c5fc1 ree4f57d 18 18 #define _M48T08_MULTIPLIER 8 19 19 #define _M48T08_NAME(_X) _X##_8 20 #define _M48T08_TYPE u nsigned820 #define _M48T08_TYPE uint8_t 21 21 22 22 #include "m48t08_reg.c" -
c/src/libchip/rtc/rtc.h
r83c5fc1 ree4f57d 20 20 */ 21 21 22 typedef u nsigned32 (*getRegister_f)(unsigned32 port, unsigned8register);22 typedef uint32_t (*getRegister_f)(uint32_t port, uint8_t register); 23 23 typedef void (*setRegister_f)( 24 u nsigned32 port, unsigned8 reg, unsigned32value);24 uint32_t port, uint8_t reg, uint32_t value); 25 25 26 26 typedef struct _rtc_fns { … … 65 65 boolean (*deviceProbe)(int minor); 66 66 void *pDeviceParams; 67 u nsigned32ulCtrlPort1;68 u nsigned32ulDataPort;67 uint32_t ulCtrlPort1; 68 uint32_t ulDataPort; 69 69 getRegister_f getRegister; 70 70 setRegister_f setRegister; -
c/src/libchip/serial/mc68681.c
r83c5fc1 ree4f57d 90 90 ) 91 91 { 92 u nsigned32pMC68681_port;93 u nsigned32pMC68681;92 uint32_t pMC68681_port; 93 uint32_t pMC68681; 94 94 unsigned int mode1; 95 95 unsigned int mode2; … … 220 220 MC68681_STATIC void mc68681_init(int minor) 221 221 { 222 u nsigned32pMC68681_port;223 u nsigned32pMC68681;222 uint32_t pMC68681_port; 223 uint32_t pMC68681; 224 224 mc68681_context *pmc68681Context; 225 225 setRegister_f setReg; … … 274 274 ) 275 275 { 276 u nsigned32pMC68681;277 u nsigned32pMC68681_port;276 uint32_t pMC68681; 277 uint32_t pMC68681_port; 278 278 unsigned int baud; 279 279 unsigned int acr_bit; … … 331 331 ) 332 332 { 333 u nsigned32pMC68681;334 u nsigned32pMC68681_port;333 uint32_t pMC68681; 334 uint32_t pMC68681_port; 335 335 setRegister_f setReg; 336 336 … … 362 362 ) 363 363 { 364 u nsigned32pMC68681_port;364 uint32_t pMC68681_port; 365 365 unsigned char ucLineStatus; 366 366 int iTimeout; … … 455 455 ) 456 456 { 457 u nsigned32Irql;458 u nsigned32pMC68681_port;457 uint32_t Irql; 458 uint32_t pMC68681_port; 459 459 setRegister_f setReg; 460 460 … … 527 527 ) 528 528 { 529 u nsigned32pMC68681_port;529 uint32_t pMC68681_port; 530 530 unsigned char ucLineStatus; 531 531 unsigned char cChar; … … 624 624 ) 625 625 { 626 u nsigned32pMC68681;627 u nsigned32pMC68681_port;628 volatile u nsigned8ucLineStatus;629 volatile u nsigned8ucISRStatus;626 uint32_t pMC68681; 627 uint32_t pMC68681_port; 628 volatile uint8_t ucLineStatus; 629 volatile uint8_t ucISRStatus; 630 630 unsigned char cChar; 631 631 getRegister_f getReg; … … 763 763 ) 764 764 { 765 u nsigned32pMC68681;765 uint32_t pMC68681; 766 766 setRegister_f setReg; 767 767 -
c/src/libchip/serial/mc68681.h
r83c5fc1 ree4f57d 71 71 */ 72 72 73 u nsigned8mc68681_get_register( /* registers are at 1 byte boundaries */74 u nsigned32ulCtrlPort, /* and accessed as bytes */75 u nsigned8ucRegNum73 uint8_t mc68681_get_register( /* registers are at 1 byte boundaries */ 74 uint32_t ulCtrlPort, /* and accessed as bytes */ 75 uint8_t ucRegNum 76 76 ); 77 77 78 78 void mc68681_set_register( 79 u nsigned32ulCtrlPort,80 u nsigned8ucRegNum,81 u nsigned8ucData79 uint32_t ulCtrlPort, 80 uint8_t ucRegNum, 81 uint8_t ucData 82 82 ); 83 83 84 u nsigned8mc68681_get_register_2( /* registers are at 2 byte boundaries */85 u nsigned32ulCtrlPort, /* and accessed as bytes */86 u nsigned8ucRegNum84 uint8_t mc68681_get_register_2( /* registers are at 2 byte boundaries */ 85 uint32_t ulCtrlPort, /* and accessed as bytes */ 86 uint8_t ucRegNum 87 87 ); 88 88 89 89 void mc68681_set_register_2( 90 u nsigned32ulCtrlPort,91 u nsigned8ucRegNum,92 u nsigned8ucData90 uint32_t ulCtrlPort, 91 uint8_t ucRegNum, 92 uint8_t ucData 93 93 ); 94 94 95 u nsigned8mc68681_get_register_4( /* registers are at 4 byte boundaries */96 u nsigned32ulCtrlPort, /* and accessed as bytes */97 u nsigned8ucRegNum95 uint8_t mc68681_get_register_4( /* registers are at 4 byte boundaries */ 96 uint32_t ulCtrlPort, /* and accessed as bytes */ 97 uint8_t ucRegNum 98 98 ); 99 99 100 100 void mc68681_set_register_4( 101 u nsigned32ulCtrlPort,102 u nsigned8ucRegNum,103 u nsigned8ucData101 uint32_t ulCtrlPort, 102 uint8_t ucRegNum, 103 uint8_t ucData 104 104 ); 105 105 106 u nsigned8mc68681_get_register_8( /* registers are at 8 byte boundaries */107 u nsigned32ulCtrlPort, /* and accessed as bytes */108 u nsigned8ucRegNum106 uint8_t mc68681_get_register_8( /* registers are at 8 byte boundaries */ 107 uint32_t ulCtrlPort, /* and accessed as bytes */ 108 uint8_t ucRegNum 109 109 ); 110 110 111 111 void mc68681_set_register_8( 112 u nsigned32ulCtrlPort,113 u nsigned8ucRegNum,114 u nsigned8ucData112 uint32_t ulCtrlPort, 113 uint8_t ucRegNum, 114 uint8_t ucData 115 115 ); 116 116 -
c/src/libchip/serial/mc68681_reg.c
r83c5fc1 ree4f57d 21 21 #define _MC68681_MULTIPLIER 1 22 22 #define _MC68681_NAME(_X) _X 23 #define _MC68681_TYPE u nsigned823 #define _MC68681_TYPE uint8_t 24 24 #endif 25 25 … … 31 31 */ 32 32 33 u nsigned8_MC68681_NAME(mc68681_get_register)(34 u nsigned32ulCtrlPort,35 u nsigned8ucRegNum33 uint8_t _MC68681_NAME(mc68681_get_register)( 34 uint32_t ulCtrlPort, 35 uint8_t ucRegNum 36 36 ) 37 37 { … … 48 48 49 49 void _MC68681_NAME(mc68681_set_register)( 50 u nsigned32ulCtrlPort,51 u nsigned8ucRegNum,52 u nsigned8ucData50 uint32_t ulCtrlPort, 51 uint8_t ucRegNum, 52 uint8_t ucData 53 53 ) 54 54 { -
c/src/libchip/serial/mc68681_reg2.c
r83c5fc1 ree4f57d 18 18 #define _MC68681_MULTIPLIER 2 19 19 #define _MC68681_NAME(_X) _X##_2 20 #define _MC68681_TYPE u nsigned820 #define _MC68681_TYPE uint8_t 21 21 22 22 #include "mc68681_reg.c" -
c/src/libchip/serial/mc68681_reg4.c
r83c5fc1 ree4f57d 18 18 #define _MC68681_MULTIPLIER 4 19 19 #define _MC68681_NAME(_X) _X##_4 20 #define _MC68681_TYPE u nsigned820 #define _MC68681_TYPE uint8_t 21 21 22 22 #include "mc68681_reg.c" -
c/src/libchip/serial/mc68681_reg8.c
r83c5fc1 ree4f57d 18 18 #define _MC68681_MULTIPLIER 8 19 19 #define _MC68681_NAME(_X) _X##_8 20 #define _MC68681_TYPE u nsigned820 #define _MC68681_TYPE uint8_t 21 21 22 22 #include "mc68681_reg.c" -
c/src/libchip/serial/ns16550.c
r83c5fc1 ree4f57d 76 76 NS16550_STATIC void ns16550_init(int minor) 77 77 { 78 u nsigned32pNS16550;79 u nsigned8ucTrash;80 u nsigned8ucDataByte;81 u nsigned32ulBaudDivisor;78 uint32_t pNS16550; 79 uint8_t ucTrash; 80 uint8_t ucDataByte; 81 uint32_t ulBaudDivisor; 82 82 ns16550_context *pns16550Context; 83 83 setRegister_f setReg; … … 104 104 105 105 ulBaudDivisor = NS16550_Baud( 106 (u nsigned32) Console_Port_Tbl[minor].ulClock,107 (u nsigned32) Console_Port_Tbl[minor].pDeviceParams106 (uint32_t ) Console_Port_Tbl[minor].ulClock, 107 (uint32_t ) Console_Port_Tbl[minor].pDeviceParams 108 108 ); 109 109 ucDataByte = SP_LINE_DLAB; … … 186 186 ) 187 187 { 188 u nsigned32pNS16550;188 uint32_t pNS16550; 189 189 unsigned char ucLineStatus; 190 190 int iTimeout; … … 232 232 NS16550_STATIC int ns16550_assert_RTS(int minor) 233 233 { 234 u nsigned32pNS16550;235 u nsigned32Irql;234 uint32_t pNS16550; 235 uint32_t Irql; 236 236 ns16550_context *pns16550Context; 237 237 setRegister_f setReg; … … 258 258 NS16550_STATIC int ns16550_negate_RTS(int minor) 259 259 { 260 u nsigned32pNS16550;261 u nsigned32Irql;260 uint32_t pNS16550; 261 uint32_t Irql; 262 262 ns16550_context *pns16550Context; 263 263 setRegister_f setReg; … … 289 289 NS16550_STATIC int ns16550_assert_DTR(int minor) 290 290 { 291 u nsigned32pNS16550;292 u nsigned32Irql;291 uint32_t pNS16550; 292 uint32_t Irql; 293 293 ns16550_context *pns16550Context; 294 294 setRegister_f setReg; … … 315 315 NS16550_STATIC int ns16550_negate_DTR(int minor) 316 316 { 317 u nsigned32pNS16550;318 u nsigned32Irql;317 uint32_t pNS16550; 318 uint32_t Irql; 319 319 ns16550_context *pns16550Context; 320 320 setRegister_f setReg; … … 347 347 ) 348 348 { 349 u nsigned32pNS16550;350 u nsigned32ulBaudDivisor;351 u nsigned8ucLineControl;352 u nsigned32baud_requested;349 uint32_t pNS16550; 350 uint32_t ulBaudDivisor; 351 uint8_t ucLineControl; 352 uint32_t baud_requested; 353 353 setRegister_f setReg; 354 354 getRegister_f getReg; 355 u nsigned32Irql;355 uint32_t Irql; 356 356 357 357 pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; … … 368 368 369 369 ulBaudDivisor = NS16550_Baud( 370 (u nsigned32) Console_Port_Tbl[minor].ulClock,370 (uint32_t ) Console_Port_Tbl[minor].ulClock, 371 371 termios_baud_to_number(baud_requested) 372 372 ); … … 444 444 ) 445 445 { 446 u nsigned32pNS16550;447 volatile u nsigned8ucLineStatus;448 volatile u nsigned8ucInterruptId;446 uint32_t pNS16550; 447 volatile uint8_t ucLineStatus; 448 volatile uint8_t ucInterruptId; 449 449 unsigned char cChar; 450 450 getRegister_f getReg; … … 540 540 ) 541 541 { 542 u nsigned32pNS16550;542 uint32_t pNS16550; 543 543 setRegister_f setReg; 544 544 … … 578 578 ) 579 579 { 580 u nsigned32Irql;581 u nsigned32pNS16550;580 uint32_t Irql; 581 uint32_t pNS16550; 582 582 setRegister_f setReg; 583 583 … … 650 650 ) 651 651 { 652 u nsigned32pNS16550;652 uint32_t pNS16550; 653 653 unsigned char ucLineStatus; 654 654 char cChar; -
c/src/libchip/serial/ns16550_p.h
r83c5fc1 ree4f57d 161 161 typedef struct _ns16550_context 162 162 { 163 u nsigned8ucModemCtrl;163 uint8_t ucModemCtrl; 164 164 } ns16550_context; 165 165 -
c/src/libchip/serial/serial.h
r83c5fc1 ree4f57d 23 23 */ 24 24 25 typedef u nsigned8 (*getRegister_f)(unsigned32 port, unsigned8register);25 typedef uint8_t (*getRegister_f)(uint32_t port, uint8_t register); 26 26 typedef void (*setRegister_f)( 27 u nsigned32 port, unsigned8 reg, unsigned8value);28 typedef u nsigned8 (*getData_f)(unsigned32port);29 typedef void (*setData_f)(u nsigned32 port, unsigned8value);27 uint32_t port, uint8_t reg, uint8_t value); 28 typedef uint8_t (*getData_f)(uint32_t port); 29 typedef void (*setData_f)(uint32_t port, uint8_t value); 30 30 31 31 typedef struct _console_fns { … … 121 121 boolean (*deviceProbe)(int minor); 122 122 console_flow *pDeviceFlow; 123 u nsigned32ulMargin;124 u nsigned32ulHysteresis;123 uint32_t ulMargin; 124 uint32_t ulHysteresis; 125 125 void *pDeviceParams; 126 u nsigned32ulCtrlPort1;127 u nsigned32ulCtrlPort2;128 u nsigned32ulDataPort;126 uint32_t ulCtrlPort1; 127 uint32_t ulCtrlPort2; 128 uint32_t ulDataPort; 129 129 getRegister_f getRegister; 130 130 setRegister_f setRegister; 131 131 getData_f getData; 132 132 setData_f setData; 133 u nsigned32ulClock;133 uint32_t ulClock; 134 134 unsigned int ulIntVector; 135 135 } console_tbl; -
c/src/libchip/serial/z85c30.c
r83c5fc1 ree4f57d 93 93 ) 94 94 { 95 u nsigned32ulCtrlPort;96 u nsigned32ulBaudDivisor;95 uint32_t ulCtrlPort; 96 uint32_t ulBaudDivisor; 97 97 setRegister_f setReg; 98 98 … … 138 138 139 139 ulBaudDivisor = Z85C30_Baud( 140 (u nsigned32) Console_Port_Tbl[minor].ulClock,141 (u nsigned32) Console_Port_Tbl[minor].pDeviceParams140 (uint32_t ) Console_Port_Tbl[minor].ulClock, 141 (uint32_t ) Console_Port_Tbl[minor].pDeviceParams 142 142 ); 143 143 … … 254 254 Z85C30_STATIC void z85c30_init(int minor) 255 255 { 256 u nsigned32ulCtrlPort;257 u nsigned8dummy;256 uint32_t ulCtrlPort; 257 uint8_t dummy; 258 258 z85c30_context *pz85c30Context; 259 259 setRegister_f setReg; … … 431 431 ) 432 432 { 433 u nsigned32ulCtrlPort;434 u nsigned32ulBaudDivisor;435 u nsigned32wr3;436 u nsigned32wr4;437 u nsigned32wr5;433 uint32_t ulCtrlPort; 434 uint32_t ulBaudDivisor; 435 uint32_t wr3; 436 uint32_t wr4; 437 uint32_t wr5; 438 438 int baud_requested; 439 439 setRegister_f setReg; … … 452 452 453 453 ulBaudDivisor = Z85C30_Baud( 454 (u nsigned32) Console_Port_Tbl[minor].ulClock,455 (u nsigned32) termios_baud_to_number( baud_requested )454 (uint32_t ) Console_Port_Tbl[minor].ulClock, 455 (uint32_t ) termios_baud_to_number( baud_requested ) 456 456 ); 457 457 … … 533 533 Z85C30_STATIC void z85c30_process( 534 534 int minor, 535 u nsigned8ucIntPend536 ) 537 { 538 u nsigned32ulCtrlPort;539 volatile u nsigned8z85c30_status;535 uint8_t ucIntPend 536 ) 537 { 538 uint32_t ulCtrlPort; 539 volatile uint8_t z85c30_status; 540 540 unsigned char cChar; 541 541 setRegister_f setReg; … … 642 642 { 643 643 int minor; 644 u nsigned32ulCtrlPort;645 volatile u nsigned8ucIntPend;646 volatile u nsigned8ucIntPendPort;644 uint32_t ulCtrlPort; 645 volatile uint8_t ucIntPend; 646 volatile uint8_t ucIntPendPort; 647 647 getRegister_f getReg; 648 648 … … 685 685 ) 686 686 { 687 u nsigned32ulCtrlPort;687 uint32_t ulCtrlPort; 688 688 setRegister_f setReg; 689 689 … … 704 704 ) 705 705 { 706 u nsigned32ulCtrlPort1;707 u nsigned32ulCtrlPort2;706 uint32_t ulCtrlPort1; 707 uint32_t ulCtrlPort2; 708 708 setRegister_f setReg; 709 709 … … 749 749 int len) 750 750 { 751 u nsigned32Irql;752 u nsigned32ulCtrlPort;751 uint32_t Irql; 752 uint32_t ulCtrlPort; 753 753 setRegister_f setReg; 754 754 … … 792 792 ) 793 793 { 794 volatile u nsigned8z85c30_status;795 u nsigned32ulCtrlPort;794 volatile uint8_t z85c30_status; 795 uint32_t ulCtrlPort; 796 796 getRegister_f getReg; 797 797 … … 853 853 ) 854 854 { 855 volatile u nsigned8z85c30_status;856 u nsigned32ulCtrlPort;855 volatile uint8_t z85c30_status; 856 uint32_t ulCtrlPort; 857 857 getRegister_f getReg; 858 858 setRegister_f setReg; -
c/src/libchip/serial/z85c30.h
r83c5fc1 ree4f57d 51 51 */ 52 52 53 u nsigned8z85c30_get_register( /* registers are byte-wide */54 u nsigned32ulCtrlPort,55 u nsigned8ucRegNum53 uint8_t z85c30_get_register( /* registers are byte-wide */ 54 uint32_t ulCtrlPort, 55 uint8_t ucRegNum 56 56 ); 57 57 58 58 void z85c30_set_register( 59 u nsigned32ulCtrlPort,60 u nsigned8ucRegNum,61 u nsigned8ucData59 uint32_t ulCtrlPort, 60 uint8_t ucRegNum, 61 uint8_t ucData 62 62 ); 63 63 64 u nsigned8z85c30_get_data(65 u nsigned32ulDataPort64 uint8_t z85c30_get_data( 65 uint32_t ulDataPort 66 66 ); 67 67 68 68 void z85c30_set_data( 69 u nsigned32ulDataPort,70 u nsigned8ucData69 uint32_t ulDataPort, 70 uint8_t ucData 71 71 ); 72 72 -
c/src/libchip/serial/z85c30_p.h
r83c5fc1 ree4f57d 311 311 typedef struct _z85c30_context 312 312 { 313 u nsigned8ucModemCtrl;313 uint8_t ucModemCtrl; 314 314 } z85c30_context; 315 315 -
c/src/libchip/serial/z85c30_reg.c
r83c5fc1 ree4f57d 20 20 #define _Z85C30_MULTIPLIER 1 21 21 #define _Z85C30_NAME(_X) _X 22 #define _Z85C30_TYPE u nsigned822 #define _Z85C30_TYPE uint8_t 23 23 #endif 24 24 … … 27 27 */ 28 28 29 u nsigned8_Z85C30_NAME(z85c30_get_register)(30 u nsigned32ulCtrlPort,31 u nsigned8ucRegNum29 uint8_t _Z85C30_NAME(z85c30_get_register)( 30 uint32_t ulCtrlPort, 31 uint8_t ucRegNum 32 32 ) 33 33 { 34 34 _Z85C30_TYPE *port; 35 u nsigned8data;35 uint8_t data; 36 36 rtems_interrupt_level level; 37 37 … … 54 54 55 55 void _Z85C30_NAME(z85c30_set_register)( 56 u nsigned32ulCtrlPort,57 u nsigned8ucRegNum,58 u nsigned8ucData56 uint32_t ulCtrlPort, 57 uint8_t ucRegNum, 58 uint8_t ucData 59 59 ) 60 60 { -
c/src/libchip/shmdr/addlq.c
r83c5fc1 ree4f57d 27 27 ) 28 28 { 29 rtems_unsigned32index;29 uint32_t index; 30 30 31 31 ecb->next = Shm_Locked_queue_End_of_list; -
c/src/libchip/shmdr/cnvpkt.c
r83c5fc1 ree4f57d 31 31 ) 32 32 { 33 rtems_unsigned32*pkt, i;33 uint32_t *pkt, i; 34 34 35 pkt = ( rtems_unsigned32*) packet;35 pkt = (uint32_t *) packet; 36 36 for ( i=RTEMS_MINIMUN_HETERO_CONVERSION ; i ; i--, pkt++ ) 37 37 *pkt = CPU_swap_u32( *pkt ); -
c/src/libchip/shmdr/dump.c
r83c5fc1 ree4f57d 25 25 Shm_Print_statistics(void) 26 26 { 27 rtems_unsigned32ticks;28 rtems_unsigned32ticks_per_second;29 rtems_unsigned32seconds;27 uint32_t ticks; 28 uint32_t ticks_per_second; 29 uint32_t seconds; 30 30 int packets_per_second; 31 31 -
c/src/libchip/shmdr/fatal.c
r83c5fc1 ree4f57d 24 24 Internal_errors_Source source, 25 25 boolean is_internal, 26 rtems_unsigned32error26 uint32_t error 27 27 ) 28 28 { -
c/src/libchip/shmdr/getlq.c
r83c5fc1 ree4f57d 29 29 { 30 30 Shm_Envelope_control *tmp_ecb; 31 rtems_unsigned32tmpfront;31 uint32_t tmpfront; 32 32 33 33 tmp_ecb = NULL; -
c/src/libchip/shmdr/init.c
r83c5fc1 ree4f57d 37 37 38 38 { 39 rtems_unsigned32i, all_initialized;40 rtems_unsigned32interrupt_cause, interrupt_value;39 uint32_t i, all_initialized; 40 uint32_t interrupt_cause, interrupt_value; 41 41 void *interrupt_address; 42 42 Shm_Node_status_control *nscb; 43 rtems_unsigned32extension_id; /* for installation of MPCI_Fatal */44 rtems_unsigned32remaining_memory;43 uint32_t extension_id; /* for installation of MPCI_Fatal */ 44 uint32_t remaining_memory; 45 45 /* XXX these should use "public" methods to set their values.... */ 46 46 rtems_configuration_table *configuration = _Configuration_Table; … … 123 123 124 124 interrupt_address = 125 (void *) Shm_Convert( ( rtems_unsigned32)Shm_Configuration->Intr.address );125 (void *) Shm_Convert( (uint32_t )Shm_Configuration->Intr.address ); 126 126 interrupt_value = Shm_Convert( Shm_Configuration->Intr.value ); 127 127 interrupt_cause = Shm_Convert( Shm_Configuration->Intr.length ); … … 173 173 */ 174 174 175 Shm_Local_node_status->int_address = ( rtems_unsigned32) interrupt_address;175 Shm_Local_node_status->int_address = (uint32_t ) interrupt_address; 176 176 Shm_Local_node_status->int_value = interrupt_value; 177 177 Shm_Local_node_status->int_length = interrupt_cause; … … 221 221 222 222 Shm_Local_node_status->int_address = 223 ( rtems_unsigned32) interrupt_address;223 (uint32_t ) interrupt_address; 224 224 Shm_Local_node_status->int_value = interrupt_value; 225 225 Shm_Local_node_status->int_length = interrupt_cause; -
c/src/libchip/shmdr/initlq.c
r83c5fc1 ree4f57d 25 25 void Shm_Locked_queue_Initialize( 26 26 Shm_Locked_queue_Control *lq_cb, 27 rtems_unsigned32owner27 uint32_t owner 28 28 ) 29 29 { -
c/src/libchip/shmdr/intr.c
r83c5fc1 ree4f57d 27 27 28 28 void Shm_Cause_interrupt( 29 rtems_unsigned32node29 uint32_t node 30 30 ) 31 31 { 32 32 Shm_Interrupt_information *intr; 33 rtems_unsigned8*u8;34 rtems_unsigned16*u16;35 rtems_unsigned32*u32;36 rtems_unsigned32value;33 uint8_t *u8; 34 uint16_t *u16; 35 uint32_t *u32; 36 uint32_t value; 37 37 38 38 intr = &Shm_Interrupt_table[node]; … … 43 43 break; 44 44 case BYTE: 45 u8 = ( rtems_unsigned8*)intr->address;46 *u8 = ( rtems_unsigned8) value;45 u8 = (uint8_t *)intr->address; 46 *u8 = (uint8_t ) value; 47 47 break; 48 48 case WORD: 49 u16 = ( rtems_unsigned16*)intr->address;50 *u16 = ( rtems_unsigned16) value;49 u16 = (uint16_t *)intr->address; 50 *u16 = (uint16_t ) value; 51 51 break; 52 52 case LONG: 53 u32 = ( rtems_unsigned32*)intr->address;54 *u32 = ( rtems_unsigned32) value;53 u32 = (uint32_t *)intr->address; 54 *u32 = (uint32_t ) value; 55 55 break; 56 56 } -
c/src/libchip/shmdr/poll.c
r83c5fc1 ree4f57d 27 27 void Shm_Poll() 28 28 { 29 rtems_unsigned32tmpfront;29 uint32_t tmpfront; 30 30 rtems_libio_ioctl_args_t args; 31 31 -
c/src/libchip/shmdr/send.c
r83c5fc1 ree4f57d 26 26 27 27 struct pkt_cpy { 28 rtems_unsigned32packet[MAX_PACKET_SIZE/4];28 uint32_t packet[MAX_PACKET_SIZE/4]; 29 29 }; 30 30 31 31 rtems_mpci_entry Shm_Send_packet( 32 rtems_unsigned32node,32 uint32_t node, 33 33 rtems_packet_prefix *packet 34 34 ) 35 35 { 36 36 Shm_Envelope_control *ecb, *tmp_ecb; 37 rtems_unsigned32nnum;37 uint32_t nnum; 38 38 39 39 ecb = Shm_Packet_prefix_to_envelope_control_pointer( packet ); -
c/src/libchip/shmdr/shm_driver.h
r83c5fc1 ree4f57d 85 85 * comply with the restrictive placement of lock bit by this 86 86 * instruction. The lock bit is the most significant bit in a 87 * big-endian rtems_unsigned32. On other processors, the lock is87 * big-endian uint32_t . On other processors, the lock is 88 88 * typically implemented via an atomic swap or atomic modify 89 89 * bits type instruction. … … 255 255 256 256 #define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \ 257 ((Shm_Envelope_control *)(( rtems_unsigned8*)(pkt) - \257 ((Shm_Envelope_control *)((uint8_t *)(pkt) - \ 258 258 (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD))) 259 259 … … 265 265 /* volatile types */ 266 266 267 typedef volatile rtems_unsigned8vol_u8;268 typedef volatile rtems_unsigned32vol_u32;267 typedef volatile uint8_t vol_u8; 268 typedef volatile uint32_t vol_u32; 269 269 270 270 /* shm control information */ … … 397 397 * address may be specific to this node. 398 398 * length - The length of the shared memory in bytes. 399 * format - The natural format for rtems_unsigned32's in the399 * format - The natural format for uint32_t 's in the 400 400 * shared memory. Valid values are currently 401 401 * only SHM_LITTLE and SHM_BIG. … … 426 426 vol_u32 (*convert)();/* neutral conversion routine */ 427 427 vol_u32 poll_intr;/* POLLED or INTR driven mode */ 428 void (*cause_intr)( rtems_unsigned32);428 void (*cause_intr)( uint32_t ); 429 429 Shm_Interrupt_information Intr; /* cause intr information */ 430 430 }; … … 447 447 SHM_EXTERN rtems_configuration_table *Shm_RTEMS_Configuration; 448 448 SHM_EXTERN rtems_multiprocessing_table *Shm_RTEMS_MP_Configuration; 449 SHM_EXTERN rtems_unsigned32Shm_Receive_message_count;450 SHM_EXTERN rtems_unsigned32Shm_Null_message_count;451 SHM_EXTERN rtems_unsigned32Shm_Interrupt_count;452 SHM_EXTERN rtems_unsigned32Shm_Local_node;449 SHM_EXTERN uint32_t Shm_Receive_message_count; 450 SHM_EXTERN uint32_t Shm_Null_message_count; 451 SHM_EXTERN uint32_t Shm_Interrupt_count; 452 SHM_EXTERN uint32_t Shm_Local_node; 453 453 SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue; 454 454 SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status; 455 SHM_EXTERN rtems_unsigned32Shm_isrstat;455 SHM_EXTERN uint32_t Shm_isrstat; 456 456 /* reported by shmdr */ 457 457 458 SHM_EXTERN rtems_unsigned32Shm_Pending_initialization;459 SHM_EXTERN rtems_unsigned32Shm_Initialization_complete;460 SHM_EXTERN rtems_unsigned32Shm_Active_node;461 462 SHM_EXTERN rtems_unsigned32Shm_Maximum_nodes;463 SHM_EXTERN rtems_unsigned32Shm_Maximum_envelopes;464 465 SHM_EXTERN rtems_unsigned32Shm_Locked_queue_End_of_list;466 SHM_EXTERN rtems_unsigned32Shm_Locked_queue_Not_on_list;458 SHM_EXTERN uint32_t Shm_Pending_initialization; 459 SHM_EXTERN uint32_t Shm_Initialization_complete; 460 SHM_EXTERN uint32_t Shm_Active_node; 461 462 SHM_EXTERN uint32_t Shm_Maximum_nodes; 463 SHM_EXTERN uint32_t Shm_Maximum_envelopes; 464 465 SHM_EXTERN uint32_t Shm_Locked_queue_End_of_list; 466 SHM_EXTERN uint32_t Shm_Locked_queue_Not_on_list; 467 467 468 468 /* functions */ … … 473 473 Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * ); 474 474 void Shm_Locked_queue_Initialize( 475 Shm_Locked_queue_Control *, rtems_unsigned32);475 Shm_Locked_queue_Control *, uint32_t ); 476 476 /* Shm_Initialize_lock is CPU dependent */ 477 477 /* Shm_Lock is CPU dependent */ … … 481 481 void Init_env_pool(); 482 482 void Shm_Print_statistics( void ); 483 void MPCI_Fatal( Internal_errors_Source, boolean, rtems_unsigned32);484 rtems_task Shm_Cause_interrupt( rtems_unsigned32);483 void MPCI_Fatal( Internal_errors_Source, boolean, uint32_t ); 484 rtems_task Shm_Cause_interrupt( uint32_t ); 485 485 void Shm_Poll(); 486 486 void Shm_setclockvec(); … … 491 491 /* target specific routines */ 492 492 void *Shm_Convert_address( void * ); 493 void Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );493 void Shm_Get_configuration( uint32_t , shm_config_table ** ); 494 494 void Shm_isr(); 495 495 void Shm_setvec( void ); … … 515 515 516 516 rtems_mpci_entry Shm_Send_packet( 517 rtems_unsigned32,517 uint32_t , 518 518 rtems_packet_prefix * 519 519 );
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