Changeset edf846e in rtems


Ignore:
Timestamp:
May 20, 2010, 2:23:13 PM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.10, 4.11, master
Children:
c3dd440
Parents:
ef6f1d0c
Message:

2010-05-20 Sebastian Huber <sebastian.huber@…>

  • include/lpc24xx.h, misc/dma-copy.c, misc/dma.c, misc/system-clocks.c, ssp/ssp.c, startup/bspstarthooks.c: Removed superfluous macros.
Location:
c/src/lib/libbsp/arm/lpc24xx
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    ref6f1d0c redf846e  
    11691169/* Register Fields */
    11701170
     1171#define GET_FIELD( val, mask, shift) \
     1172  (((val) & (mask)) >> (shift))
     1173
     1174#define SET_FIELD( val, field, mask, shift) \
     1175  (((val) & ~(mask)) | (((field) << (shift)) & (mask)))
     1176
    11711177/* CLKSRCSEL */
    11721178
  • c/src/lib/libbsp/arm/lpc24xx/misc/dma-copy.c

    ref6f1d0c redf846e  
    3939
    4040  /* Check channel 0 */
    41   if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
     41  if ((tc & GPDMA_STATUS_CH_0) != 0) {
    4242    rtems_semaphore_release(lpc24xx_dma_sema_table [0]);
    4343  }
    44   lpc24xx_dma_status_table [0] = IS_FLAG_CLEARED(err, GPDMA_STATUS_CH_0);
     44  lpc24xx_dma_status_table [0] = (err & GPDMA_STATUS_CH_0) == 0;
    4545
    4646  /* Check channel 1 */
    47   if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
     47  if ((tc & GPDMA_STATUS_CH_1) != 0) {
    4848    rtems_semaphore_release(lpc24xx_dma_sema_table [1]);
    4949  }
    50   lpc24xx_dma_status_table [1] = IS_FLAG_CLEARED(err, GPDMA_STATUS_CH_1);
     50  lpc24xx_dma_status_table [1] = (err & GPDMA_STATUS_CH_1) == 0;
    5151}
    5252
  • c/src/lib/libbsp/arm/lpc24xx/misc/dma.c

    ref6f1d0c redf846e  
    8686    if (!force) {
    8787      /* Halt */
    88       ch->cfg = SET_FLAG(cfg, GPDMA_CH_CFG_HALT);
     88      ch->cfg |= GPDMA_CH_CFG_HALT;
    8989
    9090      /* Wait for inactive */
    9191      do {
    9292        cfg = ch->cfg;
    93       } while (IS_FLAG_SET(cfg, GPDMA_CH_CFG_ACTIVE));
     93      } while ((cfg & GPDMA_CH_CFG_ACTIVE) != 0);
    9494    }
    9595
    9696    /* Disable */
    97     ch->cfg = CLEAR_FLAG(cfg, GPDMA_CH_CFG_EN);
     97    ch->cfg &= ~GPDMA_CH_CFG_EN;
    9898  }
    9999}
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    ref6f1d0c redf846e  
    9494
    9595  /* Get PLL output frequency */
    96   if (IS_FLAG_SET(PLLSTAT, PLLSTAT_PLLC)) {
     96  if ((PLLSTAT & PLLSTAT_PLLC) != 0) {
    9797    uint32_t pllcfg = PLLCFG;
    9898    unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1;
  • c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c

    ref6f1d0c redf846e  
    8888  uint32_t icr = 0;
    8989
    90   if (IS_FLAG_SET(mis, SSP_MIS_RORRIS)) {
     90  if ((mis & SSP_MIS_RORRIS) != 0) {
    9191    /* TODO */
    9292    printk("%s: Receiver overrun!\n", __func__);
     
    106106
    107107  /* Return if we are not in a transfer status */
    108   if (IS_FLAG_CLEARED(status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
     108  if ((status & LPC24XX_SSP_DMA_TRANSFER_FLAG) == 0) {
    109109    return;
    110110  }
     
    122122    switch (status) {
    123123      case LPC24XX_SSP_DMA_WAIT:
    124         if (ARE_FLAGS_SET(tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
     124        if ((tc & (GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) != 0) {
    125125          status = LPC24XX_SSP_DMA_DONE;
    126         } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
     126        } else if ((tc & GPDMA_STATUS_CH_0) != 0) {
    127127          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1;
    128         } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
     128        } else if ((tc & GPDMA_STATUS_CH_1) != 0) {
    129129          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0;
    130130        }
    131131        break;
    132132      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0:
    133         if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
     133        if ((tc & GPDMA_STATUS_CH_1) != 0) {
    134134          status = LPC24XX_SSP_DMA_ERROR;
    135         } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
     135        } else if ((tc & GPDMA_STATUS_CH_0) != 0) {
    136136          status = LPC24XX_SSP_DMA_DONE;
    137137        }
    138138        break;
    139139      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1:
    140         if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
     140        if ((tc & GPDMA_STATUS_CH_0) != 0) {
    141141          status = LPC24XX_SSP_DMA_ERROR;
    142         } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
     142        } else if ((tc & GPDMA_STATUS_CH_1) != 0) {
    143143          status = LPC24XX_SSP_DMA_DONE;
    144144        }
     
    364364  e->idle_char = mode->idle_char;
    365365
    366   while (IS_FLAG_CLEARED(regs->sr, SSP_SR_TFE)) {
     366  while ((regs->sr & SSP_SR_TFE) == 0) {
    367367    /* Wait */
    368368  }
     
    427427
    428428    /* Write */
    429     if (IS_FLAG_SET(sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
     429    if ((sr & SSP_SR_TNF) != 0 && m < LPC24XX_SSP_FIFO_SIZE) {
    430430      regs->dr = *out;
    431431      ++w;
     
    434434
    435435    /* Read */
    436     if (IS_FLAG_SET(sr, SSP_SR_RNE)) {
     436    if ((sr & SSP_SR_RNE) != 0) {
    437437      *in = (unsigned char) regs->dr;
    438438      ++r;
     
    449449    do {
    450450      sr = regs->sr;
    451     } while (IS_FLAG_CLEARED(sr, SSP_SR_RNE));
     451    } while ((sr & SSP_SR_RNE) == 0);
    452452
    453453    /* Read */
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c

    ref6f1d0c redf846e  
    144144  #ifdef LPC24XX_EMC_INIT
    145145    /* Use normal memory map */
    146     EMC_CTRL = CLEAR_FLAG(EMC_CTRL, 0x2);
     146    EMC_CTRL &= ~0x2;
    147147  #endif
    148148
    149149  #ifdef LPC24XX_EMC_MICRON
    150150    /* Check if we need to initialize it */
    151     if (IS_FLAG_CLEARED(EMC_DYN_CFG0, 0x00080000)) {
     151    if ((EMC_DYN_CFG0 & 0x00080000) == 0) {
    152152      /*
    153153       * The buffer enable bit is not set.  Now we assume that the controller
     
    279279  uint32_t clksrcsel = SET_CLKSRCSEL_CLKSRC(0, clksrc);
    280280  uint32_t cclkcfg = SET_CCLKCFG_CCLKSEL(0, cclksel | 1);
    281   bool pll_enabled = IS_FLAG_SET(pllstat, PLLSTAT_PLLE);
     281  bool pll_enabled = (pllstat & PLLSTAT_PLLE) != 0;
    282282
    283283  /* Disconnect PLL if necessary */
    284   if (IS_FLAG_SET(pllstat, PLLSTAT_PLLC)) {
     284  if ((pllstat & PLLSTAT_PLLC) != 0) {
    285285    if (pll_enabled) {
    286286      /* Check if we run already with the desired settings */
     
    313313
    314314  /* Wait for lock */
    315   while (IS_FLAG_CLEARED(PLLSTAT, PLLSTAT_PLOCK)) {
     315  while ((PLLSTAT & PLLSTAT_PLOCK) == 0) {
    316316    /* Wait */
    317317  }
     
    327327{
    328328  /* Enable main oscillator */
    329   if (IS_FLAG_CLEARED(SCS, 0x40)) {
    330     SCS = SET_FLAG(SCS, 0x20);
    331     while (IS_FLAG_CLEARED(SCS, 0x40)) {
     329  if ((SCS & 0x40) == 0) {
     330    SCS |= 0x20;
     331    while ((SCS & 0x40) == 0) {
    332332      /* Wait */
    333333    }
     
    384384
    385385  /* Enable fast IO for ports 0 and 1 */
    386   SCS = SET_FLAG(SCS, 0x1);
     386  SCS |= 0x1;
    387387
    388388  /* Set fast IO */
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