Changeset ec821af in rtems

Timestamp:

Jul 18, 2003, 5:24:48 PM (18 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

1ede24c

Parents:

7b59de1c

Message:

2003-07-18 Till Straumann <strauman@…>

PR 288/rtems

• irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly maintained and any BSP which does not do so will trip a panic in the shared code.

Location:

c/src/lib/libbsp/powerpc/shared

Files:

• ChangeLog (modified) (1 diff)
• irq/irq_asm.S (modified) (5 diffs)
• startup/bspstart.c (modified) (4 diffs)

c/src/lib/libbsp/powerpc/shared/ChangeLog

@@ +1 @@
+2003-07-18      Till Straumann <strauman@slac.stanford.edu>
+
+        PR 288/rtems
+        * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
+        maintained and any BSP which does not do so will trip a panic in the
+        shared code.
+
 2003-07-18      Till Straumann <strauman@slac.stanford.edu>
 

c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S

@@ -10 +10 @@
  *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
  *
+ *  Till Straumann <strauman@slac.stanford.edu>, 2003/7:
+ *    - store isr nesting level in _ISR_Nest_level rather than
+ *      SPRG0 - RTEMS relies on that variable.
  *
  * $Id$
@@ -141 +144 @@
          */
         addis r15,0, _Thread_Dispatch_disable_level@ha
+#if BROKEN_ISR_NEST_LEVEL
         /*
          * Get current nesting level in R3
          */
         mfspr   r3, SPRG0
+#else
+        /*
+         * Retrieve current nesting level from _ISR_Nest_level
+         */
+        lis             r7, _ISR_Nest_level@ha
+        lwz             r3, _ISR_Nest_level@l(r7)
+#endif
         /*
          * Check if stack switch is necessary
@@ -161 +172 @@
          */
         lwz     r6,_Thread_Dispatch_disable_level@l(r15)
-        /*
-         * store new nesting level in SPRG0
+#if BROKEN_ISR_NEST_LEVEL
+        /*
+         * Store new nesting level in SPRG0
          */
         mtspr   SPRG0, r3
+#else
+        /* store new nesting level in _ISR_Nest_level */
+        stw             r3, _ISR_Nest_level@l(r7)
+#endif
         
         addi    r6, r6, 1
@@ -188 +204 @@
          * then _Thread_Dispatch_disable_level > 1
          */
+#if BROKEN_ISR_NEST_LEVEL
         mfspr   r4, SPRG0
+#else
+        lis             r7, _ISR_Nest_level@ha
+        lwz             r4, _ISR_Nest_level@l(r7)
+#endif
         /*
          * start decrementing _Thread_Dispatch_disable_level
@@ -195 +216 @@
         addi    r4, r4, -1      /* Continue decrementing nesting level */
         addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
+#if BROKEN_ISR_NEST_LEVEL
         mtspr   SPRG0, r4       /* End decrementing nesting level */
+#else
+        stw             r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
+#endif
         stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
         cmpwi   r3, 0

c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

@@ -46 +46 @@
 extern void                     BSP_vme_config();
 
-SPR_RW(SPR0)
-SPR_RW(SPR1)
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
 
 /*
@@ -180 +180 @@
   unsigned l2cr;
   register unsigned char* intrStack;
-  register unsigned int intrNestingLevel = 0;
   unsigned char *work_space_start;
   ppc_cpu_id_t myCpu;
@@ -220 +219 @@
   /*
    * Initialize the interrupt related settings
-   * SPRG0 = interrupt nesting level count
    * SPRG1 = software managed IRQ stack
    *
@@ -234 +232 @@
   *((unsigned32 *)intrStack) = 0;
 
-  _write_SPR1((unsigned int)intrStack);
-  _write_SPR0(intrNestingLevel);
+  _write_SPRG1((unsigned int)intrStack);
+
+  /* signal them that we have fixed PR288 - eventually, this should go away */
+  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
+
   /*
    * Initialize default raw exception hanlders. See vectors/vectors_init.c