Changeset ebf0f8f in rtems
- Timestamp:
- 08/16/19 19:14:33 (5 years ago)
- Branches:
- 5, master
- Children:
- e2255453
- Parents:
- 5e7b3c65
- git-author:
- Kinsey Moore <kinsey.moore@…> (08/16/19 19:14:33)
- git-committer:
- Joel Sherrill <joel@…> (01/17/20 22:17:42)
- Location:
- bsps/arm
- Files:
-
- 1 added
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
bsps/arm/include/bsp/arm-gic-irq.h
r5e7b3c65 rebf0f8f 86 86 } arm_gic_irq_software_irq_target_filter; 87 87 88 void arm_gic_trigger_sgi( 89 rtems_vector_number vector, 90 arm_gic_irq_software_irq_target_filter filter, 91 uint8_t targets 92 ); 93 88 94 static inline rtems_status_code arm_gic_irq_generate_software_irq( 89 95 rtems_vector_number vector, … … 95 101 96 102 if (vector <= ARM_GIC_IRQ_SGI_15) { 97 volatile gic_dist *dist = ARM_GIC_DIST; 98 99 dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) 100 | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) 101 #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 102 | GIC_DIST_ICDSGIR_NSATT 103 #endif 104 | GIC_DIST_ICDSGIR_SGIINTID(vector); 103 arm_gic_trigger_sgi(vector, filter, targets); 105 104 } else { 106 105 sc = RTEMS_INVALID_ID; -
bsps/arm/include/bsp/arm-gic-regs.h
r5e7b3c65 rebf0f8f 87 87 88 88 typedef struct { 89 /* GICD_CTLR */ 89 90 uint32_t icddcr; 91 /* GICv3 only */ 92 #define GIC_DIST_ICDDCR_RWP BSP_BIT32(31) 93 #define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7) 94 #define GIC_DIST_ICDDCR_DS BSP_BIT32(6) 95 #define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5) 96 #define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4) 97 #define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2) 98 #define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1) 99 #define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0) 100 /* GICv1/GICv2 */ 90 101 #define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1) 91 102 #define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) … … 127 138 uint32_t reserved_900[192]; 128 139 uint32_t icdicfr[64]; 129 uint32_t reserved_d00[128]; 140 /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */ 141 uint32_t icdigmr[32]; 142 uint32_t reserved_d80[96]; 130 143 uint32_t icdsgir; 131 144 #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) … … 141 154 } gic_dist; 142 155 156 /* GICv3 only */ 157 typedef struct { 158 /* GICR_CTLR */ 159 uint32_t icrrcr; 160 #define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31) 161 #define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26) 162 #define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25) 163 #define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24) 164 #define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4) 165 #define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0) 166 uint32_t icriidr; 167 uint64_t icrtyper; 168 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63) 169 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63) 170 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63) 171 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25) 172 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25) 173 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25) 174 #define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23) 175 #define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23) 176 #define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23) 177 #define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5) 178 #define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4) 179 #define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3) 180 #define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1) 181 #define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0) 182 uint32_t unused_10; 183 uint32_t icrwaker; 184 #define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2) 185 #define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1) 186 } gic_redist; 187 188 /* GICv3 only */ 189 typedef struct { 190 uint32_t reserved_0_80[32]; 191 /* GICR_IGROUPR0 */ 192 uint32_t icspigrpr[32]; 193 /* GICR_ISENABLER0 */ 194 uint32_t icspiser[32]; 195 /* GICR_ICENABLER0 */ 196 uint32_t icspicer[32]; 197 /* GICR_ISPENDR0 */ 198 uint32_t icspispendr[32]; 199 /* GICR_ICPENDR0 */ 200 uint32_t icspicpendr[32]; 201 /* GICR_ISACTIVER0 */ 202 uint32_t icspisar[32]; 203 /* GICR_ICACTIVER0 */ 204 uint32_t icspicar[32]; 205 /* GICR_IPRIORITYR */ 206 uint8_t icspiprior[32]; 207 uint32_t reserved_420_bfc[504]; 208 /* GICR_ICFGR0 */ 209 uint32_t icspicfgr0; 210 /* GICR_ICFGR1 */ 211 uint32_t icspicfgr1; 212 uint32_t reserved_c08_cfc[62]; 213 /* GICR_IGRPMODR0 */ 214 uint32_t icspigrpmodr[64]; 215 } gic_sgi_ppi; 216 143 217 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ -
bsps/arm/shared/irq/irq-gic.c
r5e7b3c65 rebf0f8f 263 263 _Processor_mask_From_uint32_t(affinity, targets, 0); 264 264 } 265 266 void arm_gic_trigger_sgi( 267 rtems_vector_number vector, 268 arm_gic_irq_software_irq_target_filter filter, 269 uint8_t targets 270 ) 271 { 272 volatile gic_dist *dist = ARM_GIC_DIST; 273 274 dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) 275 | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) 276 #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 277 | GIC_DIST_ICDSGIR_NSATT 278 #endif 279 | GIC_DIST_ICDSGIR_SGIINTID(vector); 280 }
Note: See TracChangeset
for help on using the changeset viewer.