Changeset ea3eadf in rtems-central

Timestamp:

03/15/23 07:39:35 (7 months ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

master

Children:

77414f1

Parents:

7c0ddcc

git-author:

Sebastian Huber <sebastian.huber@…> (03/15/23 07:39:35)

git-committer:

Sebastian Huber <sebastian.huber@…> (03/15/23 07:47:37)

Message:

interface: Improve register bit field macros

Update #4828.

Location:

rtemsspec

Files:

• interface.py (modified) (1 diff)
• tests/test_interface.py (modified) (6 diffs)

rtemsspec/interface.py

@@ -578 +578 @@
             end = start + width
             sfx = "ULL" if end > 32 else "U"
-            define = f"#define {prefix.upper()}{bit['name'].upper()}"
+            base = f"{prefix.upper()}{bit['name'].upper()}"
             if index != 0:
                 lines.append("")
             if width == 1:
                 val = 1 << start
-                lines.append(f"{define} {val:#x}{sfx}")
+                lines.append(f"#define {base} {val:#x}{sfx}")
             else:
                 mask = ((1 << width) - 1) << start
-                get = (1 << width) - 1
                 lines.extend([
-                    f"{define}_SHIFT {start}", f"{define}_MASK {mask:#x}{sfx}",
-                    f"{define}_GET( _reg ) \\",
-                    f"  ( ( ( _reg ) >> {start} ) & {get:#x}{sfx} )",
-                    f"{define}( _val ) ( ( _val ) << {start} )"
+                    f"#define {base}_SHIFT {start}",
+                    f"#define {base}_MASK {mask:#x}{sfx}",
+                    f"#define {base}_GET( _reg ) \\",
+                    f"  ( ( ( _reg ) & {base}_MASK ) >> {base}_SHIFT )",
+                    f"#define {base}( _val ) \\",
+                    f"  ( ( _val ) << {base}_SHIFT )"
                 ])
         return lines

rtemsspec/tests/test_interface.py

@@ -266 +266 @@
 #define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU
 #define IRQAMP_ITCNT_TCNT_GET( _reg ) \\
-  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
-#define IRQAMP_ITCNT_TCNT( _val ) ( ( _val ) << 0 )
+  ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> IRQAMP_ITCNT_TCNT_SHIFT )
+#define IRQAMP_ITCNT_TCNT( _val ) \\
+  ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT )
 
 /** @} */
@@ -283 +284 @@
 #define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U
 #define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \\
-  ( ( ( _reg ) >> 27 ) & 0x1fU )
-#define IRQAMP_ITSTMPC_TSTAMP( _val ) ( ( _val ) << 27 )
+  ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> IRQAMP_ITSTMPC_TSTAMP_SHIFT )
+#define IRQAMP_ITSTMPC_TSTAMP( _val ) \\
+  ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT )
 
 #define IRQAMP_ITSTMPC_S1 0x4000000U
@@ -295 +297 @@
 #define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU
 #define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \\
-  ( ( ( _reg ) >> 0 ) & 0x1fU )
-#define IRQAMP_ITSTMPC_TSISEL( _val ) ( ( _val ) << 0 )
+  ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> IRQAMP_ITSTMPC_TSISEL_SHIFT )
+#define IRQAMP_ITSTMPC_TSISEL( _val ) \\
+  ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT )
 
 /** @} */
@@ -312 +315 @@
 #define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU
 #define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \\
-  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
-#define IRQAMP_ITSTMPAS_TASSERTION( _val ) ( ( _val ) << 0 )
+  ( ( ( _reg ) & IRQAMP_ITSTMPAS_TASSERTION_MASK ) >> IRQAMP_ITSTMPAS_TASSERTION_SHIFT )
+#define IRQAMP_ITSTMPAS_TASSERTION( _val ) \\
+  ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT )
 
 /** @} */
@@ -329 +333 @@
 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU
 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \\
-  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
-#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) ( ( _val ) << 0 )
+  ( ( ( _reg ) & IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) >> IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT )
+#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \\
+  ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT )
 
 /** @} */
@@ -383 +388 @@
 #define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU
 #define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \\
-  ( ( ( _reg ) >> 1 ) & 0x7fffU )
-#define IRQAMP_ILEVEL_IL_15_1( _val ) ( ( _val ) << 1 )
+  ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> IRQAMP_ILEVEL_IL_15_1_SHIFT )
+#define IRQAMP_ILEVEL_IL_15_1( _val ) \\
+  ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT )
 
 /** @} */