Changeset e9d98071 in rtems for c/src/lib/libbsp/arm/xilinx-zynq/configure.ac

Timestamp:

05/22/14 06:21:38 (8 years ago)

Author:

Chris Johns <chrisj@…>

Branches:

4.11, 5, master

Children:

3cbedb1

Parents:

18bd35bc

git-author:

Chris Johns <chrisj@…> (05/22/14 06:21:38)

git-committer:

Chris Johns <chrisj@…> (05/22/14 06:53:25)

Message:

bsp/zynq: Add BSP_ZYNQ_RAM_LENGTH to allow a user to override the RAM length.

The Zynq BSPs can be used with varations of hardware such as memory size.
This option lets you set a length.

File:

• c/src/lib/libbsp/arm/xilinx-zynq/configure.ac (modified) (5 diffs)

c/src/lib/libbsp/arm/xilinx-zynq/configure.ac

@@ -56 +56 @@
 # Zynq Memory map can be controlled from the configure command line. Use ...
 #
-#   ..../configure --target=arm-rtems4.11 ... ZYNQ_RAM_LENGTH=256M
+#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M
 #
+RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M])
+RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M])
+RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M])
+RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
+RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
+RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
+
 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu],
       [ZYNQ_RAM_ORIGIN="0x00000000"
-       ZYNQ_RAM_LENGTH="256M"
        ZYNQ_RAM_MMU="0x0fffc000"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}"
-       ZYNQ_RAM_LENGTH_AVAILABLE="${ZYNQ_RAM_LENGTH} - 16k"
+       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
@@ -72 +78 @@
 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
       [ZYNQ_RAM_ORIGIN="0x00100000"
-       ZYNQ_RAM_LENGTH="1024M"
        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
-       ZYNQ_RAM_LENGTH_AVAILABLE="${ZYNQ_RAM_LENGTH} - 1M - 16k"
+       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
@@ -84 +89 @@
 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
       [ZYNQ_RAM_ORIGIN="0x00400000"
-       ZYNQ_RAM_LENGTH="1024M"
        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
-       ZYNQ_RAM_LENGTH_AVAILABLE="${ZYNQ_RAM_LENGTH} - 4M - 16k"
+       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
@@ -96 +100 @@
 AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard],
       [ZYNQ_RAM_ORIGIN="0x00100000"
-       ZYNQ_RAM_LENGTH="512M"
        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
-       ZYNQ_RAM_LENGTH_AVAILABLE="${ZYNQ_RAM_LENGTH} - 1M - 16k"
+       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
@@ -113 +116 @@
 ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}])
 ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
-ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${ZYNQ_RAM_LENGTH}])
+ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])
 ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}])
 ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}])