Changeset e96feeb in rtems


Ignore:
Timestamp:
Oct 27, 2015, 9:20:02 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
53c99b8
Parents:
69be1a22
git-author:
Sebastian Huber <sebastian.huber@…> (10/27/15 09:20:02)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/28/15 12:04:19)
Message:

powerpc: Add FSL cache defines

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    r69be1a22 re96feeb  
    551551#define FSL_EIS_L1CFG1 516
    552552#define FSL_EIS_L1CSR0 1010
     553#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62))
    553554#define FSL_EIS_L1CSR1 1011
     555#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62))
     556
     557/* Freescale Book E Implementation Standards (EIS): L2 Cache */
     558
     559#define FSL_EIS_L2CFG0 519
     560#define FSL_EIS_L2CSR0 1017
     561#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42))
     562#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52))
     563#define FSL_EIS_L2CSR1 1018
    554564
    555565/* Freescale Book E Implementation Standards (EIS): Timer */
Note: See TracChangeset for help on using the changeset viewer.