Changeset e96a950b in rtems
- Timestamp:
- 03/31/04 02:00:03 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 35f97010
- Parents:
- 8bc4430b
- Location:
- c/src/lib/libcpu/sh
- Files:
-
- 20 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/sh/ChangeLog
r8bc4430b re96a950b 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * sh7032/clock/ckinit.c, sh7032/delay/delay.c, 4 sh7032/include/ispsh7032.h, sh7032/sci/sci.c, 5 sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/clock/ckinit.c, 6 sh7045/include/ispsh7045.h, sh7045/sci/sci.c, 7 sh7045/sci/sci_termios.c, sh7045/score/cpu_asm.c, 8 sh7045/timer/timer.c, sh7750/clock/ckinit.c, 9 sh7750/include/rtems/score/ispsh7750.h, sh7750/include/sh/sh4uart.h, 10 sh7750/sci/sh4uart.c, sh7750/score/cpu_asm.c, 11 sh7750/score/ispsh7750.c, sh7750/timer/timer.c: Convert to using c99 12 fixed size types. 13 1 14 2004-03-26 Ralf Corsepius <ralf_corsepius@rtems.org> 2 15 -
c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
r8bc4430b re96a950b 104 104 double fclicks_per_tick = 105 105 ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ; 106 return (u nsigned32) fclicks_per_tick ;106 return (uint32_t ) fclicks_per_tick ; 107 107 #endif 108 108 } … … 120 120 */ 121 121 122 volatile rtems_unsigned32Clock_driver_ticks;122 volatile uint32_t Clock_driver_ticks; 123 123 124 124 static void Clock_exit( void ); … … 133 133 */ 134 134 135 rtems_unsigned32Clock_isrs; /* ISRs until next tick */136 static rtems_unsigned32Clock_isrs_const; /* only calculated once */135 uint32_t Clock_isrs; /* ISRs until next tick */ 136 static uint32_t Clock_isrs_const; /* only calculated once */ 137 137 138 138 /* … … 165 165 * perform any timer dependent tasks 166 166 */ 167 u nsigned8temp;167 uint8_t temp; 168 168 169 169 /* reset the flags of the status register */ … … 195 195 ) 196 196 { 197 u nsigned8temp8 = 0;198 u nsigned32microseconds_per_tick ;199 u nsigned32cclicks_per_tick ;200 u nsigned16Clock_limit ;197 uint8_t temp8 = 0; 198 uint32_t microseconds_per_tick ; 199 uint32_t cclicks_per_tick ; 200 uint16_t Clock_limit ; 201 201 202 202 /* … … 281 281 void Clock_exit( void ) 282 282 { 283 u nsigned8temp8 = 0;283 uint8_t temp8 = 0; 284 284 285 285 /* turn off the timer interrupts */ … … 330 330 ) 331 331 { 332 rtems_unsigned32isrlevel;332 uint32_t isrlevel; 333 333 rtems_libio_ioctl_args_t *args = pargp; 334 334 -
c/src/lib/libcpu/sh/sh7032/delay/delay.c
r8bc4430b re96a950b 37 37 */ 38 38 39 void CPU_delay( u nsigned32microseconds )39 void CPU_delay( uint32_t microseconds ) 40 40 { 41 register u nsigned32clicks_per_usec =41 register uint32_t clicks_per_usec = 42 42 rtems_cpu_configuration_get_clicks_per_second() / 1000000 ; 43 register u nsigned32_delay =43 register uint32_t _delay = 44 44 (microseconds) * (clicks_per_usec); 45 45 asm volatile ( -
c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h
r8bc4430b re96a950b 32 32 #include <rtems/score/types.h> 33 33 34 extern void __ISR_Handler( u nsigned32vector );34 extern void __ISR_Handler( uint32_t vector ); 35 35 36 36 -
c/src/lib/libcpu/sh/sh7032/sci/sci.c
r8bc4430b re96a950b 45 45 struct scidev_t { 46 46 char * name ; 47 u nsigned32addr ;47 uint32_t addr ; 48 48 rtems_device_minor_number minor ; 49 49 unsigned short opened ; … … 66 66 tcflag_t c_cflag ) 67 67 { 68 u nsigned8smr ;69 u nsigned8brr ;68 uint8_t smr ; 69 uint8_t brr ; 70 70 71 71 if ( c_cflag & CBAUD ) … … 109 109 rtems_device_minor_number minor ) 110 110 { 111 u nsigned16temp16 ;111 uint16_t temp16 ; 112 112 113 113 /* Pin function controller initialisation for asynchronous mode */ … … 147 147 { 148 148 struct scidev_t *scidev = &sci_device[minor] ; 149 signed8ssr ;149 int8_t ssr ; 150 150 151 151 while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE )) … … 221 221 void * arg ) 222 222 { 223 u nsigned8temp8;223 uint8_t temp8; 224 224 225 225 /* check for valid minor number */ -
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
r8bc4430b re96a950b 69 69 unsigned int prio ) 70 70 { 71 u nsigned32shiftcount;72 u nsigned32prioreg;73 u nsigned16temp16;74 u nsigned32level;71 uint32_t shiftcount; 72 uint32_t prioreg; 73 uint16_t temp16; 74 uint32_t level; 75 75 76 76 /* … … 256 256 */ 257 257 258 void __ISR_Handler( u nsigned32vector)259 { 260 register u nsigned32level;258 void __ISR_Handler( uint32_t vector) 259 { 260 register uint32_t level; 261 261 262 262 _CPU_ISR_Disable( level ); -
c/src/lib/libcpu/sh/sh7032/timer/timer.c
r8bc4430b re96a950b 65 65 rtems_isr timerisr(); 66 66 67 static rtems_unsigned32Timer_interrupts;67 static uint32_t Timer_interrupts; 68 68 69 69 rtems_boolean Timer_driver_Find_average_overhead; 70 70 71 static rtems_unsigned32Timer_HZ ;71 static uint32_t Timer_HZ ; 72 72 73 73 void Timer_initialize( void ) 74 74 { 75 rtems_unsigned8temp8;76 rtems_unsigned16temp16;77 rtems_unsigned32level;75 uint8_t temp8; 76 uint16_t temp16; 77 uint32_t level; 78 78 rtems_isr *ignored; 79 79 … … 150 150 int Read_timer( void ) 151 151 { 152 rtems_unsigned32cclicks;153 rtems_unsigned32total ;152 uint32_t cclicks; 153 uint32_t total ; 154 154 /* 155 155 * Read the timer and see how many clicks it has been since we started. … … 202 202 void timerisr( void ) 203 203 { 204 u nsigned8temp8;204 uint8_t temp8; 205 205 206 206 /* reset the flags of the status register */ -
c/src/lib/libcpu/sh/sh7045/clock/ckinit.c
r8bc4430b re96a950b 72 72 */ 73 73 74 volatile rtems_unsigned32Clock_driver_ticks;74 volatile uint32_t Clock_driver_ticks; 75 75 76 76 static void Clock_exit( void ); 77 77 static rtems_isr Clock_isr( rtems_vector_number vector ); 78 static rtems_unsigned32Clock_MHZ ;78 static uint32_t Clock_MHZ ; 79 79 80 80 /* … … 86 86 */ 87 87 88 rtems_unsigned32Clock_isrs; /* ISRs until next tick */89 static rtems_unsigned32Clock_isrs_const; /* only calculated once */88 uint32_t Clock_isrs; /* ISRs until next tick */ 89 static uint32_t Clock_isrs_const; /* only calculated once */ 90 90 91 91 /* … … 119 119 * perform any timer dependent tasks 120 120 */ 121 u nsigned8temp;121 uint8_t temp; 122 122 123 123 /* reset the flags of the status register */ … … 149 149 ) 150 150 { 151 u nsigned8temp8 = 0;152 u nsigned32factor = 1000000;151 uint8_t temp8 = 0; 152 uint32_t factor = 1000000; 153 153 154 154 … … 223 223 void Clock_exit( void ) 224 224 { 225 u nsigned8temp8 = 0;225 uint8_t temp8 = 0; 226 226 227 227 /* turn off the timer interrupts */ … … 272 272 ) 273 273 { 274 rtems_unsigned32isrlevel;274 uint32_t isrlevel; 275 275 rtems_libio_ioctl_args_t *args = pargp; 276 276 -
c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h
r8bc4430b re96a950b 44 44 #include <rtems/score/types.h> 45 45 46 extern void __ISR_Handler( u nsigned32vector );46 extern void __ISR_Handler( uint32_t vector ); 47 47 48 48 -
c/src/lib/libcpu/sh/sh7045/sci/sci.c
r8bc4430b re96a950b 79 79 struct scidev_t { 80 80 char * name ; 81 u nsigned32addr ;81 uint32_t addr ; 82 82 rtems_device_minor_number minor ; 83 83 unsigned short opened ; … … 105 105 tcflag_t c_cflag ) 106 106 { 107 u nsigned8smr ;108 u nsigned8brr ;107 uint8_t smr ; 108 uint8_t brr ; 109 109 110 110 if ( c_cflag & CBAUD ) … … 151 151 rtems_boolean wrtSCI0(unsigned char ch) 152 152 { 153 u nsigned8temp;153 uint8_t temp; 154 154 rtems_boolean result=FALSE; 155 155 … … 167 167 rtems_boolean wrtSCI1(unsigned char ch) 168 168 { 169 u nsigned8temp;169 uint8_t temp; 170 170 rtems_boolean result=FALSE; 171 171 … … 204 204 rtems_boolean rdSCI0(unsigned char *ch) 205 205 { 206 u nsigned8temp;206 uint8_t temp; 207 207 rtems_boolean result=FALSE; 208 208 … … 228 228 rtems_boolean rdSCI1(unsigned char *ch) 229 229 { 230 u nsigned8temp;230 uint8_t temp; 231 231 rtems_boolean result=FALSE; 232 232 … … 340 340 void * arg ) 341 341 { 342 u nsigned8temp8;343 u nsigned16temp16;342 uint8_t temp8; 343 uint16_t temp16; 344 344 345 345 unsigned a ; -
c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c
r8bc4430b re96a950b 72 72 ) 73 73 { 74 u nsigned8smr ;75 u nsigned8brr ;74 uint8_t smr ; 75 uint8_t brr ; 76 76 int a; 77 77 … … 136 136 if(Console_Port_Tbl[minor].ulIntVector == vector) 137 137 { 138 u nsigned8temp8;138 uint8_t temp8; 139 139 140 140 /* … … 194 194 void sh_sci_init(int minor) 195 195 { 196 u nsigned16temp16;196 uint16_t temp16; 197 197 198 198 /* … … 286 286 void *arg ) 287 287 { 288 u nsigned8temp8;288 uint8_t temp8; 289 289 unsigned int a ; 290 290 … … 440 440 int sh_sci_inbyte_nonblocking_polled(int minor) 441 441 { 442 u nsigned8inbyte;442 uint8_t inbyte; 443 443 444 444 /* -
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
r8bc4430b re96a950b 68 68 unsigned int prio ) 69 69 { 70 u nsigned32shiftcount;71 u nsigned32prioreg;72 u nsigned16temp16;73 u nsigned32level;70 uint32_t shiftcount; 71 uint32_t prioreg; 72 uint16_t temp16; 73 uint32_t level; 74 74 75 75 /* … … 258 258 */ 259 259 260 void __ISR_Handler( u nsigned32vector)261 { 262 register u nsigned32level;260 void __ISR_Handler( uint32_t vector) 261 { 262 register uint32_t level; 263 263 264 264 _CPU_ISR_Disable( level ); -
c/src/lib/libcpu/sh/sh7045/timer/timer.c
r8bc4430b re96a950b 56 56 rtems_isr timerisr(); 57 57 58 static rtems_unsigned32Timer_interrupts;58 static uint32_t Timer_interrupts; 59 59 60 60 rtems_boolean Timer_driver_Find_average_overhead; 61 61 62 static rtems_unsigned32Timer_MHZ ;62 static uint32_t Timer_MHZ ; 63 63 64 64 void Timer_initialize( void ) 65 65 { 66 rtems_unsigned8temp8;67 rtems_unsigned16temp16;68 rtems_unsigned32level;66 uint8_t temp8; 67 uint16_t temp16; 68 uint32_t level; 69 69 rtems_isr *ignored; 70 70 … … 146 146 int Read_timer( void ) 147 147 { 148 rtems_unsigned32clicks;149 rtems_unsigned32total ;148 uint32_t clicks; 149 uint32_t total ; 150 150 /* 151 151 * Read the timer and see how many clicks it has been since we started. … … 198 198 void timerisr( void ) 199 199 { 200 u nsigned8temp8;200 uint8_t temp8; 201 201 202 202 /* reset the flags of the status register */ -
c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
r8bc4430b re96a950b 45 45 */ 46 46 47 volatile rtems_unsigned32Clock_driver_ticks;47 volatile uint32_t Clock_driver_ticks; 48 48 49 49 static void Clock_exit( void ); … … 78 78 Clock_isr(rtems_vector_number vector) 79 79 { 80 u nsigned16tcr;80 uint16_t tcr; 81 81 82 82 /* reset the timer underflow flag */ … … 109 109 int cpudiv = 1; /* CPU frequency divider */ 110 110 int tidiv = 1; /* Timer input frequency divider */ 111 u nsigned32timer_divider; /* Calculated Timer Divider value */112 u nsigned8temp8;113 u nsigned16temp16;111 uint32_t timer_divider; /* Calculated Timer Divider value */ 112 uint8_t temp8; 113 uint16_t temp16; 114 114 115 115 /* … … 237 237 Clock_exit(void) 238 238 { 239 u nsigned8temp8 = 0;240 u nsigned16temp16 = 0;239 uint8_t temp8 = 0; 240 uint16_t temp16 = 0; 241 241 242 242 /* turn off the timer interrupts */ … … 297 297 void *pargp) 298 298 { 299 rtems_unsigned32isrlevel;299 uint32_t isrlevel; 300 300 rtems_libio_ioctl_args_t *args = pargp; 301 301 -
c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h
r8bc4430b re96a950b 51 51 extern void _dummy_isp( void ); 52 52 53 extern void __ISR_Handler( u nsigned32vector );53 extern void __ISR_Handler( uint32_t vector ); 54 54 55 55 /* This variable contains VBR value used to pass control when debug, error -
c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h
r8bc4430b re96a950b 36 36 * Macros to call UART registers 37 37 */ 38 #define SCRDR(n) (*(volatile rtems_unsigned8*)SH7750_SCRDR(n))38 #define SCRDR(n) (*(volatile uint8_t *)SH7750_SCRDR(n)) 39 39 #define SCRDR1 SCRDR(1) 40 40 #define SCRDR2 SCRDR(2) 41 #define SCTDR(n) (*(volatile rtems_unsigned8*)SH7750_SCTDR(n))41 #define SCTDR(n) (*(volatile uint8_t *)SH7750_SCTDR(n)) 42 42 #define SCTDR1 SCTDR(1) 43 43 #define SCTDR2 SCTDR(2) 44 #define SCSMR(n) ((n) == 1 ? *(volatile rtems_unsigned8*)SH7750_SCSMR1 : \45 *(volatile rtems_unsigned16*)SH7750_SCSMR2)44 #define SCSMR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSMR1 : \ 45 *(volatile uint16_t *)SH7750_SCSMR2) 46 46 #define SCSMR1 SCSMR(1) 47 47 #define SCSMR2 SCSMR(2) 48 #define SCSCR(n) ((n) == 1 ? *(volatile rtems_unsigned8*)SH7750_SCSCR1 : \49 *(volatile rtems_unsigned16*)SH7750_SCSCR2)48 #define SCSCR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSCR1 : \ 49 *(volatile uint16_t *)SH7750_SCSCR2) 50 50 #define SCSCR1 SCSCR(1) 51 51 #define SCSCR2 SCSCR(2) 52 #define SCSSR(n) ((n) == 1 ? *(volatile rtems_unsigned8*)SH7750_SCSSR1 : \53 *(volatile rtems_unsigned16*)SH7750_SCSSR2)52 #define SCSSR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSSR1 : \ 53 *(volatile uint16_t *)SH7750_SCSSR2) 54 54 #define SCSSR1 SCSSR(1) 55 55 #define SCSSR2 SCSSR(2) 56 #define SCSPTR1 (*(volatile rtems_unsigned8*)SH7750_SCSPTR1)57 #define SCSPTR2 (*(volatile rtems_unsigned16*)SH7750_SCSPTR2)58 #define SCBRR(n) (*(volatile rtems_unsigned8*)SH7750_SCBRR(n))56 #define SCSPTR1 (*(volatile uint8_t *)SH7750_SCSPTR1) 57 #define SCSPTR2 (*(volatile uint16_t *)SH7750_SCSPTR2) 58 #define SCBRR(n) (*(volatile uint8_t *)SH7750_SCBRR(n)) 59 59 #define SCBRR1 SCBRR(1) 60 60 #define SCBRR2 SCBRR(2) 61 #define SCFCR2 (*(volatile rtems_unsigned16*)SH7750_SCFCR2)62 #define SCFDR2 (*(volatile rtems_unsigned16*)SH7750_SCFDR2)63 #define SCLSR2 (*(volatile rtems_unsigned16*)SH7750_SCLSR2)61 #define SCFCR2 (*(volatile uint16_t *)SH7750_SCFCR2) 62 #define SCFDR2 (*(volatile uint16_t *)SH7750_SCFDR2) 63 #define SCLSR2 (*(volatile uint16_t *)SH7750_SCLSR2) 64 64 65 #define IPRB (*(volatile rtems_unsigned16*)SH7750_IPRB)66 #define IPRC (*(volatile rtems_unsigned16*)SH7750_IPRC)65 #define IPRB (*(volatile uint16_t *)SH7750_IPRB) 66 #define IPRC (*(volatile uint16_t *)SH7750_IPRC) 67 67 68 68 /* … … 72 72 */ 73 73 typedef struct sh4uart { 74 rtems_unsigned8chn; /* UART channel number */75 rtems_unsigned8int_driven; /* UART interrupt vector number, or74 uint8_t chn; /* UART channel number */ 75 uint8_t int_driven; /* UART interrupt vector number, or 76 76 0 if polled I/O */ 77 77 void *tty; /* termios channel descriptor */ 78 78 79 79 volatile const char *tx_buf; /* Transmit buffer from termios */ 80 volatile rtems_unsigned32tx_buf_len; /* Transmit buffer length */81 volatile rtems_unsigned32tx_ptr; /* Index of next char to transmit*/80 volatile uint32_t tx_buf_len; /* Transmit buffer length */ 81 volatile uint32_t tx_ptr; /* Index of next char to transmit*/ 82 82 83 83 rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */ -
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
r8bc4430b re96a950b 81 81 * peripheral module clock in Hz. 82 82 */ 83 rtems_unsigned32 83 uint32_t 84 84 sh4uart_get_Pph(void) 85 85 { 86 rtems_unsigned16 frqcr = *(volatile rtems_unsigned16*)SH7750_FRQCR;87 rtems_unsigned32Pph = CPU_CLOCK_RATE_HZ;86 uint16_t frqcr = *(volatile uint16_t *)SH7750_FRQCR; 87 uint32_t Pph = CPU_CLOCK_RATE_HZ; 88 88 89 89 switch (frqcr & SH7750_FRQCR_IFC) … … 162 162 sh4uart_set_baudrate(sh4uart *uart, speed_t baud) 163 163 { 164 rtems_unsigned32rate;165 rtems_signed16div;164 uint32_t rate; 165 int16_t div; 166 166 int n; 167 rtems_unsigned32Pph = sh4uart_get_Pph();167 uint32_t Pph = sh4uart_get_Pph(); 168 168 169 169 switch (baud) … … 251 251 if (int_driven) 252 252 { 253 rtems_unsigned16ipr;253 uint16_t ipr; 254 254 255 255 if (chn == SH4_SCI) … … 359 359 int level; 360 360 speed_t baud; 361 rtems_unsigned16smr;361 uint16_t smr; 362 362 363 smr = ( rtems_unsigned16)(*(rtems_unsigned8*)SH7750_SCSMR(uart->chn));363 smr = (uint16_t )(*(uint8_t *)SH7750_SCSMR(uart->chn)); 364 364 365 365 baud = cfgetospeed(t); … … 404 404 405 405 sh4uart_set_baudrate(uart, baud); 406 SCSMR(uart->chn) = ( rtems_unsigned8)smr;406 SCSMR(uart->chn) = (uint8_t )smr; 407 407 408 408 /* enable operations */ -
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
r8bc4430b re96a950b 255 255 */ 256 256 257 void __ISR_Handler( u nsigned32vector)257 void __ISR_Handler( uint32_t vector) 258 258 { 259 register u nsigned32level;259 register uint32_t level; 260 260 261 261 _CPU_ISR_Disable( level ); -
c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
r8bc4430b re96a950b 73 73 */ 74 74 void _CPU_ISR_install_vector( 75 u nsigned32vector,75 uint32_t vector, 76 76 proc_ptr new_handler, 77 77 proc_ptr *old_handler -
c/src/lib/libcpu/sh/sh7750/timer/timer.c
r8bc4430b re96a950b 40 40 rtems_isr timerisr(); 41 41 42 static rtems_unsigned32Timer_interrupts;42 static uint32_t Timer_interrupts; 43 43 44 44 /* Counter should be divided to this value to obtain time in microseconds */ 45 static rtems_unsigned32microseconds_divider;45 static uint32_t microseconds_divider; 46 46 47 47 /* Interrupt period in microseconds */ 48 static rtems_unsigned32microseconds_per_int;48 static uint32_t microseconds_per_int; 49 49 50 50 rtems_boolean Timer_driver_Find_average_overhead; … … 66 66 Timer_initialize(void) 67 67 { 68 rtems_unsigned8temp8;69 rtems_unsigned16temp16;68 uint8_t temp8; 69 uint16_t temp16; 70 70 rtems_interrupt_level level; 71 71 rtems_isr *ignored; … … 204 204 Read_timer(void) 205 205 { 206 rtems_unsigned32clicks;207 rtems_unsigned32ints;208 rtems_unsigned32total ;206 uint32_t clicks; 207 uint32_t ints; 208 uint32_t total ; 209 209 rtems_interrupt_level level; 210 rtems_unsigned32tcr;210 uint32_t tcr; 211 211 212 212 … … 282 282 timerisr(void) 283 283 { 284 u nsigned8temp8;284 uint8_t temp8; 285 285 286 286 /* reset the flags of the status register */
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