Index: ps/powerpc/haleakala/README
===================================================================
--- bsps/powerpc/haleakala/README	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,51 +1,0 @@
-# Adapted from Virtex BSP
-
-BSP NAME:           Haleakala
-BOARD:              AMCC/UDTech Haleakala 405Exr eval board
-BUS:                N/A
-CPU FAMILY:         ppc
-CPU:                PowerPC 405EXr
-COPROCESSORS:       N/A
-MODE:               32 bit mode
-
-DEBUG MONITOR:
-
-PERIPHERALS
-===========
-TIMERS:             405EXr internal
-SERIAL PORTS:       405EXr internal
-REAL-TIME CLOCK:    DS1338
-DMA:                405EXr internal
-VIDEO:              none
-SCSI:               none
-NETWORKING:         405EXr internal
-
-DRIVER INFORMATION
-==================
-CLOCK DRIVER:       PPC Decrementer
-IOSUPP DRIVER:      N/A
-SHMSUPP:            N/A
-TIMER DRIVER:       N/A
-TTY DRIVER:         shared
-
-STDIO
-=====
-PORT:               Console port 0
-ELECTRICAL:         RS-232
-BAUD:               9600-115200
-BITS PER CHARACTER: 8
-PARITY:             None
-STOP BITS:          1
-
-Notes
-=====
-
-Board description
------------------
-clock rate:	400 MHz
-ROM:		64MByte FLASH
-RAM:		256MByte DDR DRAM
-
-
-Porting
--------
Index: ps/powerpc/haleakala/config/haleakala.cfg
===================================================================
--- bsps/powerpc/haleakala/config/haleakala.cfg	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,27 +1,0 @@
-#
-#  Config file for a PowerPC 405 based card
-#  mhamel
-#
-
-include $(RTEMS_ROOT)/make/custom/default.cfg
-
-RTEMS_CPU=powerpc
-
-#  This contains the compiler options necessary to select the CPU model
-#  and (hopefully) optimize for it.
-#
-CPU_CFLAGS = -mcpu=405
-
-# optimize flag: typically -0, could use -O4 or -fast
-# -O4 is ok for RTEMS
-# NOTE: some level of -O may be actually required by inline assembler
-CFLAGS_OPTIMIZE_V = -O1 -g
-
-# The following two lines enable compiling and linking on per element.
-CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
-LDFLAGS = -Wl,--gc-sections
-
-define bsp-post-link
-	$(default-bsp-post-link)
-	$(OBJCOPY) -O srec $(basename $@)$(EXEEXT) $(basename $@)$(DOWNEXT)
-endef
Index: ps/powerpc/haleakala/include/bsp.h
===================================================================
--- bsps/powerpc/haleakala/include/bsp.h	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,107 +1,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsPowerPCHaleakala
- *
- * @brief Global BSP definitions.
- */
-
-/*  bsp.h
- *
- *  Generic 405EX bsp.h
- *  derived from virtex/include/bsp.h
- *  by Michael Hamel ADInstruments Ltd 2008
- *
- * derived from helas403/include/bsp.h:
- *  Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp
- *  Author:  Thomas Doerfler <td@imd.m.isar.de>
- *              IMD Ingenieurbuero fuer Microcomputertechnik
- *
- *  COPYRIGHT (c) 1998 by IMD
- *
- *  Changes from IMD are covered by the original distributions terms.
- *  This file has been derived from the papyrus BSP.
- *
- *  Author:  Andrew Bray <andy@i-cubed.co.uk>
- *
- *  COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of i-cubed limited not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      i-cubed limited makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- *
- *
- */
-
-#ifndef LIBBSP_POWERPC_HALEAKALA_BSP_H
-#define LIBBSP_POWERPC_HALEAKALA_BSP_H
-
-/**
- * @defgroup RTEMSBSPsPowerPCHaleakala Haleakala
- *
- * @ingroup RTEMSBSPsPowerPC
- *
- * @brief Haleakala Board Support Package.
- *
- * @{
- */
-
-#include <bspopts.h>
-
-#ifdef ASM
-
-
-  /* Definition of where to store registers in alignment handler */
-  #define ALIGN_REGS 0x0140
-
-#else
-
-  #include <rtems.h>
-  #include <libcpu/io.h>
-  #include <bsp/irq.h>
-  #include <bsp/vectors.h>
-  #include <bsp/default-initial-extension.h>
-
-  #ifdef __cplusplus
-  extern "C" {
-  #endif
-
-  /* Network Defines */
-  #define RTEMS_BSP_NETWORK_DRIVER_NAME     "eth0"
-
-  struct rtems_bsdnet_ifconfig;
-  int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching);
-  #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach
-
-  #define BSP_UART_IOBASE_COM1  0xEF600200    /* PPC405EX */
-  #define BSP_UART_IOBASE_COM2  0xEF600300
-
-  #define BSP_CONSOLE_PORT    BSP_UART_COM1    /* console */
-
-  #define BSP_UART_BAUD_BASE    (11059200 / 16)    /* Kilauea ext clock, max speed */
-
-  #ifdef __cplusplus
-  }
-  #endif
-#endif /* ASM */
-
-/** @} */
-
-#endif /* BSP_H */
Index: ps/powerpc/haleakala/include/bsp/irq.h
===================================================================
--- bsps/powerpc/haleakala/include/bsp/irq.h	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,168 +1,0 @@
-/*===============================================================*\
-| Project: RTEMS Haleakala BSP                                    |
-| by Michael Hamel ADInstruments Ltd 2008                         |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.org/license/LICENSE.                           |
-|                                                                 |
-\*===============================================================*/
-
-
-#ifndef Haleakala_IRQ_IRQ_H
-#define Haleakala_IRQ_IRQ_H
-
-/* Implemented for us in bsp_irq_dispatch_list */
-#define BSP_SHARED_HANDLER_SUPPORT      1
-
-#include <rtems/irq.h>
-
-#ifndef ASM
-
-#include <bsp/irq-default.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-	/* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode.
-	   These are arbitrary but it makes things easier if they match the CPU interrupt numbers */
-
-	/*
-
-		#define	BSP_UIC_UART0_GP		(BSP_UIC_IRQ_LOWEST_OFFSET + 0)
-		#define	BSP_UIC_UART1			(BSP_UIC_IRQ_LOWEST_OFFSET + 1)
-		#define	BSP_UIC_IIC0			(BSP_UIC_IRQ_LOWEST_OFFSET + 2)
-		#define	BSP_UIC_ExtMaster		(BSP_UIC_IRQ_LOWEST_OFFSET + 3)
-		#define	BSP_UIC_PCI				(BSP_UIC_IRQ_LOWEST_OFFSET + 4)
-		#define	BSP_UIC_DMA0			(BSP_UIC_IRQ_LOWEST_OFFSET + 5)
-		#define	BSP_UIC_DMA1			(BSP_UIC_IRQ_LOWEST_OFFSET + 6)
-		#define	BSP_UIC_DMA2			(BSP_UIC_IRQ_LOWEST_OFFSET + 7)
-		#define	BSP_UIC_DMA3			(BSP_UIC_IRQ_LOWEST_OFFSET + 8)
-		#define	BSP_UIC_ENetWU			(BSP_UIC_IRQ_LOWEST_OFFSET + 9)
-		#define	BSP_UIC_MALSERR			(BSP_UIC_IRQ_LOWEST_OFFSET + 10)
-		#define	BSP_UIC_MALTXEOB		(BSP_UIC_IRQ_LOWEST_OFFSET + 11)
-		#define	BSP_UIC_MALRXEOB		(BSP_UIC_IRQ_LOWEST_OFFSET + 12)
-		#define	BSP_UIC_MALTXDE			(BSP_UIC_IRQ_LOWEST_OFFSET + 13)
-		#define	BSP_UIC_MALRXDE			(BSP_UIC_IRQ_LOWEST_OFFSET + 14)
-		#define	BSP_UIC_ENet			(BSP_UIC_IRQ_LOWEST_OFFSET + 15)
-		#define	BSP_UIC_PCISERR			(BSP_UIC_IRQ_LOWEST_OFFSET + 16)
-		#define	BSP_UIC_ECCERR			(BSP_UIC_IRQ_LOWEST_OFFSET + 17)
-		#define	BSP_UIC_PCIPower		(BSP_UIC_IRQ_LOWEST_OFFSET + 18)
-		#define	BSP_UIC_IRQ0			(BSP_UIC_IRQ_LOWEST_OFFSET + 25)
-		#define	BSP_UIC_IRQ1			(BSP_UIC_IRQ_LOWEST_OFFSET + 26)
-		#define	BSP_UIC_IRQ2			(BSP_UIC_IRQ_LOWEST_OFFSET + 27)
-		#define	BSP_UIC_IRQ3			(BSP_UIC_IRQ_LOWEST_OFFSET + 28)
-		#define	BSP_UIC_IRQ4			(BSP_UIC_IRQ_LOWEST_OFFSET + 29)
-		#define	BSP_UIC_IRQ5			(BSP_UIC_IRQ_LOWEST_OFFSET + 30)
-		#define	BSP_UIC_IRQ6			(BSP_UIC_IRQ_LOWEST_OFFSET + 31)
-
-		#define	BSP_UIC_IRQ_NUMBER			(32)
-
-	*/
-	/* PPC405EX interrupt vectors */
-	#define	BSP_UIC_UART1			(BSP_UIC_IRQ_LOWEST_OFFSET + 1)
-	#define	BSP_UIC_IIC0			(BSP_UIC_IRQ_LOWEST_OFFSET + 2)
-	#define	BSP_UIC_EIPPKP_READY	(BSP_UIC_IRQ_LOWEST_OFFSET + 3)
-	#define	BSP_UIC_EIPPKP_TRNG		(BSP_UIC_IRQ_LOWEST_OFFSET + 4)
-	#define	BSP_UIC_EBM				(BSP_UIC_IRQ_LOWEST_OFFSET + 5)
-	#define	BSP_UIC_OPBtoPLB		(BSP_UIC_IRQ_LOWEST_OFFSET + 6)
-	#define	BSP_UIC_IIC1			(BSP_UIC_IRQ_LOWEST_OFFSET + 7)
-	#define	BSP_UIC_SPI				(BSP_UIC_IRQ_LOWEST_OFFSET + 8)
-	#define	BSP_UIC_IRQ0			(BSP_UIC_IRQ_LOWEST_OFFSET + 9)
-	#define	BSP_UIC_MALTXEOB		(BSP_UIC_IRQ_LOWEST_OFFSET + 10)
-	#define	BSP_UIC_MALRXEOB		(BSP_UIC_IRQ_LOWEST_OFFSET + 11)
-	#define	BSP_UIC_DMA0			(BSP_UIC_IRQ_LOWEST_OFFSET + 12)
-	#define	BSP_UIC_DMA1			(BSP_UIC_IRQ_LOWEST_OFFSET + 13)
-	#define	BSP_UIC_DMA2			(BSP_UIC_IRQ_LOWEST_OFFSET + 14)
-	#define	BSP_UIC_DMA3			(BSP_UIC_IRQ_LOWEST_OFFSET + 15)
-	#define	BSP_UIC_PCIe0AL			(BSP_UIC_IRQ_LOWEST_OFFSET + 16)
-	#define	BSP_UIC_PCIe0VPD		(BSP_UIC_IRQ_LOWEST_OFFSET + 17)
-	#define	BSP_UIC_PCIe0HRst		(BSP_UIC_IRQ_LOWEST_OFFSET + 18)
-	#define	BSP_UIC_EIPPKP_PKA		(BSP_UIC_IRQ_LOWEST_OFFSET + 19)
-	#define	BSP_UIC_PCIe0TCR		(BSP_UIC_IRQ_LOWEST_OFFSET + 20)
-	#define	BSP_UIC_PCIe0VCO		(BSP_UIC_IRQ_LOWEST_OFFSET + 21)
-	#define	BSP_UIC_EIPPKP_TRNG_AL	(BSP_UIC_IRQ_LOWEST_OFFSET + 22)
-	#define	BSP_UIC_EIP94			(BSP_UIC_IRQ_LOWEST_OFFSET + 23)
-	#define	BSP_UIC_EMAC0			(BSP_UIC_IRQ_LOWEST_OFFSET + 24)
-	#define	BSP_UIC_EMAC1			(BSP_UIC_IRQ_LOWEST_OFFSET + 25)
-	#define	BSP_UIC_UART0			(BSP_UIC_IRQ_LOWEST_OFFSET + 26)
-	#define	BSP_UIC_IRQ4			(BSP_UIC_IRQ_LOWEST_OFFSET + 27)
-	#define	BSP_UIC_UIC2_STD		(BSP_UIC_IRQ_LOWEST_OFFSET + 28)
-	#define	BSP_UIC_UIC2_CRIT		(BSP_UIC_IRQ_LOWEST_OFFSET + 29)
-	#define	BSP_UIC_UIC1_STD		(BSP_UIC_IRQ_LOWEST_OFFSET + 30)
-	#define	BSP_UIC_UIC1_CRIT		(BSP_UIC_IRQ_LOWEST_OFFSET + 31)
-
-	#define BSP_UIC1_IRQ_LOWEST_OFFSET	(BSP_UIC_IRQ_LOWEST_OFFSET + 32)
-	#define	BSP_UIC_MALSERR			(BSP_UIC1_IRQ_LOWEST_OFFSET + 0)
-	#define	BSP_UIC_MALTXDE			(BSP_UIC1_IRQ_LOWEST_OFFSET + 1)
-	#define	BSP_UIC_MALRXDE			(BSP_UIC1_IRQ_LOWEST_OFFSET + 2)
-	#define	BSP_UIC_PCIe0DCRErr		(BSP_UIC1_IRQ_LOWEST_OFFSET + 3)
-	#define	BSP_UIC_PCIe1DCRErr		(BSP_UIC1_IRQ_LOWEST_OFFSET + 4)
-	#define	BSP_UIC_ExtBus			(BSP_UIC1_IRQ_LOWEST_OFFSET + 5)
-	#define	BSP_UIC_NDFC			(BSP_UIC1_IRQ_LOWEST_OFFSET + 6)
-	#define	BSP_UIC_EIPKP_SLAVE		(BSP_UIC1_IRQ_LOWEST_OFFSET + 7)
-	#define	BSP_UIC_GPT_TIMER5		(BSP_UIC1_IRQ_LOWEST_OFFSET + 8)
-	#define	BSP_UIC_GPT_TIMER6		(BSP_UIC1_IRQ_LOWEST_OFFSET + 9)
-
-	#define	BSP_UIC_GPT_TIMER0		(BSP_UIC1_IRQ_LOWEST_OFFSET + 16)
-	#define	BSP_UIC_GPT_TIMER1		(BSP_UIC1_IRQ_LOWEST_OFFSET + 17)
-	#define	BSP_UIC_IRQ7			(BSP_UIC1_IRQ_LOWEST_OFFSET + 18)
-	#define	BSP_UIC_IRQ8			(BSP_UIC1_IRQ_LOWEST_OFFSET + 19)
-	#define	BSP_UIC_IRQ9			(BSP_UIC1_IRQ_LOWEST_OFFSET + 20)
-	#define	BSP_UIC_GPT_TIMER2		(BSP_UIC1_IRQ_LOWEST_OFFSET + 21)
-	#define	BSP_UIC_GPT_TIMER3		(BSP_UIC1_IRQ_LOWEST_OFFSET + 22)
-	#define	BSP_UIC_GPT_TIMER4		(BSP_UIC1_IRQ_LOWEST_OFFSET + 23)
-	#define	BSP_UIC_SERIAL_ROM		(BSP_UIC1_IRQ_LOWEST_OFFSET + 24)
-	#define	BSP_UIC_GPT_DEC			(BSP_UIC1_IRQ_LOWEST_OFFSET + 25)
-	#define	BSP_UIC_IRQ2			(BSP_UIC1_IRQ_LOWEST_OFFSET + 26)
-	#define	BSP_UIC_IRQ5			(BSP_UIC1_IRQ_LOWEST_OFFSET + 27)
-	#define	BSP_UIC_IRQ6			(BSP_UIC1_IRQ_LOWEST_OFFSET + 28)
-	#define	BSP_UIC_EMAC0WU			(BSP_UIC1_IRQ_LOWEST_OFFSET + 29)
-	#define	BSP_UIC_IRQ1			(BSP_UIC1_IRQ_LOWEST_OFFSET + 30)
-	#define	BSP_UIC_EMAC1WU			(BSP_UIC1_IRQ_LOWEST_OFFSET + 31)
-
-	#define BSP_UIC2_IRQ_LOWEST_OFFSET	(BSP_UIC_IRQ_LOWEST_OFFSET + 64)
-	#define	BSP_UIC_PCIe0INTA		(BSP_UIC2_IRQ_LOWEST_OFFSET + 0)
-	#define	BSP_UIC_PCIe0INTB		(BSP_UIC2_IRQ_LOWEST_OFFSET + 1)
-	#define	BSP_UIC_PCIe0INTC		(BSP_UIC2_IRQ_LOWEST_OFFSET + 2)
-	#define	BSP_UIC_PCIe0INTD		(BSP_UIC2_IRQ_LOWEST_OFFSET + 3)
-	#define	BSP_UIC_IRQ3			(BSP_UIC2_IRQ_LOWEST_OFFSET + 4)
-
-	#define	BSP_UIC_USBOTG			(BSP_UIC2_IRQ_LOWEST_OFFSET + 30)
-
-	#define	BSP_UIC_IRQ_NUMBER			(95)
-
-
-	#define BSP_UIC_IRQ_LOWEST_OFFSET	0
-	#define BSP_UIC_IRQ_MAX_OFFSET		(BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1)
-
-	#define BSP_UART_COM1_IRQ		BSP_UIC_UART0 /* Required by shared/console/uart.c */
-	#define BSP_UART_COM2_IRQ		BSP_UIC_UART1
-
-	/* Define processor IRQ numbers; IRQs that are handled by the exception vectors */
-
-	#define BSP_PIT				BSP_PROCESSOR_IRQ_LOWEST_OFFSET	/* Required by ppc403/clock.c */
-	#define	BSP_FIT				BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1
-	#define	BSP_WDOG			BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
-
-	#define BSP_PROCESSOR_IRQ_NUMBER	    (3)
-	#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	(BSP_UIC_IRQ_MAX_OFFSET + 1)
-	#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
-
-	/* Summary and totals */
-
-	#define BSP_IRQ_NUMBER		 	(BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
-	#define BSP_LOWEST_OFFSET		(BSP_UIC_IRQ_LOWEST_OFFSET)
-	#define BSP_MAX_OFFSET			(BSP_IRQ_NUMBER - 1)
-
-	extern void BSP_rtems_irq_mng_init(unsigned cpuId);		// Implemented in irq_init.c
-	#include <bsp/irq_supp.h>
-
-	#ifdef __cplusplus
-	}
-	#endif
-#endif /* ASM */
-
-#endif /* Haleakala_IRQ_IRQ_H */
Index: ps/powerpc/haleakala/include/mmu_405.h
===================================================================
--- bsps/powerpc/haleakala/include/mmu_405.h	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,77 +1,0 @@
-#ifndef _mmu_405_h
-#define _mmu_405_h
-
-/* 
-   Simple interface to the PowerPC 405 MMU
-   
-   The intention here is just to allow the MMU to be used to define cacheability and
-   read/write/execute permissions in a simple enough way to fit entirely into the
-   64-entry TLB cache.
-   
-   This code does not do address relocation and does not generate any MMU-related interrupts.
-   
-   The process ID support is there for a possible future extension where RTEMS supports
-   setting the process ID on task switches, which allows per-process stack protection
-    
-   This code will call fatal_error() if your add_space() calls overrun the 64 entries
-
-   Michael Hamel ADInstruments 2008
-
-*/
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "stdint.h"
-
-enum {
-	kAllProcessIDs = 0
-};
-
-typedef enum MMUAccessType {
-	executable,
-	readOnlyData,
-	readOnlyNoCache,
-	readWriteData,
-	readWriteNoCache,
-	readWriteExecutable
-} MMUAccessType;
-
-/* Initialise and clear the MMU */
-void		mmu_initialise(void);
-
-/* Turn on/off data access translation */
-bool		mmu_enable_data(bool enable);
-
-/* Turn on instruction translation */
-bool		mmu_enable_code(bool enable);
-
-/* Define properties for an area of memory (must be 1K-aligned) */
-void		mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID);
-
-/* Delete a memory property definition */
-void		mmu_remove_space(uint32_t startAddr, uint32_t endAddr);
-
-/* Return number of TLB entries out of total in use */
-int			mmu_get_tlb_count(void);
-
-/* Allocate a new process ID and return it */
-uint8_t		mmu_new_processID(void);
-
-/* Free a process ID that has been in use */
-void		mmu_free_processID(uint8_t freeThis);
-
-/* Return the current process ID */
-uint8_t		mmu_current_processID(void);
-
-/* Change the process ID to ID and return the old value */
-uint8_t		mmu_set_processID(uint8_t toID);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //_mmu_405.h
Index: ps/powerpc/haleakala/include/tm27.h
===================================================================
--- bsps/powerpc/haleakala/include/tm27.h	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,1 +1,0 @@
-#include <rtems/tm27-default.h>
Index: ps/powerpc/haleakala/irq/irq.c
===================================================================
--- bsps/powerpc/haleakala/irq/irq.c	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,237 +1,0 @@
-/*
- *
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- *  Middleware support for PPC405 by M.Hamel ADInstruments Ltd 2008
- */
-
-#include <rtems.h>
-#include <bsp.h>
-#include <bsp/irq.h>
-#include <bsp/irq_supp.h>
-#include <bsp/vectors.h>
-#include <libcpu/powerpc-utility.h>
-
-
-/* PPC405EX UIC numbers */
-#define UIC_DCR_BASE 0xc0
-#define UIC0_SR      (UIC_DCR_BASE+0x0)  /* UIC status                       */
-#define UIC0_SRS     (UIC_DCR_BASE+0x1)  /* UIC status set                   */
-#define UIC0_ER      (UIC_DCR_BASE+0x2)  /* UIC enable                       */
-#define UIC0_CR      (UIC_DCR_BASE+0x3)  /* UIC critical                     */
-#define UIC0_PR      (UIC_DCR_BASE+0x4)  /* UIC polarity                     */
-#define UIC0_TR      (UIC_DCR_BASE+0x5)  /* UIC triggering                   */
-#define UIC0_MSR     (UIC_DCR_BASE+0x6)  /* UIC masked status                */
-#define UIC0_VR      (UIC_DCR_BASE+0x7)  /* UIC vector                       */
-#define UIC0_VCR     (UIC_DCR_BASE+0x8)  /* UIC vector configuration         */
-
-#define UIC1_SR      (UIC_DCR_BASE+0x10)  /* UIC status                       */
-#define UIC1_SRS     (UIC_DCR_BASE+0x11)  /* UIC status set                   */
-#define UIC1_ER      (UIC_DCR_BASE+0x12)  /* UIC enable                       */
-#define UIC1_CR      (UIC_DCR_BASE+0x13)  /* UIC critical                     */
-#define UIC1_PR      (UIC_DCR_BASE+0x14)  /* UIC polarity                     */
-#define UIC1_TR      (UIC_DCR_BASE+0x15)  /* UIC triggering                   */
-#define UIC1_MSR     (UIC_DCR_BASE+0x16)  /* UIC masked status                */
-#define UIC1_VR      (UIC_DCR_BASE+0x17)  /* UIC vector                       */
-#define UIC1_VCR     (UIC_DCR_BASE+0x18)  /* UIC vector configuration         */
-
-#define UIC2_SR      (UIC_DCR_BASE+0x20)  /* UIC status                       */
-#define UIC2_SRS     (UIC_DCR_BASE+0x21)  /* UIC status set                   */
-#define UIC2_ER      (UIC_DCR_BASE+0x22)  /* UIC enable                       */
-#define UIC2_CR      (UIC_DCR_BASE+0x23)  /* UIC critical                     */
-#define UIC2_PR      (UIC_DCR_BASE+0x24)  /* UIC polarity                     */
-#define UIC2_TR      (UIC_DCR_BASE+0x25)  /* UIC triggering                   */
-#define UIC2_MSR     (UIC_DCR_BASE+0x26)  /* UIC masked status                */
-#define UIC2_VR      (UIC_DCR_BASE+0x27)  /* UIC vector                       */
-#define UIC2_VCR     (UIC_DCR_BASE+0x28)  /* UIC vector configuration         */
-
-enum { kUICWords = 3 };
-
-static rtems_irq_connect_data* rtems_hdl_tblP;
-static rtems_irq_connect_data  dflt_entry;
-
-static uint32_t	gEnabledInts[kUICWords];		/* 1-bits mean enabled */
-static uint32_t	gIntInhibited[kUICWords];		/* 1-bits disable, overriding gEnabledInts because the interrupt
-												   is being processed in C_dispatch_irq_handler */
-
-static inline int IsUICIRQ(const rtems_irq_number irqLine)
-{
-  return (((int) irqLine <= BSP_UIC_IRQ_MAX_OFFSET) &&
-	  ((int) irqLine >= BSP_UIC_IRQ_LOWEST_OFFSET)
-	 );
-}
-
-static void WriteIState(void)
-/* Write the gEnabledInts state masked by gIntInhibited to the hardware */
-{
-	PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,
-					gEnabledInts[0] & ~gIntInhibited[0]);
-	PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER,
-					gEnabledInts[1] & ~gIntInhibited[1]);
-	PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER,
-					gEnabledInts[2] & ~gIntInhibited[2]);
-}
-
-void
-BSP_enable_irq_at_pic(const rtems_irq_number irq)
-/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */
-{
-	if (IsUICIRQ(irq)) {
-		/* Set relevant bit in the state, write state to the UIC */
-		gEnabledInts[irq>>5] |= (0x80000000 >> (irq & 0x1F));
-		WriteIState();
-	}
-}
-
-int
-BSP_disable_irq_at_pic(const rtems_irq_number irq)
-/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */
-{
-	if (IsUICIRQ(irq)) {
-		uint32_t oldState;
-		int		 iword = irq>>5;
-		uint32_t mask = (0x80000000 >> (irq & 0x1F));
-
-		oldState = gEnabledInts[iword] & mask;
-		gEnabledInts[iword] &= ~mask;
-		WriteIState();
-		return oldState ? 1 : 0;
-	} else
-		return -1;
-}
-
-int
-BSP_setup_the_pic(rtems_irq_global_settings* config)
-{
-	int i;
-
-	dflt_entry     = config->defaultEntry;
-	rtems_hdl_tblP = config->irqHdlTbl;
-	for (i=0; i<kUICWords; i++)
-		gIntInhibited[i] = 0;
-
-	/* disable all interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000);
-	/* Set Critical / Non Critical interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000);
-	/* Set Interrupt Polarities */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_PR, 0xf7ffffff);
-	/* Set Interrupt Trigger Levels */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_TR, 0x01e1fff8);
-	/* Set Vect base=0,INT31 Highest priority */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_VR, 0x00000001);
-	/* clear all interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_SR, 0xffffffff);
-
-	/* disable all interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_ER, 0x00000000);
-	/* Set Critical / Non Critical interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_CR, 0x00000000);
-	/* Set Interrupt Polarities */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_PR, 0xfffac785);
-	/* Set Interrupt Trigger Levels */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_TR, 0x001d0040);
-	/* Set Vect base=0,INT31 Highest priority */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_VR, 0x00000001);
-	/* clear all interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_SR, 0xffffffff);
-
-	/* Disable all interrupts except cascade UIC0 and UIC1 */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_ER, 0x0000000a);
-	/* Set Critical / Non Critical interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_CR, 0x00000000);
-	/* Set Interrupt Polarities */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_PR, 0xffbfefef);
-	/* Set Interrupt Trigger Levels */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_TR, 0x00007000);
-	/* Set Vect base=0,INT31 Highest priority */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001);
-	/* clear all interrupts */
-	PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff);
-
-	return 1;
-}
-
-
-/*
- * High level IRQ handler called from shared_raw_irq_code_entry; decode and
- * dispatch. Note that this routine needs to be re-entrant
- *
- * No support for critical interrupts here yet
- */
-
-int
-C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
-{
-	if (excNum == ASM_EXT_VECTOR) {
-		uint32_t active[kUICWords];
-
-		/* Fetch the masked flags that tell us what external ints are active.
-		   Likely to be only one, but we need to handle more than one,
-		   OR the flags into gIntInhibited */
-		active[0] = PPC_DEVICE_CONTROL_REGISTER(UIC0_MSR);
-		active[1] = PPC_DEVICE_CONTROL_REGISTER(UIC1_MSR);
-		active[2] = PPC_DEVICE_CONTROL_REGISTER(UIC2_MSR);
-		gIntInhibited[0] |= active[0];
-		gIntInhibited[1] |= active[1];
-		gIntInhibited[2] |= active[2];
-
-		/*  ...and update the hardware so the active interrupts are disabled */
-		WriteIState();
-
-		/* Loop, calling bsp_irq_dispatch_list for each active interrupt */
-		while ((active[0] | active[1] | active[2]) != 0) {
-			uint32_t index = -1;
-			uint32_t bit, bmask;
-
-			/* Find an active interrupt, searching 0..2, bit 0..bit 31 (IBM order) */
-			do {
-				index++;
-				asm volatile ("	cntlzw %0, %1":"=r" (bit):"r" (active[index]));
-			} while (bit==32);
-
-			/* Call the matching handler */
-			bsp_irq_dispatch_list(rtems_hdl_tblP, (index*32)+bit, dflt_entry.hdl);
-
-			/* Write a 1-bit to the appropriate status register to clear it */
-			bmask = 0x80000000 >> bit;
-			switch (index) {
-			case 0:
-			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask);
-			  break;
-			case 1:
-			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask);
-			  break;
-			case 2:
-			  PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask);
-			  break;
-			}
-
-			/* Clear in the active record and gIntInhibited */
-			active[index] &= ~bmask;
-			gIntInhibited[index] &= ~bmask;
-		};
-
-		/* Update the hardware again so the interrupts we have handled are unmasked */
-		WriteIState();
-		return 0;
-
-	} else if (excNum == ASM_DEC_VECTOR) {		/* 0x1000 remapped by C_dispatch_dec_handler_bookE  */
-		bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl);
-		return 0;
-
-	} else if (excNum == ASM_BOOKE_FIT_VECTOR) {		/* 0x1010 mapped to 0x13 by ppc_get_vector_addr */
-		bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl);
-		return 0;
-
-	} else if (excNum == ASM_BOOKE_WDOG_VECTOR) {		/* 0x1020 mapped to 0x14 by ppc_get_vector_addr */
-		bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl);
-		return 0;
-
-	} else
-		return -1; /* unhandled interrupt, panic time */
-}
-
Index: ps/powerpc/haleakala/irq/irq_init.c
===================================================================
--- bsps/powerpc/haleakala/irq/irq_init.c	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,96 +1,0 @@
-/*===============================================================*\
-| Project: RTEMS Haleakala BSP                                    |
-|  *  by Michael Hamel ADInstruments Ltd 2008                     |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be         |
-| found in the file LICENSE in this distribution or at            |
-|                                                                 |
-| http://www.rtems.org/license/LICENSE.                           |
-|                                                                 |
-+-----------------------------------------------------------------+
-| this file contains the irq controller handler                   |
-\*===============================================================*/
-#include <libcpu/spr.h>
-#include <bsp/irq.h>
-#include <bsp.h>
-#include <bsp/vectors.h>
-#include <rtems/bspIo.h>
-#include <rtems/powerpc/powerpc.h>
-
-
-/*
- * default on/off function
- */
-static void nop_func(void)
-{
-}
-
-/*
- * default isOn function
- */
-static int not_connected(void)
-{
-	return 0;
-}
-
-static rtems_irq_connect_data      rtemsIrq[BSP_IRQ_NUMBER];
-static rtems_irq_global_settings   initial_config;
-static rtems_irq_connect_data      defaultIrq = {
-  .name   = 0,
-  .hdl    = NULL,
-  .handle = NULL,
-  .on     = (rtems_irq_enable) nop_func,
-  .off    = (rtems_irq_disable) nop_func,
-  .isOn   = (rtems_irq_is_enabled) not_connected,
-#ifdef BSP_SHARED_HANDLER_SUPPORT
-  .next_handler = NULL
-#endif
-};
-
-static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
-  /*
-   * Processor exceptions handled as interrupts
-   */
-  0
-};
-
-  /*
-   * This code assumes the exceptions management setup has already
-   * been done. We just need to replace the exceptions that will
-   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
-   * this means the decrementer exception and the external exception.
-   */
-
-void BSP_rtems_irq_mng_init(unsigned cpuId)
-{
-  int i;
-
-  /*
-   * re-init the rtemsIrq table
-   */
-  for (i = 0; i < BSP_IRQ_NUMBER; i++) {
-    rtemsIrq[i]      = defaultIrq;
-    rtemsIrq[i].name = i;
-  }
-  /*
-   * Init initial Interrupt management config
-   */
-  initial_config.irqNb        = BSP_IRQ_NUMBER;
-  initial_config.defaultEntry = defaultIrq;
-  initial_config.irqHdlTbl    = rtemsIrq;
-  initial_config.irqBase      = BSP_LOWEST_OFFSET;
-  initial_config.irqPrioTbl   = irqPrioTable;
-
-  if (!BSP_rtems_irq_mngt_set(&initial_config)) {
-    /*
-     * put something here that will show the failure...
-     */
-    rtems_panic(
-      "Unable to initialize RTEMS interrupt management!!! System locked\n"
-    );
-  }
-
-  #ifdef TRACE_IRQ_INIT
-    printk("RTEMS IRQ management is now operational\n");
-  #endif
-}
Index: ps/powerpc/haleakala/start/bspstart.c
===================================================================
--- bsps/powerpc/haleakala/start/bspstart.c	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,190 +1,0 @@
-/*
- *  This routine does the bulk of the system initialization.
- */
-
-/*
- *  Author:     Thomas Doerfler <td@imd.m.isar.de>
- *              IMD Ingenieurbuero fuer Microcomputertechnik
- *
- *  COPYRIGHT (c) 1998 by IMD
- *
- *  Changes from IMD are covered by the original distributions terms.
- *  This file has been derived from the papyrus BSP:
- *
- *  Author:     Andrew Bray <andy@i-cubed.co.uk>
- *
- *  COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of i-cubed limited not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      i-cubed limited makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Modifications for spooling console driver and control of memory layout
- *  with linker command file by
- *              Thomas Doerfler <td@imd.m.isar.de>
- *  for these modifications:
- *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies. IMD makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c:
- *
- *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  Modifications for PPC405GP by Dennis Ehlin
- *
- *  Further modified for the PPC405EX Haleakala board by
- *  Michael Hamel ADInstruments Ltd May 2008
- */
-#include <string.h>
-#include <fcntl.h>
-
-#include <rtems/bspIo.h>
-#include <rtems/counter.h>
-
-#include <bsp.h>
-#include <bsp/bootcard.h>
-#include <bsp/uart.h>
-#include <bsp/irq.h>
-#include <libcpu/powerpc-utility.h>
-#include <bsp/vectors.h>
-#include <ppc4xx/ppc405gp.h>
-#include <ppc4xx/ppc405ex.h>
-
-#include <stdio.h>
-/*
- *  Driver configuration parameters
- */
-
-/* Expected by clock.c */
-uint32_t    bsp_clicks_per_usec;
-
-/*-------------------- Haleakala-specific UART setup -------------------------*/
-
-static void
-EarlyUARTInit(int baudRate)
-{
-  volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
-  int divider = BSP_UART_BAUD_BASE / baudRate;
-  up[LCR] = DLAB;    /* Access DLM/DLL */
-  up[DLL] = divider & 0x0FF;
-  up[DLM] = divider >> 8;
-  up[LCR] = CHR_8_BITS;
-  up[MCR] = DTR | RTS;
-  up[FCR] = FIFO_EN | XMIT_RESET | RCV_RESET;
-  up[THR] = '+';
-}
-
-
-static void
-InitUARTClock(void)
-{
-  uint32_t reg;
-  mfsdr(SDR0_UART0,reg);
-  reg &= ~0x008000FF;
-  reg |= 0x00800001;    /* Ext clock, div 1 */
-  mtsdr(SDR0_UART0,reg);
-}
-
-static void GPIO_AlternateSelect(int bitnum, int source)
-/* PPC405EX: select a GPIO function for the specified pin */
-{
-  int shift;
-  unsigned long value, mask;
-  GPIORegisters* gpioPtr = (GPIORegisters*)(GPIOAddress);
-
-  shift = (31 - bitnum) & 0xF;
-  value = (source & 3) << (shift*2);
-  mask  = 3 << (shift*2);
-  if (bitnum <= 15) {
-    gpioPtr->OSRL = (gpioPtr->OSRL & ~mask) | value;
-    gpioPtr->TSRL = (gpioPtr->TSRL & ~mask) | value;
-  } else {
-    gpioPtr->OSRH = (gpioPtr->OSRH & ~mask) | value;
-    gpioPtr->TSRH = (gpioPtr->TSRH & ~mask) | value;
-  }
-}
-
-static void Init_FPGA(void)
-{
-  /* Have to write to the FPGA to enable the UART drivers */
-  /* Have to enable CS2 as an output in GPIO to get the FPGA working */
-  mtebc(EBC0_B2CR,0xF0018000);  /* Set up CS2 at 0xF0000000 */
-  mtebc(EBC0_B2AP,0x9400C800);
-  GPIO_AlternateSelect(9,1);    /* GPIO9 = PerCS2 */
-  {
-    unsigned long *fpgaPtr = (unsigned long*)(0xF0000000);
-    unsigned long n;
-    n = *(fpgaPtr);
-    n &= ~0x00100;    /* User LEDs on */
-    n |=  0x30000;    /* UART 0 and 1 transcievers on! */
-    *fpgaPtr = n;
-  }
-}
-
-/*===================================================================*/
-
-static void
-DirectUARTWrite(const char c)
-{
-  volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
-  while ((up[LSR] & THRE) == 0) { ; }
-  up[THR] = c;
-}
-
-/* We will provide our own printk output function as it may get used early */
-BSP_output_char_function_type     BSP_output_char = DirectUARTWrite;
-BSP_polling_getchar_function_type BSP_poll_char = NULL;
-
-uint32_t _CPU_Counter_frequency(void)
-{
-  return bsp_clicks_per_usec * 1000000;
-}
-
-/*===================================================================*/
-
-void bsp_start( void )
-{
-  /* Get the UART clock initialized first in case we call printk */
-
-  InitUARTClock();
-  Init_FPGA();
-  EarlyUARTInit(115200);
-
-  /*
-   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
-   * function store the result in global variables
-   * so that it can be used later...
-   */
-  get_ppc_cpu_type();
-  get_ppc_cpu_revision();
-
-  /*
-   *  initialize the device driver parameters
-   */
-
-  /* Set globals visible to clock.c */
-  /* timebase register ticks/microsecond = CPU Clk in MHz */
-  bsp_clicks_per_usec = 400;
-
-  ppc_exc_initialize();
-
-  /*
-   * Install our own set of exception vectors
-   */
-  BSP_rtems_irq_mng_init(0);
-}
Index: ps/powerpc/haleakala/start/linkcmds
===================================================================
--- bsps/powerpc/haleakala/start/linkcmds	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,274 +1,0 @@
-/* 
- *  This file contains directives for the GNU linker which are specific
- *  to the 405GP/EX
- *  This file is intended to be used together with dlentry.s
- *  it will generate downloadable code
- *
- *  Modifications for gen405 by Dennis Ehlin
- *  Modifications for virtex by Keith, Greg, and Bob
- *  Modifications for 405GP/EX by Michael Hamel
- */
-
-OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
-OUTPUT_ARCH(powerpc)
-STARTUP(start.o)
-ENTRY(download_entry)
-EXTERN(__vectors)
-
-RamBase = DEFINED(RamBase) ? RamBase : 0;
-RamSize = DEFINED(RamSize) ? RamSize : 256M;
-RamEnd = RamBase + RamSize;
-HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
-
-MEMORY {
-        RAM : ORIGIN = 0, LENGTH = 256M
-        /*FLASH : ORIGIN = 0xFFE00000, LENGTH = 16M*/
-}
-
-/*
- * Max sdata/bss.
- */
-bsp_section_small_data_area_size = 65536;
-
-SECTIONS
-{
-  /* First 16K is occupied by exception vectors and anything else we want to put there */
-  .text 0x4000:
-  {
-     text.start = . ;
-     *(.entry)
-     *(.entry2)
-     *(.text*)
-     *(.rodata*)
-     *(.rodata1)
-     KEEP (*(SORT(.rtemsroset.*)))
-
-     /*
-      * Special FreeBSD sysctl sections.
-      */
-     . = ALIGN (16);
-     __start_set_sysctl_set = .;
-     *(set_sysctl_*);
-     __stop_set_sysctl_set = ABSOLUTE(.);
-     *(set_domain_*);
-     *(set_pseudo_*);
-
-    /* C++ constructors/destructors */
-    *(.gnu.linkonce.t*)
-
-    /*  Initialization and finalization code.
-     *
-     *  Various files can provide initialization and finalization functions.
-     *  The bodies of these functions are in .init and .fini sections. We
-     *  accumulate the bodies here, and prepend function prologues from
-     *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
-     *  first; ecrtn.o must be linked last. Because these are wildcards, it
-     *  doesn't matter if the user does not actually link against ecrti.o and
-     *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
-     *  wildcard also means that it doesn't matter which directory ecrti.o
-     *  and ecrtn.o are in. 
-     */
-    PROVIDE (_init = .);
-    *ecrti.o(.init)
-    *(.init)
-    *ecrtn.o(.init)
-    
-    PROVIDE (_fini = .);
-    *ecrti.o(.fini)
-    *(.fini)
-    *ecrtn.o(.init)
-
-    KEEP (*ecrti.o(.ctors))
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *ecrtn.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*ecrti.o(.dtors))
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *ecrtn.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-
-    /* Exception frame info */
-     *(.eh_frame)
-    /* Miscellaneous read-only data */
-    _rodata_start = . ;
-    *(.gnu.linkonce.r*)
-    *(.lit)
-    *(.shdata)
-    *(.rodata)
-    *(.rodata1)
-    *(.descriptors)
-    *(rom_ver)
-    _erodata = .;
-
-    PROVIDE (__EXCEPT_START__ = .);
-    *(.gcc_except_table*)
-    PROVIDE (__EXCEPT_END__ = .);
-    __GOT_START__ = .;
-    s.got = .;
-    *(.got.plt) 
-    *(.got)
-    *(.got1)
-    PROVIDE (__GOT2_START__ = .);
-    PROVIDE (_GOT2_START_ = .);
-    *(.got2)
-    PROVIDE (__GOT2_END__ = .);
-    PROVIDE (_GOT2_END_ = .);
-    
-    PROVIDE (__FIXUP_START__ = .);
-    PROVIDE (_FIXUP_START_ = .);
-    *(.fixup)
-    PROVIDE (_FIXUP_END_ = .);
-    PROVIDE (__FIXUP_END__ = .);
-    
-
-    /* Various possible names for the end of the .text section */
-     etext = ALIGN(0x10);
-     _etext = .;
-
-     *(.lit)
-     *(.shdata)
-     _endtext = ALIGN(0x10);
-     text.end = .;
-     text.size = text.end - text.start;
-  } >RAM
-
-  text.size = text.end - text.start;
-
-  .tdata : {
-    _TLS_Data_begin = .;
-    *(.tdata .tdata.* .gnu.linkonce.td.*)
-    _TLS_Data_end = .;
-  } >RAM
-
-  .tbss : {
-    _TLS_BSS_begin = .;
-    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
-    _TLS_BSS_end = .;
-  } >RAM
-
-  _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
-  _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
-  _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
-  _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
-  _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
-  _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
-
-  .jcr : { KEEP (*(.jcr)) } >RAM
-
-    .rel.dyn : {
-      *(.rel.init)
-      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
-      *(.rel.fini)
-      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
-      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
-      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
-      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
-      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
-      *(.rel.ctors)
-      *(.rel.dtors)
-      *(.rel.got)
-      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
-      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
-      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
-      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
-      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
-    } >RAM
-    .rela.dyn : {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.got1)
-      *(.rela.got2)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-    } >RAM
-
-
-    /* Initialised large data */
-    .data ( . ) :
-    {
-      . = ALIGN (4);
-      data.start = .;
-      *(.data)
-      *(.data1)
-      KEEP (*(SORT(.rtemsrwset.*)))
-      *(.data.* .gnu.linkonce.d.*)
-      data.end = .;
-    } > RAM
-
-	/* Initialised small data addressed as offsets from r13 */
-	.sdata : {
-      . = ALIGN (4);
-	  PROVIDE (__SDATA_START__ = .);
-      bsp_section_sdata_begin = .;
-      sdata.start = .;
-	  *(.sdata*)
-      *(.gnu.linkonce.s.*)
-	  sdata.end = .;
-      bsp_section_sdata_end = .;
-	} > RAM
-
-	/* Zeroed small data addressed as offsets from r13 */
-   .sbss : {
-      . = ALIGN (4);
-	  PROVIDE(__SBSS_START__ = .);
-      bsp_section_sbss_begin = .;
-	  sbss.start = .;
-      *(.sbss .sbss.* *.gnu.linkonce.sb.*);
-	  sbss.end = .;
-      bsp_section_sbss_end = .;
-      bsp_section_sdata_libdl_begin = .;
-      . = DEFINED(bsp_section_small_data_area_size) ?
-            bsp_section_sdata_begin + bsp_section_small_data_area_size : .;
-      bsp_section_sdata_libdl_end = .;
-    } > RAM
-    PROVIDE(__SBSS_END__ = .);
-
-	/* Zeroed large data */
-	.bss : {
-      . = ALIGN (4);
-	  bss.start = .;
-      *(.bss .bss* .gnu.linkonce.b*)
-      . = ALIGN(4);
-      bss.end = .;
-    } > RAM
-
-    bss.size = bss.end - bss.start;
-    sbss.size = sbss.end - sbss.start;
-
-    .noinit (NOLOAD) : {
-        *(.noinit*)
-    } >RAM
-
-    .rtemsstack (NOLOAD) : {
-        *(SORT(.rtemsstack.*))
-    } >RAM
-
-    WorkAreaBase = .;
-
-	/* Debugging information */
-    .line 0 : { *(.line) }
-    .debug 0 : { *(.debug) }
-    .debug_sfnames 0 : { *(.debug_sfnames) }
-    .debug_srcinfo 0 : { *(.debug_srcinfo) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-    .debug_aregion 0 : { *(.debug_aregion) }
-    .debug_macinfo 0 : { *(.debug_macinfo) }
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-}
Index: ps/powerpc/haleakala/start/mmu_405.c
===================================================================
--- bsps/powerpc/haleakala/start/mmu_405.c	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,293 +1,0 @@
-/* 
- *  Simple interface to the PowerPC 405 MMU
- *
- *   Michael Hamel ADInstruments 2008
- *
-  */
-
-
-#include <bsp.h>
-#include <libcpu/powerpc-utility.h>
-#include "mmu_405.h"
-#include <inttypes.h>
-
-/* #define qLogTLB */
-/* #define qLogTLBDetails */
-
-
-/*----------------------------- TLB handling -------------------------------- */
-/* The following are in assembler in mmu_405asm.S  */
-extern  void MMU_GetTLBEntry(uint8_t index, uint32_t* tagword, uint32_t* dataword, uint8_t* pid);
-extern  void MMU_SetTLBEntry(uint8_t index, uint32_t hiword, uint32_t loword, uint8_t pid);
-extern  void MMU_ClearTLBs(void);
-extern  int16_t MMU_FindTLBEntry(uint32_t address);
-
-
-enum { kNTLBs = 64 };    /* for 403GCX and 405 */
-
-static bool    sFreeTLBs[kNTLBs];
-static uint8_t  sLastIndex = 0;
-static int    sNInUse = 0;
-
-static void MMUFault(const char* what)
-/* Used for all setup faults; these can't really be ignored */
-{
-  printk("\n>>>MMU fatal error %s\n",what);
-  rtems_fatal_error_occurred(RTEMS_INTERNAL_ERROR);
-}
-
-static uint8_t AllocTLB(void)
-{
-  uint8_t index;
-  
-  index = sLastIndex;
-  do {
-    index++;
-    if (index == kNTLBs)
-      index = 0;
-    if (index == sLastIndex)
-      MMUFault("TLB table full");
-  } while (! sFreeTLBs[index]);
-  sFreeTLBs[index] = false;
-  sLastIndex = index;
-  sNInUse++;
-  return index;
-}
-
-static void FreeTLB(uint8_t index)
-{
-  MMU_SetTLBEntry(index,0,0,0);
-  sFreeTLBs[index] = true;
-  sLastIndex = index-1;
-  sNInUse--;
-}
-
-
-/*---------------------------- MMU operations ---------------------------------- */
-
-int DataMissException(BSP_Exception_frame *f, unsigned int vector);
-int InstructionMissException(BSP_Exception_frame *f, unsigned int vector);
-int InstructionFetchException(BSP_Exception_frame *f, unsigned int vector);
-void mmu_initialise(void);
-int mmu_get_tlb_count(void);
-uint8_t  mmu_new_processID(void);
-uint8_t mmu_current_processID(void);
-
-void
-mmu_initialise(void)
-/* Clear the TLBs and set up exception handlers for the MMU miss handlers */
-{
-  int i;
-  
-  MMU_ClearTLBs();
-  for (i=0; i<kNTLBs; i++) {
-    sFreeTLBs[i] = true;
-    MMU_SetTLBEntry(i,0,0,0xFF);
-  }
-  ppc_exc_set_handler(ASM_ISI_VECTOR ,InstructionFetchException);
-  ppc_exc_set_handler(ASM_BOOKE_ITLBMISS_VECTOR ,DataMissException);
-  ppc_exc_set_handler(ASM_BOOKE_DTLBMISS_VECTOR ,InstructionMissException);
-}
-
-static void
-MakeTLBEntries(uint32_t startAt, uint32_t nBytes, bool EX, bool WR, bool I, uint8_t PID)
-{
-  uint32_t mask, options, tagWord, dataWord;
-  uint8_t   index, sizeCode, pid;
-  
-  if ((startAt & 0x3FF) != 0)
-    MMUFault("TLB entry not on 1K boundary");
-  if ((nBytes & 0x3FF) != 0)
-    MMUFault("TLB size not on 1K boundary");
-    
-  options = 0;
-  if (EX) options += 0x200;
-  if (WR) options += 0x100;
-  if (I) options += 5;
-  
-  #ifdef qLogTLB
-    printk("TLB: make entries for $%X bytes from $%X..$%X PID %d",nBytes, startAt, startAt+nBytes-1, PID);
-    if (EX) printk(" EX");
-    if (WR) printk(" WR");
-    if (I) printk(" I");
-    printk("\n");
-  #endif
-  
-  while (nBytes > 0) {
-    /* Find the largest block we can base on this address */
-    mask = 0x3FF;
-    sizeCode = 0;
-    while (mask < nBytes && ((startAt & mask)==0) && sizeCode < 8) {
-      mask = (mask<<2) + 3;
-      sizeCode++;
-    }
-    mask >>= 2;
-    sizeCode--;
-    
-    /* Make a TLB entry describing this, ZSEL=0 */
-    tagWord = startAt | (sizeCode<<7) | 0x40;
-    dataWord = startAt | options;
-    index = AllocTLB();
-    MMU_SetTLBEntry( index , tagWord, dataWord, PID);
-    
-    {
-      /* Paranoia: check that we can read that back... */
-      uint8_t tdex, oldpid;
-      
-      oldpid = mmu_current_processID();
-      mmu_set_processID(PID);
-      tdex = MMU_FindTLBEntry(startAt);
-      mmu_set_processID(oldpid);
-      
-      if (tdex != index) {
-        printk(" Add TLB %d: At %" PRIx32 " for $%" PRIx32
-               " sizecode %d tagWord $%" PRIx32 "  ",
-               index, startAt, mask+1,sizeCode,tagWord);
-        printk(" -- find failed, %d/%d!\n",tdex,index);
-        MMU_GetTLBEntry(index, &tagWord, &dataWord, &pid);
-        printk(" -- reads back $%" PRIx32 " : $%" PRIx32
-               ", PID %d\n",tagWord,dataWord,pid);
-      } else {
-        #ifdef qLogTLBDetails
-        printk(" Add TLB %d: At %X for $%X sizecode %d tagWord $%X\n",index, startAt, mask+1,sizeCode,tagWord);
-        #endif
-      }
-    }
-  
-    /* Subtract block from startAddr and nBytes */
-    mask++;    /* Convert to a byte count */
-    startAt += mask;
-    nBytes -= mask;
-  }
-  #ifdef qLogTLB
-    printk(" %d in use\n",sNInUse);
-  #endif
-}
-
-void
-mmu_remove_space(uint32_t startAt, uint32_t endAt)
-{
-  int16_t index;
-  int32_t size;
-  uint32_t tagword, dataword, nBytes;
-  uint8_t  pid, sCode;
-  
-  nBytes = endAt - startAt;
-  
-  #ifdef qLogTLB
-  printk("TLB: delete entries for $%X bytes from $%X\n",nBytes,startAt);
-  #endif
-  
-  while (nBytes > 0) {
-    index = MMU_FindTLBEntry( (uint32_t)startAt );
-    size = 1024;
-    if (index >= 0) {
-      MMU_GetTLBEntry(index, &tagword, &dataword, &pid);
-      if ((tagword & 0x40) == 0)
-        MMUFault("Undefine failed: redundant entries?");
-      if ((tagword & 0xFFFFFC00) != (uint32_t)startAt)
-        MMUFault("Undefine not on TLB boundary");
-      FreeTLB(index);
-      sCode = (tagword >> 7) & 7;
-      while (sCode > 0) {
-        size <<= 2;
-        sCode--;
-      }
-      #ifdef qLogTLBDetails
-      printk(" Free TLB %d: At %X for $%X\n",index, startAt, size);
-      #endif
-    }
-    startAt += size;
-    nBytes -= size;
-  }
-}
-
-void
-mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID)
-/* Convert accesstype to write-enable, executable, and cache-inhibit bits */
-{
-  bool EX, WR, I;
-  
-  EX = false;
-  WR = false;
-  I = false;
-  switch (permissions) {
-    case executable     : EX = true;  break;
-    case readOnlyData     : break;
-    case readOnlyNoCache   : I = true; break;
-    case readWriteData     : WR = true; break;
-    case readWriteNoCache   : WR = true; I= true; break;
-    case readWriteExecutable: WR = true; EX = true; break;
-  }
-  MakeTLBEntries( (uint32_t)startAddr, (uint32_t)(endAddr-startAddr+1), EX, WR, I, processID);
-}
-
-int
-mmu_get_tlb_count(void)
-{
-  return sNInUse;
-}
-
-/*---------------------------- CPU process ID handling ----------------------------------
- * Really dumb system where we just hand out sequential numbers and eventually fail
- * As long as we only use 8-9 processes this isn't a problem */
-
-static uint8_t sNextPID = 1;
-
-#define SPR_PID    0x3B1
-
-uint8_t  mmu_new_processID(void)
-{
-  return sNextPID++;
-}
-
-void mmu_free_processID(uint8_t freeThis)
-{
-}
-
-uint8_t mmu_current_processID(void)
-{
-  return PPC_SPECIAL_PURPOSE_REGISTER(SPR_PID);
-}
-
-uint8_t mmu_set_processID(uint8_t newID)
-{
-  uint8_t prev = mmu_current_processID();
-  PPC_SET_SPECIAL_PURPOSE_REGISTER(SPR_PID,newID);
-  return prev;
-}
-
-
-/* ------------------ Fault handlers ------------------ */
-
-#define SPR_ESR    0x3D4
-#define SPR_DEAR  0x3D5
-
-enum { kESR_DST = 0x00800000 };
-
-int DataMissException(BSP_Exception_frame *f, unsigned int vector)
-{
-  uint32_t addr, excSyn;
-  
-  addr = PPC_SPECIAL_PURPOSE_REGISTER(SPR_DEAR);
-  excSyn  = PPC_SPECIAL_PURPOSE_REGISTER(SPR_ESR);
-  if (excSyn & kESR_DST) printk("\n---Data write to $%" PRIx32
-      " attempted at $%" PRIxPTR "\n",addr,f->EXC_SRR0);
-            else printk("\n---Data read from $%" PRIx32 " attempted at $%"
-                        PRIxPTR "\n",addr,f->EXC_SRR0);
-  return -1;
-}
-
-int InstructionMissException(BSP_Exception_frame *f, unsigned int vector)
-{
-  printk("\n---Instruction fetch attempted from $%" PRIxPTR ", no TLB exists\n",
-         f->EXC_SRR0);
-  return -1;
-}
-
-int InstructionFetchException(BSP_Exception_frame *f, unsigned int vector)
-{
-  printk("\n---Instruction fetch attempted from $%" PRIxPTR
-         ", TLB is no-execute\n",f->EXC_SRR0);
-  return -1;
-}
Index: ps/powerpc/haleakala/start/mmu_405asm.S
===================================================================
--- bsps/powerpc/haleakala/start/mmu_405asm.S	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,83 +1,0 @@
-/*
-
-Low-level interface to the PPC405 MMU
-
-M.Hamel ADInstruments 2008
-
-*/
-
-#include <rtems/asm.h>
-
-/* Useful MMU SPR values */
-
-#define SPR_ZPR		0x3B0
-#define SPR_PID		0x3B1
-
-			.text
-
-/* void MMU_ClearTLBs(); */
-			PUBLIC_VAR(MMU_ClearTLBs)
-SYM (MMU_ClearTLBs):
-			tlbia
-			isync
-			lis		r3,0x5555		// *** Gratuitous fiddle of ZPR to 0101010101 to take it out of 
-			mtspr	SPR_ZPR,r3		// the picture
-			blr
-			
-/* void MMU_SetTLBEntry(UInt8 index, UInt32 tagword, UInt32 dataword, UInt8 SPR_PID) */
-			PUBLIC_VAR(MMU_SetTLBEntry)
-SYM (MMU_SetTLBEntry):
-			mfspr	r7,SPR_PID		// Save the current SPR_PID
-			mtspr	SPR_PID,r6		// Write to SPR_PID
-			tlbwehi	r4,r3			// Write hiword
-			mtspr	SPR_PID,r7		// Restore the SPR_PID
-			tlbwelo	r5,r3			// Write loword
-			isync
-			blr
-
-/* void MMU_GetTLBEntry(UInt8 index, UInt32& tagword, UInt32& dataword, UInt8& SPR_PID) */
-			PUBLIC_VAR(MMU_GetTLBEntry)
-SYM (MMU_GetTLBEntry):		
-			mfspr	r7,SPR_PID		// Save the current SPR_PID
-			tlbrehi	r8,r3			// Read hiword & SPR_PID
-			mfspr	r9,SPR_PID		// Copy the SPR_PID
-			mtspr	SPR_PID,r7		// Restore original SPR_PID so we can proceed
-			stw		r8,0(r4)		// Write to r4 pointer
-			stb		r9,0(r6)		// Write to r6 pointer
-			tlbrelo	r8,r3			// Read loword
-			stw		r8,0(r5)		// Write to r5 pointer
-			blr
-			
-/* SInt16 MMU_FindTLBEntry(UInt32 address) */
-/* Returns index of covering TLB entry (0..63), or -1 if there isn't one */
-			PUBLIC_VAR(MMU_FindTLBEntry)
-SYM (MMU_FindTLBEntry):		
-			tlbsx.	r3,0,r3
-			beqlr
-			li		r3,0xFFFFFFFF
-			blr
-
-/* bool		mmu_enable_code(bool enable); */
-			PUBLIC_VAR(mmu_enable_code)
-SYM (mmu_enable_code):	
-			li		r5,0x20	// IR bit
-			b		msrbits
-			
-/* bool		mmu_enable_data(bool enable); */
-			PUBLIC_VAR(mmu_enable_data)
-SYM (mmu_enable_data):	
-			li		r5,0x10		// DR bit
-msrbits:	cmpwi	r3,0			// Common code: parameter 0?
-			mfmsr	r4				// r4 = MSR state
-			beq		clrBit
-			or		r6,r4,r5		// If 1, r6 = MSR with bit set
-			b		setmsr
-clrBit:		andc	r6,r4,r5		// If 0 r6 = MSR with bit clear
-setmsr:		mtmsr	r6				// Write new MSR
-			and.	r3,r4,r5		// Result = old MSR bit
-			beqlr						// If zero return zero
-			li		r3,0xFF		// If nonzero return byte -1
-			blr
-	
-			
-			
Index: ps/powerpc/haleakala/start/start.S
===================================================================
--- bsps/powerpc/haleakala/start/start.S	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,237 +1,0 @@
-/*  dlentry.s
- *
- *  This file contains the entry code for RTEMS programs starting
- *  after download to RAM
- *
- *  Author:	Thomas Doerfler <td@imd.m.isar.de>
- *              IMD Ingenieurbuero fuer Microcomputertechnik
- *
- *  COPYRIGHT (c) 1998 by IMD
- *
- *  Changes from IMD are covered by the original distributions terms.
- *  This file has been derived from the papyrus BSP:
- *
- *  This file contains the entry veneer for RTEMS programs
- *  downloaded to Papyrus.
- *
- *  Author:	Andrew Bray <andy@i-cubed.co.uk>
- *
- *  COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of i-cubed limited not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      i-cubed limited makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  derived from "helas403/dlentry.S":
- *
- *  Further changes to derive for the PPC405CR/GP/GPr/EX/EXr
- *  by Michael Hamel ADInstruments Ltd 2008
- */
-
-#include <rtems/asm.h>
-
-/*
- *  The virtex ELF link scripts support three special sections:
- *    .entry    The actual entry point
- *    .vectors  The section containing the interrupt entry veneers.
- */
-
-/*
- *  Downloaded code loads the vectors separately to 0x00000100,
- *  so .entry can be over 256 bytes.
- *
- *  The other sections are linked in the following order:
- *    .entry
- *    .text
- *    .data
- *    .bss
- * see linker command file for section placement
- *
- *  The initial stack is set to _ISR_Stack_area_end.
- *
- *  All the entry veneer has to do is to clear the BSS.
- */
-
-/*
- *  GDB likes to have debugging information for the entry veneer.
- *  Here was some DWARF information. IMD removed it, because we
- *  could not check, whether it was still correct. Sorry.
-
- */
-
-
-			.section .entry
-
-			PUBLIC_VAR (start)
-			PUBLIC_VAR (download_entry)
-			PUBLIC_VAR (__rtems_entry_point)
-
-SYM(start):
-SYM(download_entry):
-SYM(__rtems_entry_point):
-
-			.extern SYM (boot_card)
-
-			bl	.startup		/* First word is branch to reset_entry */
-
-
-/*---------------------------------------------------------------------------
- * Parameters from linker
- *--------------------------------------------------------------------------*/
-
-base_addr:
-toc_pointer:
-		.long	s.got
-bss_length:
-		.long	bss.size
-bss_addr:
-		.long	bss.start
-sbss_length:
-		.long	sbss.size
-sbss_addr:
-		.long	sbss.start
-stack_top:
-		.long	_ISR_Stack_area_end
-PUBLIC_VAR (text_addr)
-text_addr:
-        .long   text.start
-PUBLIC_VAR (text_length)
-text_length:
-        .long   text.size
-
-/*---------------------------------------------------------------------------
- * Reset_entry.
- *--------------------------------------------------------------------------*/
-.startup:
-			/* Get entrypoint address in R1 so we can find linker variables */
-			mflr	r1
-
-			/* Initialise procesor registers generally */
-			bl		init405
-
-			/* Clear .bss and .sbss */
-			bl		bssclr
-
-			/*-------------------------------------------------------------------
-			 * C_setup.
-			 *------------------------------------------------------------------*/
-			lwz     r1,stack_top - base_addr(r1)         /* Now set R1 to stack_top */
-			addi    r1,r1,-56-4         /* start stack at text_addr - 56 */
-			li		r3,0
-			stw		r3, 0(r1)			/* Clear stack chain */
-			stw		r3, 4(r1)
-			stw		r3, 8(r1)
-			stw		r3, 12(r1)
-
-			bl		__eabi				/* Initialise EABI: sets up r2 & r13 */
-
-			li		r3, 0			/* command line */
-
-			b       SYM (boot_card) 	 /* call the first C routine */
-
-/*---------------------------------------------------------------------------
- * bssclr.
- *--------------------------------------------------------------------------*/
-bssclr:		lwz     r2,bss_addr-base_addr(r1)   /* start of bss set by loader */
-			lwz     r3,bss_length-base_addr(r1) /* bss length */
-			srwi.	r3,r3,2		/* div 4 to get # of words */
-			li		r0,0
-			beq		dosbss					/* no bss */
-			mtctr   r3                      /* set ctr reg */
-			subi	r2,r2,4
-clear_bss:	stwu	r0,4(r2)
-			bdnz    clear_bss               /* decrement counter and loop */
-
-dosbss:		lwz     r2,sbss_addr-base_addr(r1)   /* start of sbss set by loader */
-			lwz     r3,sbss_length-base_addr(r1) /* sbss length */
-			slwi.	r3,r3,2					/* div 4 to get # of words */
-			subi	r2,r2,4
-			beqlr                           /* no sbss */
-			mtctr   r3                      /* set ctr reg */
-clear_sbss:	stwu	r0,4(r2)
-			bdnz    clear_sbss               /* decrement counter and loop */
-
-			blr                             /* return */
-
-
-/*---------------------------------------------------------------------------
- * Generic 405 register setup
- *--------------------------------------------------------------------------*/
-init405:
-			li		r0, 0
-			mtmsr	r0
-			mticcr	r0
-			mtdccr	r0
-
-			li		r3,0x7FFC	# 405EX-specific
-			mtsgr	r3			# Clear guarded mode on all storage except PCIe region
-
-			mtsler	r0			# Storage is all big-endian
-			mtsu0r	r0			# and uncompressed
-
-			iccci	r3,0			# Invalidate the instruction cache
-			li		r3,1			# Enable F800 0000 to FFFF FFFF
-			oris	r3,r3,0xC000	# Enable 0000 0000 to 0FFF FFFF
-			mticcr	r3
-			isync
-
-			li		r3,0
-			li		r4,256		# 405 has 128 or 256 32-byte lines: do 256
-			mtctr	r4			# set loop ctr
-dcloop:		dccci	0,r3		# invalidate line
-			addi	r3,r3,0x20	# bump to next line
-			bdnz	dcloop
-			mtdcwr	r0			# Select write-back caching
-			lis		r3,0xC000	# Enable 0000 0000 to 0FFF FFFF
-			# mtdccr	r3			# Enable data cache
-
-			mtevpr	r0
-			mtesr	r0
-			mtxer	r0
-
-			lwarx   r3,r0,r0		# get some data/set resv bit
-			stwcx.	r3,r0,r0		# store out and clear resv bit
-
-			lis		r3,0xDEAD
-			ori		r3,r3,0xBEEF	# Make distintive uninitialised value
-			mr		r4, r3
-			mr		r5, r3
-			mr		r6, r3
-			mr		r7, r3
-			mr		r8, r3
-			mr		r9, r3
-			mr		r10, r3
-			mr		r11, r3
-			mr		r12, r3
-			mr		r13, r3
-			mr		r14, r3
-			mr		r15, r3
-			mr		r16, r3
-			mr		r17, r3
-			mr		r18, r3
-			mr		r19, r3
-			mr		r20, r3
-			mr		r21, r3
-			mr		r22, r3
-			mr		r23, r3
-			mr		r24, r3
-			mr		r25, r3
-			mr		r26, r3
-			mr		r27, r3
-			mr		r28, r3
-			mr		r29, r3
-			mr		r30, r3
-			mr		r31, r3
-
-			blr
-
-.L_text_e:
-
-			.comm	environ,4,4
Index: spec/build/bsps/optconsolebaud.yml
===================================================================
--- spec/build/bsps/optconsolebaud.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ spec/build/bsps/optconsolebaud.yml	(revision e92bc254530825ae14646520b35efe000699ce74)
@@ -14,5 +14,4 @@
   - powerpc/hsc_cm01
   - powerpc/beatnik
-  - powerpc/haleakala
   - powerpc/mvme3100
   - powerpc/mvme5500
Index: ec/build/bsps/powerpc/haleakala/abi.yml
===================================================================
--- spec/build/bsps/powerpc/haleakala/abi.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,18 +1,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-string: null
-- split: null
-- env-append: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default:
-- -Dppc405
-- -mcpu=405
-default-by-variant: []
-description: |
-  ABI flags
-enabled-by: true
-links: []
-name: ABI_FLAGS
-type: build
Index: ec/build/bsps/powerpc/haleakala/bsphaleakala.yml
===================================================================
--- spec/build/bsps/powerpc/haleakala/bsphaleakala.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,72 +1,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-arch: powerpc
-bsp: haleakala
-build-type: bsp
-cflags: []
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-cppflags: []
-enabled-by: true
-family: haleakala
-includes: []
-install:
-- destination: ${BSP_INCLUDEDIR}
-  source:
-  - bsps/powerpc/haleakala/include/bsp.h
-  - bsps/powerpc/haleakala/include/mmu_405.h
-  - bsps/powerpc/haleakala/include/tm27.h
-- destination: ${BSP_INCLUDEDIR}/bsp
-  source:
-  - bsps/powerpc/haleakala/include/bsp/irq.h
-- destination: ${BSP_LIBDIR}
-  source:
-  - bsps/powerpc/haleakala/start/linkcmds
-links:
-- role: build-dependency
-  uid: ../../obj
-- role: build-dependency
-  uid: ../../objirqdflt
-- role: build-dependency
-  uid: ../../opto1
-- role: build-dependency
-  uid: ../crti
-- role: build-dependency
-  uid: ../crtn
-- role: build-dependency
-  uid: ../grp
-- role: build-dependency
-  uid: abi
-- role: build-dependency
-  uid: ../../optconsolebaud
-- role: build-dependency
-  uid: optsprg
-- role: build-dependency
-  uid: optvecbase
-- role: build-dependency
-  uid: start
-- role: build-dependency
-  uid: ../obj
-- role: build-dependency
-  uid: ../objexc
-- role: build-dependency
-  uid: ../../objmem
-- role: build-dependency
-  uid: ../../bspopts
-source:
-- bsps/powerpc/haleakala/irq/irq.c
-- bsps/powerpc/haleakala/irq/irq_init.c
-- bsps/powerpc/haleakala/start/bspstart.c
-- bsps/powerpc/haleakala/start/mmu_405.c
-- bsps/powerpc/haleakala/start/mmu_405asm.S
-- bsps/powerpc/shared/btimer/btimer-ppc-dec.c
-- bsps/powerpc/shared/cache/cache.c
-- bsps/powerpc/shared/clock/clock-ppc403.c
-- bsps/powerpc/shared/console/console.c
-- bsps/powerpc/shared/console/uart.c
-- bsps/powerpc/shared/irq/ppc-irq-legacy.c
-- bsps/shared/dev/getentropy/getentropy-cpucounter.c
-- bsps/shared/start/bspfatal-default.c
-- bsps/shared/start/bspreset-loop.c
-- bsps/shared/start/gettargethash-default.c
-- bsps/shared/start/sbrk.c
-type: build
Index: ec/build/bsps/powerpc/haleakala/optsprg.yml
===================================================================
--- spec/build/bsps/powerpc/haleakala/optsprg.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,15 +1,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
-description: |
-  If defined, then the PowerPC specific code in RTEMS will use some of the special purpose registers to slightly optimize interrupt response time.  The use of these registers can conflict with other tools like debuggers.
-enabled-by: true
-links: []
-name: PPC_USE_SPRG
-type: build
Index: ec/build/bsps/powerpc/haleakala/optvecbase.yml
===================================================================
--- spec/build/bsps/powerpc/haleakala/optvecbase.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,16 +1,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-integer: null
-- define: null
-build-type: option
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 256
-default-by-variant: []
-description: |
-  This defines the base address of the exception table.  NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.
-enabled-by: true
-format: '{:#010x}'
-links: []
-name: PPC_VECTOR_FILE_BASE
-type: build
Index: ec/build/bsps/powerpc/haleakala/start.yml
===================================================================
--- spec/build/bsps/powerpc/haleakala/start.yml	(revision 98ab69323ea3799dbd1c418517c72526af699c5a)
+++ 	(revision )
@@ -1,14 +1,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-asflags: []
-build-type: start-file
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-cppflags: []
-enabled-by: true
-includes: []
-install-path: ${BSP_LIBDIR}
-links: []
-source:
-- bsps/powerpc/haleakala/start/start.S
-target: start.o
-type: build
