Changeset e80ac7f6 in rtems for cpukit/score


Ignore:
Timestamp:
Apr 18, 2002, 1:18:11 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
0117487
Parents:
383e974
Message:

2002-04-18 Jay Monkman <jtm@…>

  • rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them where they correctly inform the compiler about the register they are modifying.
Location:
cpukit/score/cpu/arm
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/ChangeLog

    r383e974 re80ac7f6  
     12002-04-18      Jay Monkman <jtm@smoothsmoothie.com>
     2
     3        * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them
     4        where they correctly inform the compiler about the register they
     5        are modifying.
     6
    172001-04-03      Joel Sherrill <joel@OARcorp.com>
    28
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r383e974 re80ac7f6  
    541541  { \
    542542    (_level) = 0; \
    543     asm volatile ("MRS  r0, cpsr \n" ); \
    544     asm volatile ("ORR  r0, r0, #0xc0 \n" ); \
    545     asm volatile ("MSR  cpsr, r0 \n" ); \
     543   asm volatile ("MRS r0, cpsr          \n"  \
     544                 "ORR  r0, r0, #0xc0    \n" \
     545                 "MSR  cpsr, r0         \n" \
     546                   : : : "r0"); \
    546547  }
    547548
     
    554555#define _CPU_ISR_Enable( _level )  \
    555556  { \
    556     asm volatile ("MRS  r0, cpsr \n" ); \
    557     asm volatile ("AND  r0, r0, #0xFFFFFF3F \n" ); \
    558     asm volatile ("MSR  cpsr, r0 \n" ); \
     557   asm volatile ("MRS r0, cpsr                  \n"  \
     558                 "AND  r0, r0, #0xFFFFFF3F      \n" \
     559                 "MSR  cpsr, r0                 \n" \
     560                 : : : "r0" ); \
    559561  }
    560562 
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